Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/a8xx: Fix the ticks used in submit traces
GMU_ALWAYS_ON_COUNTER_* registers got moved in A8x, but currently, A6x
register offsets are used in the submit traces instead of A8x offsets.
To fix this, refactor a bit and use adreno_gpu->funcs->get_timestamp()
everywhere.
While we are at it, update a8xx_gmu_get_timestamp() to use the GMU AO
counter.
Fixes: 288a93200892 ("drm/msm/adreno: Introduce A8x GPU Support")
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/714655/
Message-ID: <20260327-a8xx-gpu-batch2-v2-2-2b53c38d2101@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
authored by
Akhil P Oommen
and committed by
Rob Clark
cfc8b486
dc78b35d
+27
-44
+2
-4
drivers/gpu/drm/msm/adreno/a4xx_gpu.c
+2
-4
drivers/gpu/drm/msm/adreno/a4xx_gpu.c
···
604
604
return 0;
605
605
}
606
606
607
-
static int a4xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
607
+
static u64 a4xx_get_timestamp(struct msm_gpu *gpu)
608
608
{
609
-
*value = gpu_read64(gpu, REG_A4XX_RBBM_PERFCTR_CP_0_LO);
610
-
611
-
return 0;
609
+
return gpu_read64(gpu, REG_A4XX_RBBM_PERFCTR_CP_0_LO);
612
610
}
613
611
614
612
static u64 a4xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate)
+2
-4
drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+2
-4
drivers/gpu/drm/msm/adreno/a5xx_gpu.c
···
1435
1435
return 0;
1436
1436
}
1437
1437
1438
-
static int a5xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
1438
+
static u64 a5xx_get_timestamp(struct msm_gpu *gpu)
1439
1439
{
1440
-
*value = gpu_read64(gpu, REG_A5XX_RBBM_ALWAYSON_COUNTER_LO);
1441
-
1442
-
return 0;
1440
+
return gpu_read64(gpu, REG_A5XX_RBBM_ALWAYSON_COUNTER_LO);
1443
1441
}
1444
1442
1445
1443
struct a5xx_crashdumper {
+7
-16
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+7
-16
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
···
16
16
17
17
#define GPU_PAS_ID 13
18
18
19
-
static u64 read_gmu_ao_counter(struct a6xx_gpu *a6xx_gpu)
19
+
static u64 a6xx_gmu_get_timestamp(struct msm_gpu *gpu)
20
20
{
21
+
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
22
+
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
21
23
u64 count_hi, count_lo, temp;
22
24
23
25
do {
···
406
404
OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence)));
407
405
OUT_RING(ring, submit->seqno);
408
406
409
-
trace_msm_gpu_submit_flush(submit, read_gmu_ao_counter(a6xx_gpu));
407
+
trace_msm_gpu_submit_flush(submit, adreno_gpu->funcs->get_timestamp(gpu));
410
408
411
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a6xx_flush(gpu, ring);
412
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}
···
616
614
}
617
615
618
616
619
-
trace_msm_gpu_submit_flush(submit, read_gmu_ao_counter(a6xx_gpu));
617
+
trace_msm_gpu_submit_flush(submit, adreno_gpu->funcs->get_timestamp(gpu));
620
618
621
619
a6xx_flush(gpu, ring);
622
620
···
2416
2414
return 0;
2417
2415
}
2418
2416
2419
-
static int a6xx_gmu_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
2417
+
static u64 a6xx_get_timestamp(struct msm_gpu *gpu)
2420
2418
{
2421
-
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
2422
-
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
2423
-
2424
-
*value = read_gmu_ao_counter(a6xx_gpu);
2425
-
2426
-
return 0;
2427
-
}
2428
-
2429
-
static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
2430
-
{
2431
-
*value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER);
2432
-
return 0;
2419
+
return gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER);
2433
2420
}
2434
2421
2435
2422
static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu)
+1
-1
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+1
-1
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
···
320
320
void a8xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool gx_off);
321
321
int a8xx_fault_handler(void *arg, unsigned long iova, int flags, void *data);
322
322
void a8xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
323
-
int a8xx_gmu_get_timestamp(struct msm_gpu *gpu, uint64_t *value);
323
+
u64 a8xx_gmu_get_timestamp(struct msm_gpu *gpu);
324
324
u64 a8xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate);
325
325
int a8xx_gpu_feature_probe(struct msm_gpu *gpu);
326
326
void a8xx_gpu_get_slice_info(struct msm_gpu *gpu);
+8
-12
drivers/gpu/drm/msm/adreno/a8xx_gpu.c
+8
-12
drivers/gpu/drm/msm/adreno/a8xx_gpu.c
···
1184
1184
gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
1185
1185
}
1186
1186
1187
-
int a8xx_gmu_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
1187
+
u64 a8xx_gmu_get_timestamp(struct msm_gpu *gpu)
1188
1188
{
1189
1189
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1190
1190
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1191
+
u64 count_hi, count_lo, temp;
1191
1192
1192
-
mutex_lock(&a6xx_gpu->gmu.lock);
1193
+
do {
1194
+
count_hi = gmu_read(&a6xx_gpu->gmu, REG_A8XX_GMU_ALWAYS_ON_COUNTER_H);
1195
+
count_lo = gmu_read(&a6xx_gpu->gmu, REG_A8XX_GMU_ALWAYS_ON_COUNTER_L);
1196
+
temp = gmu_read(&a6xx_gpu->gmu, REG_A8XX_GMU_ALWAYS_ON_COUNTER_H);
1197
+
} while (unlikely(count_hi != temp));
1193
1198
1194
-
/* Force the GPU power on so we can read this register */
1195
-
a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);
1196
-
1197
-
*value = gpu_read64(gpu, REG_A8XX_CP_ALWAYS_ON_COUNTER);
1198
-
1199
-
a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);
1200
-
1201
-
mutex_unlock(&a6xx_gpu->gmu.lock);
1202
-
1203
-
return 0;
1199
+
return (count_hi << 32) | count_lo;
1204
1200
}
1205
1201
1206
1202
u64 a8xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate)
+2
-4
drivers/gpu/drm/msm/adreno/adreno_gpu.c
+2
-4
drivers/gpu/drm/msm/adreno/adreno_gpu.c
···
391
391
return 0;
392
392
case MSM_PARAM_TIMESTAMP:
393
393
if (adreno_gpu->funcs->get_timestamp) {
394
-
int ret;
395
-
396
394
pm_runtime_get_sync(&gpu->pdev->dev);
397
-
ret = adreno_gpu->funcs->get_timestamp(gpu, value);
395
+
*value = adreno_gpu->funcs->get_timestamp(gpu);
398
396
pm_runtime_put_autosuspend(&gpu->pdev->dev);
399
397
400
-
return ret;
398
+
return 0;
401
399
}
402
400
return -EINVAL;
403
401
case MSM_PARAM_PRIORITIES:
+1
-1
drivers/gpu/drm/msm/adreno/adreno_gpu.h
+1
-1
drivers/gpu/drm/msm/adreno/adreno_gpu.h
···
75
75
struct adreno_gpu_funcs {
76
76
struct msm_gpu_funcs base;
77
77
struct msm_gpu *(*init)(struct drm_device *dev);
78
-
int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
78
+
u64 (*get_timestamp)(struct msm_gpu *gpu);
79
79
void (*bus_halt)(struct adreno_gpu *adreno_gpu, bool gx_off);
80
80
int (*mmu_fault_handler)(void *arg, unsigned long iova, int flags, void *data);
81
81
};
+4
-2
drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
+4
-2
drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
···
141
141
<reg32 offset="0x1f9f0" name="GMU_BOOT_KMD_LM_HANDSHAKE"/>
142
142
<reg32 offset="0x1f957" name="GMU_LLM_GLM_SLEEP_CTRL"/>
143
143
<reg32 offset="0x1f958" name="GMU_LLM_GLM_SLEEP_STATUS"/>
144
-
<reg32 offset="0x1f888" name="GMU_ALWAYS_ON_COUNTER_L"/>
145
-
<reg32 offset="0x1f889" name="GMU_ALWAYS_ON_COUNTER_H"/>
144
+
<reg32 offset="0x1f888" name="GMU_ALWAYS_ON_COUNTER_L" variants="A6XX-A7XX"/>
145
+
<reg32 offset="0x1f840" name="GMU_ALWAYS_ON_COUNTER_L" variants="A8XX-"/>
146
+
<reg32 offset="0x1f889" name="GMU_ALWAYS_ON_COUNTER_H" variants="A6XX-A7XX"/>
147
+
<reg32 offset="0x1f841" name="GMU_ALWAYS_ON_COUNTER_H" variants="A8XX-"/>
146
148
<reg32 offset="0x1f8c3" name="GMU_GMU_PWR_COL_KEEPALIVE" variants="A6XX-A7XX"/>
147
149
<reg32 offset="0x1f7e4" name="GMU_GMU_PWR_COL_KEEPALIVE" variants="A8XX-"/>
148
150
<reg32 offset="0x1f8c4" name="GMU_PWR_COL_PREEMPT_KEEPALIVE" variants="A6XX-A7XX"/>