Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915: Extract South chicken registers from i915_reg.h to display
Extract South Chicken registers from i915_reg.h to display header.
This allows intel_pch_refclk.c not to include i915_reg.h
v3: Drop whitespace changes, commit header updated (Jani)
v2: Drop common header in include and use display_regs.h (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patch.msgid.link/20260205094341.1882816-3-uma.shankar@intel.com
+27
-28
+27
drivers/gpu/drm/i915/display/intel_display_regs.h
+27
drivers/gpu/drm/i915/display/intel_display_regs.h
···
2871
2871
#define SFUSE_STRAP_DDIC_DETECTED (1 << 1)
2872
2872
#define SFUSE_STRAP_DDID_DETECTED (1 << 0)
2873
2873
2874
+
#define SOUTH_CHICKEN1 _MMIO(0xc2000)
2875
+
#define FDIA_PHASE_SYNC_SHIFT_OVR 19
2876
+
#define FDIA_PHASE_SYNC_SHIFT_EN 18
2877
+
#define INVERT_DDIE_HPD REG_BIT(28)
2878
+
#define INVERT_DDID_HPD_MTP REG_BIT(27)
2879
+
#define INVERT_TC4_HPD REG_BIT(26)
2880
+
#define INVERT_TC3_HPD REG_BIT(25)
2881
+
#define INVERT_TC2_HPD REG_BIT(24)
2882
+
#define INVERT_TC1_HPD REG_BIT(23)
2883
+
#define INVERT_DDID_HPD (1 << 18)
2884
+
#define INVERT_DDIC_HPD (1 << 17)
2885
+
#define INVERT_DDIB_HPD (1 << 16)
2886
+
#define INVERT_DDIA_HPD (1 << 15)
2887
+
#define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
2888
+
#define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
2889
+
#define FDI_BC_BIFURCATION_SELECT (1 << 12)
2890
+
#define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
2891
+
#define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
2892
+
#define SBCLK_RUN_REFCLK_DIS (1 << 7)
2893
+
#define ICP_SECOND_PPS_IO_SELECT REG_BIT(2)
2894
+
#define SPT_PWM_GRANULARITY (1 << 0)
2895
+
#define SOUTH_CHICKEN2 _MMIO(0xc2004)
2896
+
#define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13)
2897
+
#define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12)
2898
+
#define LPT_PWM_GRANULARITY (1 << 5)
2899
+
#define DPLS_EDP_PPS_FIX_DIS (1 << 0)
2900
+
2874
2901
/* Gen4+ Timestamp and Pipe Frame time stamp registers */
2875
2902
#define GEN4_TIMESTAMP _MMIO(0x2358)
2876
2903
#define ILK_TIMESTAMP_HI _MMIO(0x70070)
-1
drivers/gpu/drm/i915/display/intel_pch_refclk.c
-1
drivers/gpu/drm/i915/display/intel_pch_refclk.c
-27
drivers/gpu/drm/i915/i915_reg.h
-27
drivers/gpu/drm/i915/i915_reg.h
···
1023
1023
#define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10)
1024
1024
#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4)
1025
1025
1026
-
#define SOUTH_CHICKEN1 _MMIO(0xc2000)
1027
-
#define FDIA_PHASE_SYNC_SHIFT_OVR 19
1028
-
#define FDIA_PHASE_SYNC_SHIFT_EN 18
1029
-
#define INVERT_DDIE_HPD REG_BIT(28)
1030
-
#define INVERT_DDID_HPD_MTP REG_BIT(27)
1031
-
#define INVERT_TC4_HPD REG_BIT(26)
1032
-
#define INVERT_TC3_HPD REG_BIT(25)
1033
-
#define INVERT_TC2_HPD REG_BIT(24)
1034
-
#define INVERT_TC1_HPD REG_BIT(23)
1035
-
#define INVERT_DDID_HPD (1 << 18)
1036
-
#define INVERT_DDIC_HPD (1 << 17)
1037
-
#define INVERT_DDIB_HPD (1 << 16)
1038
-
#define INVERT_DDIA_HPD (1 << 15)
1039
-
#define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
1040
-
#define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
1041
-
#define FDI_BC_BIFURCATION_SELECT (1 << 12)
1042
-
#define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
1043
-
#define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
1044
-
#define SBCLK_RUN_REFCLK_DIS (1 << 7)
1045
-
#define ICP_SECOND_PPS_IO_SELECT REG_BIT(2)
1046
-
#define SPT_PWM_GRANULARITY (1 << 0)
1047
-
#define SOUTH_CHICKEN2 _MMIO(0xc2004)
1048
-
#define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13)
1049
-
#define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12)
1050
-
#define LPT_PWM_GRANULARITY (1 << 5)
1051
-
#define DPLS_EDP_PPS_FIX_DIS (1 << 0)
1052
-
1053
1026
#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
1054
1027
#define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
1055
1028
#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)