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tools headers: Sync arm64 headers with kernel sources

To pick up changes from:

b0a3f0e894f34e01 ("arm64/sysreg: Replace TCR_EL1 field macros")
3bbf004c4808e2c3 ("arm64: cputype: Add Neoverse-V3AE definitions")
e185c8a0d84236d1 ("arm64: cputype: Add NVIDIA Olympus definitions")
52b49bd6de29a89a ("arm64: cputype: Remove duplicate Cortex-X1C definitions")

This should address these tools/perf build warnings:

Warning: Kernel ABI header differences:
diff -u tools/arch/arm64/include/asm/cputype.h arch/arm64/include/asm/cputype.h

Please see tools/include/uapi/README.

Note that this is still out of sync due to is_midr_in_range_list().

Reviewed-by: Leo Yan <leo.yan@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Namhyung Kim <namhyung@kernel.org>

Namhyung Kim 0d5d3bb6 369e91bd

+3 -3
+3 -3
tools/arch/arm64/include/asm/cputype.h
··· 81 81 #define ARM_CPU_PART_CORTEX_A78AE 0xD42 82 82 #define ARM_CPU_PART_CORTEX_X1 0xD44 83 83 #define ARM_CPU_PART_CORTEX_A510 0xD46 84 - #define ARM_CPU_PART_CORTEX_X1C 0xD4C 85 84 #define ARM_CPU_PART_CORTEX_A520 0xD80 86 85 #define ARM_CPU_PART_CORTEX_A710 0xD47 87 86 #define ARM_CPU_PART_CORTEX_A715 0xD4D ··· 92 93 #define ARM_CPU_PART_NEOVERSE_V2 0xD4F 93 94 #define ARM_CPU_PART_CORTEX_A720 0xD81 94 95 #define ARM_CPU_PART_CORTEX_X4 0xD82 96 + #define ARM_CPU_PART_NEOVERSE_V3AE 0xD83 95 97 #define ARM_CPU_PART_NEOVERSE_V3 0xD84 96 98 #define ARM_CPU_PART_CORTEX_X925 0xD85 97 99 #define ARM_CPU_PART_CORTEX_A725 0xD87 ··· 172 172 #define MIDR_CORTEX_A78AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78AE) 173 173 #define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1) 174 174 #define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510) 175 - #define MIDR_CORTEX_X1C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1C) 176 175 #define MIDR_CORTEX_A520 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520) 177 176 #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710) 178 177 #define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A715) ··· 183 184 #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) 184 185 #define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720) 185 186 #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4) 187 + #define MIDR_NEOVERSE_V3AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3AE) 186 188 #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3) 187 189 #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925) 188 190 #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725) ··· 247 247 /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */ 248 248 #define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX 249 249 #define MIDR_FUJITSU_ERRATUM_010001_MASK (~MIDR_CPU_VAR_REV(1, 0)) 250 - #define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_NFD1 | TCR_NFD0) 250 + #define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_EL1_NFD1 | TCR_EL1_NFD0) 251 251 252 252 #ifndef __ASSEMBLER__ 253 253