Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm: merge dpu_format and mdp_format in struct msm_format
Structures dpu_format and mdp_format are largely the same structures.
In order to remove duplication between format databases, merge these two
stucture definitions into the global struct msm_format.
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/590434/
Link: https://lore.kernel.org/r/20240420-dpu-format-v2-5-9e93226cbffd@linaro.org
+296
-305
+6
-6
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+6
-6
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
···
320
320
}
321
321
322
322
static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
323
-
struct dpu_plane_state *pstate, struct dpu_format *format)
323
+
struct dpu_plane_state *pstate, const struct msm_format *format)
324
324
{
325
325
struct dpu_hw_mixer *lm = mixer->hw_lm;
326
326
uint32_t blend_op;
···
363
363
fg_alpha, bg_alpha, blend_op);
364
364
365
365
DRM_DEBUG_ATOMIC("format:%p4cc, alpha_en:%u blend_op:0x%x\n",
366
-
&format->base.pixel_format, format->alpha_enable, blend_op);
366
+
&format->pixel_format, format->alpha_enable, blend_op);
367
367
}
368
368
369
369
static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc)
···
395
395
struct dpu_crtc_mixer *mixer,
396
396
u32 num_mixers,
397
397
enum dpu_stage stage,
398
-
struct dpu_format *format,
398
+
const struct msm_format *format,
399
399
uint64_t modifier,
400
400
struct dpu_sw_pipe *pipe,
401
401
unsigned int stage_idx,
···
412
412
413
413
trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane),
414
414
state, to_dpu_plane_state(state), stage_idx,
415
-
format->base.pixel_format,
415
+
format->pixel_format,
416
416
modifier);
417
417
418
418
DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d multirect_idx %d\n",
···
440
440
struct drm_plane_state *state;
441
441
struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
442
442
struct dpu_plane_state *pstate = NULL;
443
-
struct dpu_format *format;
443
+
const struct msm_format *format;
444
444
struct dpu_hw_ctl *ctl = mixer->lm_ctl;
445
445
446
446
uint32_t lm_idx;
···
459
459
pstate = to_dpu_plane_state(state);
460
460
fb = state->fb;
461
461
462
-
format = to_dpu_format(msm_framebuffer_format(pstate->base.fb));
462
+
format = msm_framebuffer_format(pstate->base.fb);
463
463
464
464
if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
465
465
bg_alpha_enable = true;
+6
-6
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+6
-6
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
···
675
675
if (disp_info->intf_type == INTF_WB && conn_state->writeback_job) {
676
676
fb = conn_state->writeback_job->fb;
677
677
678
-
if (fb && DPU_FORMAT_IS_YUV(to_dpu_format(msm_framebuffer_format(fb))))
678
+
if (fb && MSM_FORMAT_IS_YUV(msm_framebuffer_format(fb)))
679
679
topology.needs_cdm = true;
680
680
} else if (disp_info->intf_type == INTF_DP) {
681
681
if (msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]], adj_mode))
···
2184
2184
}
2185
2185
2186
2186
void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,
2187
-
const struct dpu_format *dpu_fmt,
2187
+
const struct msm_format *dpu_fmt,
2188
2188
u32 output_type)
2189
2189
{
2190
2190
struct dpu_hw_cdm *hw_cdm;
···
2202
2202
if (!hw_cdm)
2203
2203
return;
2204
2204
2205
-
if (!DPU_FORMAT_IS_YUV(dpu_fmt)) {
2205
+
if (!MSM_FORMAT_IS_YUV(dpu_fmt)) {
2206
2206
DPU_DEBUG("[enc:%d] cdm_disable fmt:%p4cc\n", DRMID(phys_enc->parent),
2207
-
&dpu_fmt->base.pixel_format);
2207
+
&dpu_fmt->pixel_format);
2208
2208
if (hw_cdm->ops.bind_pingpong_blk)
2209
2209
hw_cdm->ops.bind_pingpong_blk(hw_cdm, PINGPONG_NONE);
2210
2210
···
2217
2217
cdm_cfg->output_height = phys_enc->cached_mode.vdisplay;
2218
2218
cdm_cfg->output_fmt = dpu_fmt;
2219
2219
cdm_cfg->output_type = output_type;
2220
-
cdm_cfg->output_bit_depth = DPU_FORMAT_IS_DX(dpu_fmt) ?
2220
+
cdm_cfg->output_bit_depth = MSM_FORMAT_IS_DX(dpu_fmt) ?
2221
2221
CDM_CDWN_OUTPUT_10BIT : CDM_CDWN_OUTPUT_8BIT;
2222
2222
cdm_cfg->csc_cfg = &dpu_csc10_rgb2yuv_601l;
2223
2223
···
2246
2246
2247
2247
DPU_DEBUG("[enc:%d] cdm_enable:%d,%d,%p4cc,%d,%d,%d,%d]\n",
2248
2248
DRMID(phys_enc->parent), cdm_cfg->output_width,
2249
-
cdm_cfg->output_height, &cdm_cfg->output_fmt->base.pixel_format,
2249
+
cdm_cfg->output_height, &cdm_cfg->output_fmt->pixel_format,
2250
2250
cdm_cfg->output_type, cdm_cfg->output_bit_depth,
2251
2251
cdm_cfg->h_cdwn_type, cdm_cfg->v_cdwn_type);
2252
2252
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+2
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+2
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
···
235
235
{
236
236
struct drm_display_mode mode;
237
237
struct dpu_hw_intf_timing_params timing_params = { 0 };
238
-
const struct dpu_format *fmt = NULL;
238
+
const struct msm_format *fmt = NULL;
239
239
u32 fmt_fourcc;
240
240
unsigned long lock_flags;
241
241
struct dpu_hw_intf_cfg intf_cfg = { 0 };
···
409
409
static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
410
410
{
411
411
struct dpu_hw_ctl *ctl;
412
-
const struct dpu_format *fmt;
412
+
const struct msm_format *fmt;
413
413
u32 fmt_fourcc;
414
414
415
415
ctl = phys_enc->hw_ctl;
+2
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+2
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
···
322
322
struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
323
323
struct drm_writeback_job *wb_job;
324
324
const struct msm_format *format;
325
-
const struct dpu_format *dpu_fmt;
325
+
const struct msm_format *dpu_fmt;
326
326
327
327
wb_job = wb_enc->wb_job;
328
328
format = msm_framebuffer_format(wb_enc->wb_job->fb);
···
594
594
wb_cfg->dest.height = job->fb->height;
595
595
wb_cfg->dest.num_planes = wb_cfg->dest.format->num_planes;
596
596
597
-
if ((wb_cfg->dest.format->fetch_planes == MDP_PLANE_PLANAR) &&
597
+
if ((wb_cfg->dest.format->fetch_type == MDP_PLANE_PLANAR) &&
598
598
(wb_cfg->dest.format->element[0] == C1_B_Cb))
599
599
swap(wb_cfg->dest.plane_addr[1], wb_cfg->dest.plane_addr[2]);
600
600
+101
-83
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+101
-83
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
···
34
34
#define INTERLEAVED_RGB_FMT(fmt, a, r, g, b, e0, e1, e2, e3, uc, alpha, \
35
35
bp, flg, fm, np) \
36
36
{ \
37
-
.base.pixel_format = DRM_FORMAT_ ## fmt, \
38
-
.fetch_planes = MDP_PLANE_INTERLEAVED, \
37
+
.pixel_format = DRM_FORMAT_ ## fmt, \
38
+
.fetch_type = MDP_PLANE_INTERLEAVED, \
39
39
.alpha_enable = alpha, \
40
40
.element = { (e0), (e1), (e2), (e3) }, \
41
-
.bits = { g, b, r, a }, \
41
+
.bpc_g_y = g, \
42
+
.bpc_b_cb = b, \
43
+
.bpc_r_cr = r, \
44
+
.bpc_a = a, \
42
45
.chroma_sample = CHROMA_FULL, \
43
46
.unpack_align_msb = 0, \
44
47
.unpack_tight = 1, \
45
48
.unpack_count = uc, \
46
49
.bpp = bp, \
47
-
.base.fetch_mode = fm, \
48
-
.base.flags = flg, \
50
+
.fetch_mode = fm, \
51
+
.flags = flg, \
49
52
.num_planes = np, \
50
53
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
51
54
}
···
56
53
#define INTERLEAVED_RGB_FMT_TILED(fmt, a, r, g, b, e0, e1, e2, e3, uc, \
57
54
alpha, bp, flg, fm, np, th) \
58
55
{ \
59
-
.base.pixel_format = DRM_FORMAT_ ## fmt, \
60
-
.fetch_planes = MDP_PLANE_INTERLEAVED, \
56
+
.pixel_format = DRM_FORMAT_ ## fmt, \
57
+
.fetch_type = MDP_PLANE_INTERLEAVED, \
61
58
.alpha_enable = alpha, \
62
59
.element = { (e0), (e1), (e2), (e3) }, \
63
-
.bits = { g, b, r, a }, \
60
+
.bpc_g_y = g, \
61
+
.bpc_b_cb = b, \
62
+
.bpc_r_cr = r, \
63
+
.bpc_a = a, \
64
64
.chroma_sample = CHROMA_FULL, \
65
65
.unpack_align_msb = 0, \
66
66
.unpack_tight = 1, \
67
67
.unpack_count = uc, \
68
68
.bpp = bp, \
69
-
.base.fetch_mode = fm, \
70
-
.base.flags = flg, \
69
+
.fetch_mode = fm, \
70
+
.flags = flg, \
71
71
.num_planes = np, \
72
72
.tile_height = th \
73
73
}
···
79
73
#define INTERLEAVED_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, e3, \
80
74
alpha, chroma, count, bp, flg, fm, np) \
81
75
{ \
82
-
.base.pixel_format = DRM_FORMAT_ ## fmt, \
83
-
.fetch_planes = MDP_PLANE_INTERLEAVED, \
76
+
.pixel_format = DRM_FORMAT_ ## fmt, \
77
+
.fetch_type = MDP_PLANE_INTERLEAVED, \
84
78
.alpha_enable = alpha, \
85
79
.element = { (e0), (e1), (e2), (e3)}, \
86
-
.bits = { g, b, r, a }, \
80
+
.bpc_g_y = g, \
81
+
.bpc_b_cb = b, \
82
+
.bpc_r_cr = r, \
83
+
.bpc_a = a, \
87
84
.chroma_sample = chroma, \
88
85
.unpack_align_msb = 0, \
89
86
.unpack_tight = 1, \
90
87
.unpack_count = count, \
91
88
.bpp = bp, \
92
-
.base.fetch_mode = fm, \
93
-
.base.flags = flg, \
89
+
.fetch_mode = fm, \
90
+
.flags = flg, \
94
91
.num_planes = np, \
95
92
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
96
93
}
97
94
98
95
#define PSEUDO_YUV_FMT(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np) \
99
96
{ \
100
-
.base.pixel_format = DRM_FORMAT_ ## fmt, \
101
-
.fetch_planes = MDP_PLANE_PSEUDO_PLANAR, \
102
-
.alpha_enable = false, \
97
+
.pixel_format = DRM_FORMAT_ ## fmt, \
98
+
.fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
99
+
.alpha_enable = 0, \
103
100
.element = { (e0), (e1), 0, 0 }, \
104
-
.bits = { g, b, r, a }, \
101
+
.bpc_g_y = g, \
102
+
.bpc_b_cb = b, \
103
+
.bpc_r_cr = r, \
104
+
.bpc_a = a, \
105
105
.chroma_sample = chroma, \
106
106
.unpack_align_msb = 0, \
107
107
.unpack_tight = 1, \
108
108
.unpack_count = 2, \
109
109
.bpp = 2, \
110
-
.base.fetch_mode = fm, \
111
-
.base.flags = flg, \
110
+
.fetch_mode = fm, \
111
+
.flags = flg, \
112
112
.num_planes = np, \
113
113
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
114
114
}
···
122
110
#define PSEUDO_YUV_FMT_TILED(fmt, a, r, g, b, e0, e1, chroma, \
123
111
flg, fm, np, th) \
124
112
{ \
125
-
.base.pixel_format = DRM_FORMAT_ ## fmt, \
126
-
.fetch_planes = MDP_PLANE_PSEUDO_PLANAR, \
127
-
.alpha_enable = false, \
113
+
.pixel_format = DRM_FORMAT_ ## fmt, \
114
+
.fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
115
+
.alpha_enable = 0, \
128
116
.element = { (e0), (e1), 0, 0 }, \
129
-
.bits = { g, b, r, a }, \
117
+
.bpc_g_y = g, \
118
+
.bpc_b_cb = b, \
119
+
.bpc_r_cr = r, \
120
+
.bpc_a = a, \
130
121
.chroma_sample = chroma, \
131
122
.unpack_align_msb = 0, \
132
123
.unpack_tight = 1, \
133
124
.unpack_count = 2, \
134
125
.bpp = 2, \
135
-
.base.fetch_mode = fm, \
136
-
.base.flags = flg, \
126
+
.fetch_mode = fm, \
127
+
.flags = flg, \
137
128
.num_planes = np, \
138
129
.tile_height = th \
139
130
}
140
131
141
132
#define PSEUDO_YUV_FMT_LOOSE(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np)\
142
133
{ \
143
-
.base.pixel_format = DRM_FORMAT_ ## fmt, \
144
-
.fetch_planes = MDP_PLANE_PSEUDO_PLANAR, \
145
-
.alpha_enable = false, \
134
+
.pixel_format = DRM_FORMAT_ ## fmt, \
135
+
.fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
136
+
.alpha_enable = 0, \
146
137
.element = { (e0), (e1), 0, 0 }, \
147
-
.bits = { g, b, r, a }, \
138
+
.bpc_g_y = g, \
139
+
.bpc_b_cb = b, \
140
+
.bpc_r_cr = r, \
141
+
.bpc_a = a, \
148
142
.chroma_sample = chroma, \
149
143
.unpack_align_msb = 1, \
150
144
.unpack_tight = 0, \
151
145
.unpack_count = 2, \
152
146
.bpp = 2, \
153
-
.base.fetch_mode = fm, \
154
-
.base.flags = flg, \
147
+
.fetch_mode = fm, \
148
+
.flags = flg, \
155
149
.num_planes = np, \
156
150
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
157
151
}
···
165
147
#define PSEUDO_YUV_FMT_LOOSE_TILED(fmt, a, r, g, b, e0, e1, chroma, \
166
148
flg, fm, np, th) \
167
149
{ \
168
-
.base.pixel_format = DRM_FORMAT_ ## fmt, \
169
-
.fetch_planes = MDP_PLANE_PSEUDO_PLANAR, \
170
-
.alpha_enable = false, \
150
+
.pixel_format = DRM_FORMAT_ ## fmt, \
151
+
.fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
152
+
.alpha_enable = 0, \
171
153
.element = { (e0), (e1), 0, 0 }, \
172
-
.bits = { g, b, r, a }, \
154
+
.bpc_g_y = g, \
155
+
.bpc_b_cb = b, \
156
+
.bpc_r_cr = r, \
157
+
.bpc_a = a, \
173
158
.chroma_sample = chroma, \
174
159
.unpack_align_msb = 1, \
175
160
.unpack_tight = 0, \
176
161
.unpack_count = 2, \
177
162
.bpp = 2, \
178
-
.base.fetch_mode = fm, \
179
-
.base.flags = flg, \
163
+
.fetch_mode = fm, \
164
+
.flags = flg, \
180
165
.num_planes = np, \
181
166
.tile_height = th \
182
167
}
···
188
167
#define PLANAR_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, alpha, chroma, bp, \
189
168
flg, fm, np) \
190
169
{ \
191
-
.base.pixel_format = DRM_FORMAT_ ## fmt, \
192
-
.fetch_planes = MDP_PLANE_PLANAR, \
170
+
.pixel_format = DRM_FORMAT_ ## fmt, \
171
+
.fetch_type = MDP_PLANE_PLANAR, \
193
172
.alpha_enable = alpha, \
194
173
.element = { (e0), (e1), (e2), 0 }, \
195
-
.bits = { g, b, r, a }, \
174
+
.bpc_g_y = g, \
175
+
.bpc_b_cb = b, \
176
+
.bpc_r_cr = r, \
177
+
.bpc_a = a, \
196
178
.chroma_sample = chroma, \
197
179
.unpack_align_msb = 0, \
198
180
.unpack_tight = 1, \
199
181
.unpack_count = 1, \
200
182
.bpp = bp, \
201
-
.base.fetch_mode = fm, \
202
-
.base.flags = flg, \
183
+
.fetch_mode = fm, \
184
+
.flags = flg, \
203
185
.num_planes = np, \
204
186
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
205
187
}
···
217
193
uint32_t color;
218
194
};
219
195
220
-
static const struct dpu_format dpu_format_map[] = {
196
+
static const struct msm_format dpu_format_map[] = {
221
197
INTERLEAVED_RGB_FMT(ARGB8888,
222
198
BPC8A, BPC8, BPC8, BPC8,
223
199
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
···
507
483
* If a compression ratio needs to be used for this or any other format,
508
484
* the data will be passed by user-space.
509
485
*/
510
-
static const struct dpu_format dpu_format_map_ubwc[] = {
486
+
static const struct msm_format dpu_format_map_ubwc[] = {
511
487
INTERLEAVED_RGB_FMT_TILED(BGR565,
512
488
0, BPC5, BPC6, BPC5,
513
489
C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
···
617
593
}
618
594
}
619
595
620
-
static int _dpu_format_get_media_color_ubwc(const struct dpu_format *fmt)
596
+
static int _dpu_format_get_media_color_ubwc(const struct msm_format *fmt)
621
597
{
622
598
static const struct dpu_media_color_map dpu_media_ubwc_map[] = {
623
599
{DRM_FORMAT_ABGR8888, COLOR_FMT_RGBA8888_UBWC},
···
633
609
int color_fmt = -1;
634
610
int i;
635
611
636
-
if (fmt->base.pixel_format == DRM_FORMAT_NV12 ||
637
-
fmt->base.pixel_format == DRM_FORMAT_P010) {
638
-
if (DPU_FORMAT_IS_DX(fmt)) {
612
+
if (fmt->pixel_format == DRM_FORMAT_NV12 ||
613
+
fmt->pixel_format == DRM_FORMAT_P010) {
614
+
if (MSM_FORMAT_IS_DX(fmt)) {
639
615
if (fmt->unpack_tight)
640
616
color_fmt = COLOR_FMT_NV12_BPP10_UBWC;
641
617
else
···
646
622
}
647
623
648
624
for (i = 0; i < ARRAY_SIZE(dpu_media_ubwc_map); ++i)
649
-
if (fmt->base.pixel_format == dpu_media_ubwc_map[i].format) {
625
+
if (fmt->pixel_format == dpu_media_ubwc_map[i].format) {
650
626
color_fmt = dpu_media_ubwc_map[i].color;
651
627
break;
652
628
}
···
654
630
}
655
631
656
632
static int _dpu_format_get_plane_sizes_ubwc(
657
-
const struct dpu_format *fmt,
633
+
const struct msm_format *fmt,
658
634
const uint32_t width,
659
635
const uint32_t height,
660
636
struct dpu_hw_fmt_layout *layout)
661
637
{
662
638
int i;
663
639
int color;
664
-
bool meta = DPU_FORMAT_IS_UBWC(fmt);
640
+
bool meta = MSM_FORMAT_IS_UBWC(fmt);
665
641
666
642
memset(layout, 0, sizeof(struct dpu_hw_fmt_layout));
667
643
layout->format = fmt;
···
672
648
color = _dpu_format_get_media_color_ubwc(fmt);
673
649
if (color < 0) {
674
650
DRM_ERROR("UBWC format not supported for fmt: %p4cc\n",
675
-
&fmt->base.pixel_format);
651
+
&fmt->pixel_format);
676
652
return -EINVAL;
677
653
}
678
654
679
-
if (DPU_FORMAT_IS_YUV(layout->format)) {
655
+
if (MSM_FORMAT_IS_YUV(layout->format)) {
680
656
uint32_t y_sclines, uv_sclines;
681
657
uint32_t y_meta_scanlines = 0;
682
658
uint32_t uv_meta_scanlines = 0;
···
733
709
}
734
710
735
711
static int _dpu_format_get_plane_sizes_linear(
736
-
const struct dpu_format *fmt,
712
+
const struct msm_format *fmt,
737
713
const uint32_t width,
738
714
const uint32_t height,
739
715
struct dpu_hw_fmt_layout *layout,
···
748
724
layout->num_planes = fmt->num_planes;
749
725
750
726
/* Due to memset above, only need to set planes of interest */
751
-
if (fmt->fetch_planes == MDP_PLANE_INTERLEAVED) {
727
+
if (fmt->fetch_type == MDP_PLANE_INTERLEAVED) {
752
728
layout->num_planes = 1;
753
729
layout->plane_size[0] = width * height * layout->format->bpp;
754
730
layout->plane_pitch[0] = width * layout->format->bpp;
···
766
742
return -EINVAL;
767
743
}
768
744
769
-
if ((fmt->base.pixel_format == DRM_FORMAT_NV12) &&
770
-
(DPU_FORMAT_IS_DX(fmt)))
745
+
if ((fmt->pixel_format == DRM_FORMAT_NV12) &&
746
+
(MSM_FORMAT_IS_DX(fmt)))
771
747
bpp = 2;
772
748
layout->plane_pitch[0] = width * bpp;
773
749
layout->plane_pitch[1] = layout->plane_pitch[0] / h_subsample;
···
775
751
layout->plane_size[1] = layout->plane_pitch[1] *
776
752
(height / v_subsample);
777
753
778
-
if (fmt->fetch_planes == MDP_PLANE_PSEUDO_PLANAR) {
754
+
if (fmt->fetch_type == MDP_PLANE_PSEUDO_PLANAR) {
779
755
layout->num_planes = 2;
780
756
layout->plane_size[1] *= 2;
781
757
layout->plane_pitch[1] *= 2;
···
805
781
}
806
782
807
783
static int dpu_format_get_plane_sizes(
808
-
const struct dpu_format *fmt,
784
+
const struct msm_format *fmt,
809
785
const uint32_t w,
810
786
const uint32_t h,
811
787
struct dpu_hw_fmt_layout *layout,
···
821
797
return -ERANGE;
822
798
}
823
799
824
-
if (DPU_FORMAT_IS_UBWC(fmt) || DPU_FORMAT_IS_TILE(fmt))
800
+
if (MSM_FORMAT_IS_UBWC(fmt) || MSM_FORMAT_IS_TILE(fmt))
825
801
return _dpu_format_get_plane_sizes_ubwc(fmt, w, h, layout);
826
802
827
803
return _dpu_format_get_plane_sizes_linear(fmt, w, h, layout, pitches);
···
847
823
return -EFAULT;
848
824
}
849
825
850
-
meta = DPU_FORMAT_IS_UBWC(layout->format);
826
+
meta = MSM_FORMAT_IS_UBWC(layout->format);
851
827
852
828
/* Per-format logic for verifying active planes */
853
-
if (DPU_FORMAT_IS_YUV(layout->format)) {
829
+
if (MSM_FORMAT_IS_YUV(layout->format)) {
854
830
/************************************************/
855
831
/* UBWC ** */
856
832
/* buffer ** DPU PLANE */
···
966
942
return -ERANGE;
967
943
}
968
944
969
-
layout->format = to_dpu_format(msm_framebuffer_format(fb));
945
+
layout->format = msm_framebuffer_format(fb);
970
946
971
947
/* Populate the plane sizes etc via get_format */
972
948
ret = dpu_format_get_plane_sizes(layout->format, fb->width, fb->height,
···
975
951
return ret;
976
952
977
953
/* Populate the addresses given the fb */
978
-
if (DPU_FORMAT_IS_UBWC(layout->format) ||
979
-
DPU_FORMAT_IS_TILE(layout->format))
954
+
if (MSM_FORMAT_IS_UBWC(layout->format) ||
955
+
MSM_FORMAT_IS_TILE(layout->format))
980
956
ret = _dpu_format_populate_addrs_ubwc(aspace, fb, layout);
981
957
else
982
958
ret = _dpu_format_populate_addrs_linear(aspace, fb, layout);
···
986
962
987
963
int dpu_format_check_modified_format(
988
964
const struct msm_kms *kms,
989
-
const struct msm_format *msm_fmt,
965
+
const struct msm_format *fmt,
990
966
const struct drm_mode_fb_cmd2 *cmd,
991
967
struct drm_gem_object **bos)
992
968
{
993
969
const struct drm_format_info *info;
994
-
const struct dpu_format *fmt;
995
970
struct dpu_hw_fmt_layout layout;
996
971
uint32_t bos_total_size = 0;
997
972
int ret, i;
998
973
999
-
if (!msm_fmt || !cmd || !bos) {
974
+
if (!fmt || !cmd || !bos) {
1000
975
DRM_ERROR("invalid arguments\n");
1001
976
return -EINVAL;
1002
977
}
1003
978
1004
-
fmt = to_dpu_format(msm_fmt);
1005
-
info = drm_format_info(fmt->base.pixel_format);
979
+
info = drm_format_info(fmt->pixel_format);
1006
980
if (!info)
1007
981
return -EINVAL;
1008
982
···
1027
1005
return 0;
1028
1006
}
1029
1007
1030
-
const struct dpu_format *dpu_get_dpu_format_ext(
1008
+
const struct msm_format *dpu_get_dpu_format_ext(
1031
1009
const uint32_t format,
1032
1010
const uint64_t modifier)
1033
1011
{
1034
1012
uint32_t i = 0;
1035
-
const struct dpu_format *fmt = NULL;
1036
-
const struct dpu_format *map = NULL;
1013
+
const struct msm_format *fmt = NULL;
1014
+
const struct msm_format *map = NULL;
1037
1015
ssize_t map_size = 0;
1038
1016
1039
1017
/*
···
1059
1037
}
1060
1038
1061
1039
for (i = 0; i < map_size; i++) {
1062
-
if (format == map[i].base.pixel_format) {
1040
+
if (format == map[i].pixel_format) {
1063
1041
fmt = &map[i];
1064
1042
break;
1065
1043
}
···
1071
1049
else
1072
1050
DRM_DEBUG_ATOMIC("fmt %4.4s mod 0x%llX ubwc %d yuv %ld\n",
1073
1051
(char *)&format, modifier,
1074
-
DPU_FORMAT_IS_UBWC(fmt),
1075
-
DPU_FORMAT_IS_YUV(fmt));
1052
+
MSM_FORMAT_IS_UBWC(fmt),
1053
+
MSM_FORMAT_IS_YUV(fmt));
1076
1054
1077
1055
return fmt;
1078
1056
}
···
1082
1060
const uint32_t format,
1083
1061
const uint64_t modifiers)
1084
1062
{
1085
-
const struct dpu_format *fmt = dpu_get_dpu_format_ext(format,
1086
-
modifiers);
1087
-
if (fmt)
1088
-
return &fmt->base;
1089
-
return NULL;
1063
+
return dpu_get_dpu_format_ext(format, modifiers);
1090
1064
}
+3
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h
+3
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h
···
14
14
* @format: DRM FourCC Code
15
15
* @modifiers: format modifier array from client, one per plane
16
16
*/
17
-
const struct dpu_format *dpu_get_dpu_format_ext(
17
+
const struct msm_format *dpu_get_dpu_format_ext(
18
18
const uint32_t format,
19
19
const uint64_t modifier);
20
20
···
43
43
}
44
44
45
45
/**
46
-
* dpu_get_msm_format - get an dpu_format by its msm_format base
46
+
* dpu_get_msm_format - get an msm_format by its msm_format base
47
47
* callback function registers with the msm_kms layer
48
48
* @kms: kms driver
49
49
* @format: DRM FourCC Code
···
58
58
* dpu_format_check_modified_format - validate format and buffers for
59
59
* dpu non-standard, i.e. modified format
60
60
* @kms: kms driver
61
-
* @msm_fmt: pointer to the msm_fmt base pointer of an dpu_format
61
+
* @msm_fmt: pointer to the msm_fmt base pointer of an msm_format
62
62
* @cmd: fb_cmd2 structure user request
63
63
* @bos: gem buffer object list
64
64
*
+2
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
+2
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
···
170
170
static int dpu_hw_cdm_enable(struct dpu_hw_cdm *ctx, struct dpu_hw_cdm_cfg *cdm)
171
171
{
172
172
struct dpu_hw_blk_reg_map *c = &ctx->hw;
173
-
const struct dpu_format *fmt;
173
+
const struct msm_format *fmt;
174
174
u32 opmode = 0;
175
175
u32 csc = 0;
176
176
···
179
179
180
180
fmt = cdm->output_fmt;
181
181
182
-
if (!DPU_FORMAT_IS_YUV(fmt))
182
+
if (!MSM_FORMAT_IS_YUV(fmt))
183
183
return -EINVAL;
184
184
185
185
dpu_hw_csc_setup(&ctx->hw, CDM_CSC_10_MATRIX_COEFF_0, cdm->csc_cfg, true);
+2
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h
+2
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h
···
19
19
* @output_bit_depth: output bit-depth of CDM block
20
20
* @h_cdwn_type: downsample type used for horizontal pixels
21
21
* @v_cdwn_type: downsample type used for vertical pixels
22
-
* @output_fmt: handle to dpu_format of CDM block
22
+
* @output_fmt: handle to msm_format of CDM block
23
23
* @csc_cfg: handle to CSC matrix programmed for CDM block
24
24
* @output_type: interface to which CDM is paired (HDMI/WB)
25
25
* @pp_id: ping-pong block to which CDM is bound to
···
30
30
u32 output_bit_depth;
31
31
u32 h_cdwn_type;
32
32
u32 v_cdwn_type;
33
-
const struct dpu_format *output_fmt;
33
+
const struct msm_format *output_fmt;
34
34
const struct dpu_csc_cfg *csc_cfg;
35
35
u32 output_type;
36
36
int pp_id;
+5
-5
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+5
-5
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
···
98
98
99
99
static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf,
100
100
const struct dpu_hw_intf_timing_params *p,
101
-
const struct dpu_format *fmt)
101
+
const struct msm_format *fmt)
102
102
{
103
103
struct dpu_hw_blk_reg_map *c = &intf->hw;
104
104
u32 hsync_period, vsync_period;
···
194
194
(p->vsync_polarity << 1) | /* VSYNC Polarity */
195
195
(p->hsync_polarity << 0); /* HSYNC Polarity */
196
196
197
-
if (!DPU_FORMAT_IS_YUV(fmt))
198
-
panel_format = (fmt->bits[C0_G_Y] |
199
-
(fmt->bits[C1_B_Cb] << 2) |
200
-
(fmt->bits[C2_R_Cr] << 4) |
197
+
if (!MSM_FORMAT_IS_YUV(fmt))
198
+
panel_format = (fmt->bpc_g_y |
199
+
(fmt->bpc_b_cb << 2) |
200
+
(fmt->bpc_r_cr << 4) |
201
201
(0x21 << 8));
202
202
else
203
203
/* Interface treats all the pixel data in RGB888 format */
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
···
81
81
struct dpu_hw_intf_ops {
82
82
void (*setup_timing_gen)(struct dpu_hw_intf *intf,
83
83
const struct dpu_hw_intf_timing_params *p,
84
-
const struct dpu_format *fmt);
84
+
const struct msm_format *fmt);
85
85
86
86
void (*setup_prg_fetch)(struct dpu_hw_intf *intf,
87
87
const struct dpu_hw_intf_prog_fetch *fetch);
+1
-40
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+1
-40
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
···
37
37
#define DPU_MAX_DE_CURVES 3
38
38
#endif
39
39
40
-
#define DPU_FORMAT_IS_YUV(X) MSM_FORMAT_IS_YUV(&(X)->base)
41
-
#define DPU_FORMAT_IS_DX(X) MSM_FORMAT_IS_DX(&(X)->base)
42
-
#define DPU_FORMAT_IS_LINEAR(X) MSM_FORMAT_IS_LINEAR(&(X)->base)
43
-
#define DPU_FORMAT_IS_TILE(X) MSM_FORMAT_IS_TILE(&(X)->base)
44
-
#define DPU_FORMAT_IS_UBWC(X) MSM_FORMAT_IS_UBWC(&(X)->base)
45
-
46
40
#define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0)
47
41
#define DPU_BLEND_FG_ALPHA_BG_CONST (1 << 0)
48
42
#define DPU_BLEND_FG_ALPHA_FG_PIXEL (2 << 0)
···
299
305
BLEND_3D_MAX
300
306
};
301
307
302
-
/** struct dpu_format - defines the format configuration which
303
-
* allows DPU HW to correctly fetch and decode the format
304
-
* @base: base msm_format structure containing fourcc code
305
-
* @fetch_planes: how the color components are packed in pixel format
306
-
* @element: element color ordering
307
-
* @bits: element bit widths
308
-
* @chroma_sample: chroma sub-samplng type
309
-
* @unpack_align_msb: unpack aligned, 0 to LSB, 1 to MSB
310
-
* @unpack_tight: 0 for loose, 1 for tight
311
-
* @unpack_count: 0 = 1 component, 1 = 2 component
312
-
* @bpp: bytes per pixel
313
-
* @alpha_enable: whether the format has an alpha channel
314
-
* @num_planes: number of planes (including meta data planes)
315
-
* @tile_width: format tile width
316
-
* @tile_height: format tile height
317
-
*/
318
-
struct dpu_format {
319
-
struct msm_format base;
320
-
enum mdp_fetch_type fetch_planes;
321
-
u8 element[DPU_MAX_PLANES];
322
-
u8 bits[DPU_MAX_PLANES];
323
-
enum mdp_chroma_samp_type chroma_sample;
324
-
u8 unpack_align_msb;
325
-
u8 unpack_tight;
326
-
u8 unpack_count;
327
-
u8 bpp;
328
-
u8 alpha_enable;
329
-
u8 num_planes;
330
-
u16 tile_width;
331
-
u16 tile_height;
332
-
};
333
-
#define to_dpu_format(x) container_of(x, struct dpu_format, base)
334
-
335
308
/**
336
309
* struct dpu_hw_fmt_layout - format information of the source pixel data
337
310
* @format: pixel format parameters
···
311
350
* @plane_pitch: pitch of each plane
312
351
*/
313
352
struct dpu_hw_fmt_layout {
314
-
const struct dpu_format *format;
353
+
const struct msm_format *format;
315
354
uint32_t num_planes;
316
355
uint32_t width;
317
356
uint32_t height;
+15
-15
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+15
-15
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
···
206
206
* Setup source pixel format, flip,
207
207
*/
208
208
static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
209
-
const struct dpu_format *fmt, u32 flags)
209
+
const struct msm_format *fmt, u32 flags)
210
210
{
211
211
struct dpu_hw_sspp *ctx = pipe->sspp;
212
212
struct dpu_hw_blk_reg_map *c;
···
247
247
chroma_samp = CHROMA_H2V1;
248
248
}
249
249
250
-
src_format = (chroma_samp << 23) | (fmt->fetch_planes << 19) |
251
-
(fmt->bits[C3_ALPHA] << 6) | (fmt->bits[C2_R_Cr] << 4) |
252
-
(fmt->bits[C1_B_Cb] << 2) | (fmt->bits[C0_G_Y] << 0);
250
+
src_format = (chroma_samp << 23) | (fmt->fetch_type << 19) |
251
+
(fmt->bpc_a << 6) | (fmt->bpc_r_cr << 4) |
252
+
(fmt->bpc_b_cb << 2) | (fmt->bpc_g_y << 0);
253
253
254
254
if (flags & DPU_SSPP_ROT_90)
255
255
src_format |= BIT(11); /* ROT90 */
256
256
257
-
if (fmt->alpha_enable && fmt->fetch_planes == MDP_PLANE_INTERLEAVED)
257
+
if (fmt->alpha_enable && fmt->fetch_type == MDP_PLANE_INTERLEAVED)
258
258
src_format |= BIT(8); /* SRCC3_EN */
259
259
260
260
if (flags & DPU_SSPP_SOLID_FILL)
···
267
267
(fmt->unpack_align_msb << 18) |
268
268
((fmt->bpp - 1) << 9);
269
269
270
-
if (!DPU_FORMAT_IS_LINEAR(fmt)) {
271
-
if (DPU_FORMAT_IS_UBWC(fmt))
270
+
if (fmt->fetch_mode != MDP_FETCH_LINEAR) {
271
+
if (MSM_FORMAT_IS_UBWC(fmt))
272
272
opmode |= MDSS_MDP_OP_BWC_EN;
273
-
src_format |= (fmt->base.fetch_mode & 3) << 30; /*FRAME_FORMAT */
273
+
src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */
274
274
DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
275
275
DPU_FETCH_CONFIG_RESET_VALUE |
276
276
ctx->ubwc->highest_bank_bit << 18);
···
295
295
break;
296
296
case UBWC_4_0:
297
297
DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
298
-
DPU_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
298
+
MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
299
299
break;
300
300
}
301
301
}
···
303
303
opmode |= MDSS_MDP_OP_PE_OVERRIDE;
304
304
305
305
/* if this is YUV pixel format, enable CSC */
306
-
if (DPU_FORMAT_IS_YUV(fmt))
306
+
if (MSM_FORMAT_IS_YUV(fmt))
307
307
src_format |= BIT(15);
308
308
309
-
if (DPU_FORMAT_IS_DX(fmt))
309
+
if (MSM_FORMAT_IS_DX(fmt))
310
310
src_format |= BIT(14);
311
311
312
312
/* update scaler opmode, if appropriate */
313
313
if (test_bit(DPU_SSPP_CSC, &ctx->cap->features))
314
314
_sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
315
-
DPU_FORMAT_IS_YUV(fmt));
315
+
MSM_FORMAT_IS_YUV(fmt));
316
316
else if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features))
317
317
_sspp_setup_csc10_opmode(ctx,
318
318
VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT,
319
-
DPU_FORMAT_IS_YUV(fmt));
319
+
MSM_FORMAT_IS_YUV(fmt));
320
320
321
321
DPU_REG_WRITE(c, format_off, src_format);
322
322
DPU_REG_WRITE(c, unpack_pat_off, unpack);
···
385
385
386
386
static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
387
387
struct dpu_hw_scaler3_cfg *scaler3_cfg,
388
-
const struct dpu_format *format)
388
+
const struct msm_format *format)
389
389
{
390
390
if (!ctx || !scaler3_cfg)
391
391
return;
···
556
556
}
557
557
558
558
static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe,
559
-
const struct dpu_format *fmt,
559
+
const struct msm_format *fmt,
560
560
bool enable)
561
561
{
562
562
struct dpu_hw_sspp *ctx = pipe->sspp;
+3
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+3
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
···
183
183
* @flags: Extra flags for format config
184
184
*/
185
185
void (*setup_format)(struct dpu_sw_pipe *pipe,
186
-
const struct dpu_format *fmt, u32 flags);
186
+
const struct msm_format *fmt, u32 flags);
187
187
188
188
/**
189
189
* setup_rects - setup pipe ROI rectangles
···
279
279
*/
280
280
void (*setup_scaler)(struct dpu_hw_sspp *ctx,
281
281
struct dpu_hw_scaler3_cfg *scaler3_cfg,
282
-
const struct dpu_format *format);
282
+
const struct msm_format *format);
283
283
284
284
/**
285
285
* setup_cdp - setup client driven prefetch
···
288
288
* @enable: whether the CDP should be enabled for this pipe
289
289
*/
290
290
void (*setup_cdp)(struct dpu_sw_pipe *pipe,
291
-
const struct dpu_format *fmt,
291
+
const struct msm_format *fmt,
292
292
bool enable);
293
293
};
294
294
+7
-7
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
+7
-7
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
···
282
282
void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
283
283
struct dpu_hw_scaler3_cfg *scaler3_cfg,
284
284
u32 scaler_offset, u32 scaler_version,
285
-
const struct dpu_format *format)
285
+
const struct msm_format *format)
286
286
{
287
287
u32 op_mode = 0;
288
288
u32 phase_init, preload, src_y_rgb, src_uv, dst;
···
293
293
op_mode |= BIT(0);
294
294
op_mode |= (scaler3_cfg->y_rgb_filter_cfg & 0x3) << 16;
295
295
296
-
if (format && DPU_FORMAT_IS_YUV(format)) {
296
+
if (format && MSM_FORMAT_IS_YUV(format)) {
297
297
op_mode |= BIT(12);
298
298
op_mode |= (scaler3_cfg->uv_filter_cfg & 0x3) << 24;
299
299
}
···
367
367
DPU_REG_WRITE(c, QSEED3_DST_SIZE + scaler_offset, dst);
368
368
369
369
end:
370
-
if (format && !DPU_FORMAT_IS_DX(format))
370
+
if (format && !MSM_FORMAT_IS_DX(format))
371
371
op_mode |= BIT(14);
372
372
373
373
if (format && format->alpha_enable) {
···
522
522
#define CDP_PRELOAD_AHEAD_64 BIT(3)
523
523
524
524
void dpu_setup_cdp(struct dpu_hw_blk_reg_map *c, u32 offset,
525
-
const struct dpu_format *fmt, bool enable)
525
+
const struct msm_format *fmt, bool enable)
526
526
{
527
527
u32 cdp_cntl = CDP_PRELOAD_AHEAD_64;
528
528
529
529
if (enable)
530
530
cdp_cntl |= CDP_ENABLE;
531
-
if (DPU_FORMAT_IS_UBWC(fmt))
531
+
if (MSM_FORMAT_IS_UBWC(fmt))
532
532
cdp_cntl |= CDP_UBWC_META_ENABLE;
533
-
if (DPU_FORMAT_IS_UBWC(fmt) ||
534
-
DPU_FORMAT_IS_TILE(fmt))
533
+
if (MSM_FORMAT_IS_UBWC(fmt) ||
534
+
MSM_FORMAT_IS_TILE(fmt))
535
535
cdp_cntl |= CDP_TILE_AMORTIZE_ENABLE;
536
536
537
537
DPU_REG_WRITE(c, offset, cdp_cntl);
+2
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+2
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
···
344
344
void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
345
345
struct dpu_hw_scaler3_cfg *scaler3_cfg,
346
346
u32 scaler_offset, u32 scaler_version,
347
-
const struct dpu_format *format);
347
+
const struct msm_format *format);
348
348
349
349
void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c,
350
350
u32 csc_reg_off,
351
351
const struct dpu_csc_cfg *data, bool csc10);
352
352
353
353
void dpu_setup_cdp(struct dpu_hw_blk_reg_map *c, u32 offset,
354
-
const struct dpu_format *fmt, bool enable);
354
+
const struct msm_format *fmt, bool enable);
355
355
356
356
u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,
357
357
u32 total_fl);
+9
-9
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
+9
-9
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
···
67
67
struct dpu_hw_wb_cfg *data)
68
68
{
69
69
struct dpu_hw_blk_reg_map *c = &ctx->hw;
70
-
const struct dpu_format *fmt = data->dest.format;
70
+
const struct msm_format *fmt = data->dest.format;
71
71
u32 dst_format, pattern, ystride0, ystride1, outsize, chroma_samp;
72
72
u32 write_config = 0;
73
73
u32 opmode = 0;
···
76
76
chroma_samp = fmt->chroma_sample;
77
77
78
78
dst_format = (chroma_samp << 23) |
79
-
(fmt->fetch_planes << 19) |
80
-
(fmt->bits[C3_ALPHA] << 6) |
81
-
(fmt->bits[C2_R_Cr] << 4) |
82
-
(fmt->bits[C1_B_Cb] << 2) |
83
-
(fmt->bits[C0_G_Y] << 0);
79
+
(fmt->fetch_type << 19) |
80
+
(fmt->bpc_a << 6) |
81
+
(fmt->bpc_r_cr << 4) |
82
+
(fmt->bpc_b_cb << 2) |
83
+
(fmt->bpc_g_y << 0);
84
84
85
-
if (fmt->bits[C3_ALPHA] || fmt->alpha_enable) {
85
+
if (fmt->bpc_a || fmt->alpha_enable) {
86
86
dst_format |= BIT(8); /* DSTC3_EN */
87
87
if (!fmt->alpha_enable ||
88
88
!(ctx->caps->features & BIT(DPU_WB_PIPE_ALPHA)))
89
89
dst_format |= BIT(14); /* DST_ALPHA_X */
90
90
}
91
91
92
-
if (DPU_FORMAT_IS_YUV(fmt))
92
+
if (MSM_FORMAT_IS_YUV(fmt))
93
93
dst_format |= BIT(15);
94
94
95
95
pattern = (fmt->element[3] << 24) |
···
149
149
}
150
150
151
151
static void dpu_hw_wb_setup_cdp(struct dpu_hw_wb *ctx,
152
-
const struct dpu_format *fmt,
152
+
const struct msm_format *fmt,
153
153
bool enable)
154
154
{
155
155
if (!ctx)
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h
+37
-37
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+37
-37
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
···
113
113
* Prefill BW Equation: line src bytes * line_time
114
114
*/
115
115
static u64 _dpu_plane_calc_bw(const struct dpu_mdss_cfg *catalog,
116
-
const struct dpu_format *fmt,
116
+
const struct msm_format *fmt,
117
117
const struct drm_display_mode *mode,
118
118
struct dpu_sw_pipe_cfg *pipe_cfg)
119
119
{
···
195
195
static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
196
196
struct dpu_sw_pipe *pipe,
197
197
enum dpu_qos_lut_usage lut_usage,
198
-
const struct dpu_format *fmt, u32 src_width)
198
+
const struct msm_format *fmt, u32 src_width)
199
199
{
200
200
struct dpu_plane *pdpu;
201
201
u32 fixed_buff_size;
···
214
214
215
215
/* FIXME: in multirect case account for the src_width of all the planes */
216
216
217
-
if (fmt->fetch_planes == MDP_PLANE_PSEUDO_PLANAR) {
217
+
if (fmt->fetch_type == MDP_PLANE_PSEUDO_PLANAR) {
218
218
if (fmt->chroma_sample == CHROMA_420) {
219
219
/* NV12 */
220
220
total_fl = (fixed_buff_size / 2) /
···
236
236
237
237
DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc w:%u fl:%u\n",
238
238
pipe->sspp->idx - SSPP_VIG0,
239
-
&fmt->base.pixel_format,
239
+
&fmt->pixel_format,
240
240
src_width, total_fl);
241
241
242
242
return total_fl;
···
251
251
*/
252
252
static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
253
253
struct dpu_sw_pipe *pipe,
254
-
const struct dpu_format *fmt, struct dpu_sw_pipe_cfg *pipe_cfg)
254
+
const struct msm_format *fmt, struct dpu_sw_pipe_cfg *pipe_cfg)
255
255
{
256
256
struct dpu_plane *pdpu = to_dpu_plane(plane);
257
257
struct dpu_hw_qos_cfg cfg;
···
260
260
if (!pdpu->is_rt_pipe) {
261
261
lut_usage = DPU_QOS_LUT_USAGE_NRT;
262
262
} else {
263
-
if (fmt && DPU_FORMAT_IS_LINEAR(fmt))
263
+
if (fmt && MSM_FORMAT_IS_LINEAR(fmt))
264
264
lut_usage = DPU_QOS_LUT_USAGE_LINEAR;
265
265
else
266
266
lut_usage = DPU_QOS_LUT_USAGE_MACROTILE;
···
284
284
pdpu->is_rt_pipe);
285
285
286
286
trace_dpu_perf_set_qos_luts(pipe->sspp->idx - SSPP_VIG0,
287
-
(fmt) ? fmt->base.pixel_format : 0,
287
+
(fmt) ? fmt->pixel_format : 0,
288
288
pdpu->is_rt_pipe, total_fl, cfg.creq_lut, lut_usage);
289
289
290
290
DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc rt:%d fl:%u lut:0x%llx\n",
291
291
pdpu->pipe - SSPP_VIG0,
292
-
fmt ? &fmt->base.pixel_format : NULL,
292
+
fmt ? &fmt->pixel_format : NULL,
293
293
pdpu->is_rt_pipe, total_fl, cfg.creq_lut);
294
294
295
295
trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0,
296
-
(fmt) ? fmt->base.pixel_format : 0,
297
-
(fmt) ? fmt->base.fetch_mode : 0,
296
+
(fmt) ? fmt->pixel_format : 0,
297
+
(fmt) ? fmt->fetch_mode : 0,
298
298
cfg.danger_lut,
299
299
cfg.safe_lut);
300
300
301
301
DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc mode:%d luts[0x%x, 0x%x]\n",
302
302
pdpu->pipe - SSPP_VIG0,
303
-
fmt ? &fmt->base.pixel_format : NULL,
304
-
fmt ? fmt->base.fetch_mode : -1,
303
+
fmt ? &fmt->pixel_format : NULL,
304
+
fmt ? fmt->fetch_mode : -1,
305
305
cfg.danger_lut,
306
306
cfg.safe_lut);
307
307
···
425
425
static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw,
426
426
uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
427
427
struct dpu_hw_scaler3_cfg *scale_cfg,
428
-
const struct dpu_format *fmt,
428
+
const struct msm_format *fmt,
429
429
uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v,
430
430
unsigned int rotation)
431
431
{
···
477
477
scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V;
478
478
}
479
479
}
480
-
if (!(DPU_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
480
+
if (!(MSM_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
481
481
&& (src_w == dst_w))
482
482
return;
483
483
···
510
510
}
511
511
512
512
static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_sw_pipe *pipe,
513
-
const struct dpu_format *fmt)
513
+
const struct msm_format *fmt)
514
514
{
515
515
const struct dpu_csc_cfg *csc_ptr;
516
516
517
-
if (!DPU_FORMAT_IS_YUV(fmt))
517
+
if (!MSM_FORMAT_IS_YUV(fmt))
518
518
return NULL;
519
519
520
520
if (BIT(DPU_SSPP_CSC_10BIT) & pipe->sspp->cap->features)
···
526
526
}
527
527
528
528
static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe,
529
-
const struct dpu_format *fmt, bool color_fill,
529
+
const struct msm_format *fmt, bool color_fill,
530
530
struct dpu_sw_pipe_cfg *pipe_cfg,
531
531
unsigned int rotation)
532
532
{
533
533
struct dpu_hw_sspp *pipe_hw = pipe->sspp;
534
-
const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format);
534
+
const struct drm_format_info *info = drm_format_info(fmt->pixel_format);
535
535
struct dpu_hw_scaler3_cfg scaler3_cfg;
536
536
struct dpu_hw_pixel_ext pixel_ext;
537
537
u32 src_width = drm_rect_width(&pipe_cfg->src_rect);
···
577
577
struct dpu_sw_pipe *pipe,
578
578
struct drm_rect *dst_rect,
579
579
u32 fill_color,
580
-
const struct dpu_format *fmt)
580
+
const struct msm_format *fmt)
581
581
{
582
582
struct dpu_sw_pipe_cfg pipe_cfg;
583
583
···
615
615
static void _dpu_plane_color_fill(struct dpu_plane *pdpu,
616
616
uint32_t color, uint32_t alpha)
617
617
{
618
-
const struct dpu_format *fmt;
618
+
const struct msm_format *fmt;
619
619
const struct drm_plane *plane = &pdpu->base;
620
620
struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
621
621
u32 fill_color = (color & 0xFFFFFF) | ((alpha & 0xFF) << 24);
···
704
704
705
705
static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu,
706
706
const struct dpu_sspp_sub_blks *sblk,
707
-
struct drm_rect src, const struct dpu_format *fmt)
707
+
struct drm_rect src, const struct msm_format *fmt)
708
708
{
709
709
size_t num_formats;
710
710
const u32 *supported_formats;
···
723
723
supported_formats = sblk->rotation_cfg->rot_format_list;
724
724
num_formats = sblk->rotation_cfg->rot_num_formats;
725
725
726
-
if (!DPU_FORMAT_IS_UBWC(fmt) ||
727
-
!dpu_find_format(fmt->base.pixel_format, supported_formats, num_formats))
726
+
if (!MSM_FORMAT_IS_UBWC(fmt) ||
727
+
!dpu_find_format(fmt->pixel_format, supported_formats, num_formats))
728
728
return -EINVAL;
729
729
730
730
return 0;
···
733
733
static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu,
734
734
struct dpu_sw_pipe *pipe,
735
735
struct dpu_sw_pipe_cfg *pipe_cfg,
736
-
const struct dpu_format *fmt,
736
+
const struct msm_format *fmt,
737
737
const struct drm_display_mode *mode)
738
738
{
739
739
uint32_t min_src_size;
740
740
struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
741
741
742
-
min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1;
742
+
min_src_size = MSM_FORMAT_IS_YUV(fmt) ? 2 : 1;
743
743
744
-
if (DPU_FORMAT_IS_YUV(fmt) &&
744
+
if (MSM_FORMAT_IS_YUV(fmt) &&
745
745
(!pipe->sspp->cap->sblk->scaler_blk.len ||
746
746
!pipe->sspp->cap->sblk->csc_blk.len)) {
747
747
DPU_DEBUG_PLANE(pdpu,
···
758
758
}
759
759
760
760
/* valid yuv image */
761
-
if (DPU_FORMAT_IS_YUV(fmt) &&
761
+
if (MSM_FORMAT_IS_YUV(fmt) &&
762
762
(pipe_cfg->src_rect.x1 & 0x1 ||
763
763
pipe_cfg->src_rect.y1 & 0x1 ||
764
764
drm_rect_width(&pipe_cfg->src_rect) & 0x1 ||
···
798
798
struct dpu_sw_pipe *pipe = &pstate->pipe;
799
799
struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
800
800
const struct drm_crtc_state *crtc_state = NULL;
801
-
const struct dpu_format *fmt;
801
+
const struct msm_format *fmt;
802
802
struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
803
803
struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
804
804
struct drm_rect fb_rect = { 0 };
···
858
858
return -E2BIG;
859
859
}
860
860
861
-
fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb));
861
+
fmt = msm_framebuffer_format(new_plane_state->fb);
862
862
863
863
max_linewidth = pdpu->catalog->caps->max_linewidth;
864
864
···
870
870
* full width is more than max_linewidth, thus each rect is
871
871
* wider than allowed.
872
872
*/
873
-
if (DPU_FORMAT_IS_UBWC(fmt) &&
873
+
if (MSM_FORMAT_IS_UBWC(fmt) &&
874
874
drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) {
875
875
DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, tiled format\n",
876
876
DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
···
887
887
drm_rect_height(&pipe_cfg->src_rect) != drm_rect_height(&pipe_cfg->dst_rect) ||
888
888
(!test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) &&
889
889
!test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features)) ||
890
-
DPU_FORMAT_IS_YUV(fmt)) {
890
+
MSM_FORMAT_IS_YUV(fmt)) {
891
891
DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, can't use split source\n",
892
892
DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
893
893
return -E2BIG;
···
945
945
946
946
static void dpu_plane_flush_csc(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe)
947
947
{
948
-
const struct dpu_format *format =
949
-
to_dpu_format(msm_framebuffer_format(pdpu->base.state->fb));
948
+
const struct msm_format *format =
949
+
msm_framebuffer_format(pdpu->base.state->fb);
950
950
const struct dpu_csc_cfg *csc_ptr;
951
951
952
952
if (!pipe->sspp || !pipe->sspp->ops.setup_csc)
···
1017
1017
static void dpu_plane_sspp_update_pipe(struct drm_plane *plane,
1018
1018
struct dpu_sw_pipe *pipe,
1019
1019
struct dpu_sw_pipe_cfg *pipe_cfg,
1020
-
const struct dpu_format *fmt,
1020
+
const struct msm_format *fmt,
1021
1021
int frame_rate,
1022
1022
struct dpu_hw_fmt_layout *layout)
1023
1023
{
···
1095
1095
struct drm_crtc *crtc = state->crtc;
1096
1096
struct drm_framebuffer *fb = state->fb;
1097
1097
bool is_rt_pipe;
1098
-
const struct dpu_format *fmt =
1099
-
to_dpu_format(msm_framebuffer_format(fb));
1098
+
const struct msm_format *fmt =
1099
+
msm_framebuffer_format(fb);
1100
1100
struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
1101
1101
struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
1102
1102
struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
···
1120
1120
DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT
1121
1121
", %p4cc ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src),
1122
1122
crtc->base.id, DRM_RECT_ARG(&state->dst),
1123
-
&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt));
1123
+
&fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt));
1124
1124
1125
1125
dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt,
1126
1126
drm_mode_vrefresh(&crtc->mode),
+2
-2
drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
+2
-2
drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
···
182
182
enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
183
183
int idx = idxs[pipe_id];
184
184
if (idx > 0) {
185
-
const struct mdp_format *format =
186
-
to_mdp_format(msm_framebuffer_format(plane->state->fb));
185
+
const struct msm_format *format =
186
+
msm_framebuffer_format(plane->state->fb);
187
187
alpha[idx-1] = format->alpha_enable;
188
188
}
189
189
}
+13
-13
drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
+13
-13
drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
···
218
218
struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
219
219
struct mdp4_kms *mdp4_kms = get_kms(plane);
220
220
enum mdp4_pipe pipe = mdp4_plane->pipe;
221
-
const struct mdp_format *format;
221
+
const struct msm_format *format;
222
222
uint32_t op_mode = 0;
223
223
uint32_t phasex_step = MDP4_VG_PHASE_STEP_DEFAULT;
224
224
uint32_t phasey_step = MDP4_VG_PHASE_STEP_DEFAULT;
···
241
241
fb->base.id, src_x, src_y, src_w, src_h,
242
242
crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
243
243
244
-
format = to_mdp_format(msm_framebuffer_format(fb));
244
+
format = msm_framebuffer_format(fb);
245
245
246
246
if (src_w > (crtc_w * DOWN_SCALE_MAX)) {
247
247
DRM_DEV_ERROR(dev->dev, "Width down scaling exceeds limits!\n");
···
267
267
uint32_t sel_unit = SCALE_FIR;
268
268
op_mode |= MDP4_PIPE_OP_MODE_SCALEX_EN;
269
269
270
-
if (MDP_FORMAT_IS_YUV(format)) {
270
+
if (MSM_FORMAT_IS_YUV(format)) {
271
271
if (crtc_w > src_w)
272
272
sel_unit = SCALE_PIXEL_RPT;
273
273
else if (crtc_w <= (src_w / 4))
···
283
283
uint32_t sel_unit = SCALE_FIR;
284
284
op_mode |= MDP4_PIPE_OP_MODE_SCALEY_EN;
285
285
286
-
if (MDP_FORMAT_IS_YUV(format)) {
286
+
if (MSM_FORMAT_IS_YUV(format)) {
287
287
288
288
if (crtc_h > src_h)
289
289
sel_unit = SCALE_PIXEL_RPT;
···
316
316
317
317
mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_FORMAT(pipe),
318
318
MDP4_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
319
-
MDP4_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
320
-
MDP4_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
321
-
MDP4_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
319
+
MDP4_PIPE_SRC_FORMAT_R_BPC(format->bpc_r_cr) |
320
+
MDP4_PIPE_SRC_FORMAT_G_BPC(format->bpc_g_y) |
321
+
MDP4_PIPE_SRC_FORMAT_B_BPC(format->bpc_b_cb) |
322
322
COND(format->alpha_enable, MDP4_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
323
-
MDP4_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
323
+
MDP4_PIPE_SRC_FORMAT_CPP(format->bpp - 1) |
324
324
MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
325
325
MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(format->fetch_type) |
326
326
MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample) |
···
328
328
COND(format->unpack_tight, MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT));
329
329
330
330
mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_UNPACK(pipe),
331
-
MDP4_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
332
-
MDP4_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
333
-
MDP4_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
334
-
MDP4_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
331
+
MDP4_PIPE_SRC_UNPACK_ELEM0(format->element[0]) |
332
+
MDP4_PIPE_SRC_UNPACK_ELEM1(format->element[1]) |
333
+
MDP4_PIPE_SRC_UNPACK_ELEM2(format->element[2]) |
334
+
MDP4_PIPE_SRC_UNPACK_ELEM3(format->element[3]));
335
335
336
-
if (MDP_FORMAT_IS_YUV(format)) {
336
+
if (MSM_FORMAT_IS_YUV(format)) {
337
337
struct csc_cfg *csc = mdp_get_default_csc_cfg(CSC_YUV2RGB);
338
338
339
339
op_mode |= MDP4_PIPE_OP_MODE_SRC_YCBCR;
+3
-4
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+3
-4
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
···
216
216
struct mdp5_kms *mdp5_kms = get_kms(crtc);
217
217
struct drm_plane *plane;
218
218
struct mdp5_plane_state *pstate, *pstates[STAGE_MAX + 1] = {NULL};
219
-
const struct mdp_format *format;
219
+
const struct msm_format *format;
220
220
struct mdp5_hw_mixer *mixer = pipeline->mixer;
221
221
uint32_t lm = mixer->lm;
222
222
struct mdp5_hw_mixer *r_mixer = pipeline->r_mixer;
···
274
274
ctl_blend_flags |= MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT;
275
275
DBG("Border Color is enabled");
276
276
} else if (plane_cnt) {
277
-
format = to_mdp_format(msm_framebuffer_format(pstates[STAGE_BASE]->base.fb));
277
+
format = msm_framebuffer_format(pstates[STAGE_BASE]->base.fb);
278
278
279
279
if (format->alpha_enable)
280
280
bg_alpha_enabled = true;
···
285
285
if (!pstates[i])
286
286
continue;
287
287
288
-
format = to_mdp_format(
289
-
msm_framebuffer_format(pstates[i]->base.fb));
288
+
format = msm_framebuffer_format(pstates[i]->base.fb);
290
289
plane = pstates[i]->base.plane;
291
290
blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
292
291
MDP5_LM_BLEND_OP_MODE_BG_ALPHA(BG_CONST);
+27
-27
drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
+27
-27
drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
···
228
228
229
229
if (plane_enabled(state)) {
230
230
unsigned int rotation;
231
-
const struct mdp_format *format;
231
+
const struct msm_format *format;
232
232
struct mdp5_kms *mdp5_kms = get_kms(plane);
233
233
uint32_t blkcfg = 0;
234
234
235
-
format = to_mdp_format(msm_framebuffer_format(state->fb));
236
-
if (MDP_FORMAT_IS_YUV(format))
235
+
format = msm_framebuffer_format(state->fb);
236
+
if (MSM_FORMAT_IS_YUV(format))
237
237
caps |= MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC;
238
238
239
239
if (((state->src_w >> 16) != state->crtc_w) ||
···
268
268
new_hwpipe = true;
269
269
270
270
if (mdp5_kms->smp) {
271
-
const struct mdp_format *format =
272
-
to_mdp_format(msm_framebuffer_format(state->fb));
271
+
const struct msm_format *format =
272
+
msm_framebuffer_format(state->fb);
273
273
274
274
blkcfg = mdp5_smp_calculate(mdp5_kms->smp, format,
275
275
state->src_w >> 16, false);
···
630
630
return 0;
631
631
}
632
632
633
-
static uint32_t get_scale_config(const struct mdp_format *format,
633
+
static uint32_t get_scale_config(const struct msm_format *format,
634
634
uint32_t src, uint32_t dst, bool horz)
635
635
{
636
-
const struct drm_format_info *info = drm_format_info(format->base.pixel_format);
637
-
bool yuv = MDP_FORMAT_IS_YUV(format);
636
+
const struct drm_format_info *info = drm_format_info(format->pixel_format);
637
+
bool yuv = MSM_FORMAT_IS_YUV(format);
638
638
bool scaling = yuv ? true : (src != dst);
639
639
uint32_t sub;
640
640
uint32_t ya_filter, uv_filter;
···
661
661
COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter));
662
662
}
663
663
664
-
static void calc_pixel_ext(const struct mdp_format *format,
664
+
static void calc_pixel_ext(const struct msm_format *format,
665
665
uint32_t src, uint32_t dst, uint32_t phase_step[2],
666
666
int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX],
667
667
bool horz)
668
668
{
669
-
bool scaling = MDP_FORMAT_IS_YUV(format) ? true : (src != dst);
669
+
bool scaling = MSM_FORMAT_IS_YUV(format) ? true : (src != dst);
670
670
int i;
671
671
672
672
/*
···
684
684
}
685
685
686
686
static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
687
-
const struct mdp_format *format,
687
+
const struct msm_format *format,
688
688
uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX],
689
689
uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX])
690
690
{
691
-
const struct drm_format_info *info = drm_format_info(format->base.pixel_format);
691
+
const struct drm_format_info *info = drm_format_info(format->pixel_format);
692
692
uint32_t lr, tb, req;
693
693
int i;
694
694
···
696
696
uint32_t roi_w = src_w;
697
697
uint32_t roi_h = src_h;
698
698
699
-
if (MDP_FORMAT_IS_YUV(format) && i == COMP_1_2) {
699
+
if (MSM_FORMAT_IS_YUV(format) && i == COMP_1_2) {
700
700
roi_w /= info->hsub;
701
701
roi_h /= info->vsub;
702
702
}
···
770
770
{
771
771
enum mdp5_pipe pipe = hwpipe->pipe;
772
772
bool has_pe = hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT;
773
-
const struct mdp_format *format =
774
-
to_mdp_format(msm_framebuffer_format(fb));
773
+
const struct msm_format *format =
774
+
msm_framebuffer_format(fb);
775
775
776
776
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe),
777
777
MDP5_PIPE_SRC_IMG_SIZE_WIDTH(src_img_w) |
···
795
795
796
796
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe),
797
797
MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
798
-
MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
799
-
MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
800
-
MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
798
+
MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r_cr) |
799
+
MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g_y) |
800
+
MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b_cb) |
801
801
COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
802
-
MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
802
+
MDP5_PIPE_SRC_FORMAT_CPP(format->bpp - 1) |
803
803
MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
804
804
COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
805
805
MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) |
806
806
MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample));
807
807
808
808
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe),
809
-
MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
810
-
MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
811
-
MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
812
-
MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
809
+
MDP5_PIPE_SRC_UNPACK_ELEM0(format->element[0]) |
810
+
MDP5_PIPE_SRC_UNPACK_ELEM1(format->element[1]) |
811
+
MDP5_PIPE_SRC_UNPACK_ELEM2(format->element[2]) |
812
+
MDP5_PIPE_SRC_UNPACK_ELEM3(format->element[3]));
813
813
814
814
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe),
815
815
(hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) |
···
842
842
}
843
843
844
844
if (hwpipe->caps & MDP_PIPE_CAP_CSC) {
845
-
if (MDP_FORMAT_IS_YUV(format))
845
+
if (MSM_FORMAT_IS_YUV(format))
846
846
csc_enable(mdp5_kms, pipe,
847
847
mdp_get_default_csc_cfg(CSC_YUV2RGB));
848
848
else
···
861
861
struct mdp5_kms *mdp5_kms = get_kms(plane);
862
862
enum mdp5_pipe pipe = hwpipe->pipe;
863
863
struct mdp5_hw_pipe *right_hwpipe;
864
-
const struct mdp_format *format;
864
+
const struct msm_format *format;
865
865
uint32_t nplanes, config = 0;
866
866
struct phase_step step = { { 0 } };
867
867
struct pixel_ext pe = { { 0 } };
···
882
882
if (WARN_ON(nplanes > pipe2nclients(pipe)))
883
883
return -EINVAL;
884
884
885
-
format = to_mdp_format(msm_framebuffer_format(fb));
886
-
pix_format = format->base.pixel_format;
885
+
format = msm_framebuffer_format(fb);
886
+
pix_format = format->pixel_format;
887
887
888
888
src_x = src->x1;
889
889
src_y = src->y1;
+2
-2
drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c
+2
-2
drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c
···
114
114
* presumably happens during the dma from scanout buffer).
115
115
*/
116
116
uint32_t mdp5_smp_calculate(struct mdp5_smp *smp,
117
-
const struct mdp_format *format,
117
+
const struct msm_format *format,
118
118
u32 width, bool hdecim)
119
119
{
120
-
const struct drm_format_info *info = drm_format_info(format->base.pixel_format);
120
+
const struct drm_format_info *info = drm_format_info(format->pixel_format);
121
121
struct mdp5_kms *mdp5_kms = get_kms(smp);
122
122
int rev = mdp5_cfg_get_hw_rev(mdp5_kms->cfg);
123
123
int i, hsub, nplanes, nlines;
+1
-1
drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h
+1
-1
drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h
···
74
74
struct mdp5_global_state *global_state);
75
75
76
76
uint32_t mdp5_smp_calculate(struct mdp5_smp *smp,
77
-
const struct mdp_format *format,
77
+
const struct msm_format *format,
78
78
u32 width, bool hdecim);
79
79
80
80
int mdp5_smp_assign(struct mdp5_smp *smp, struct mdp5_smp_state *state,
+14
-16
drivers/gpu/drm/msm/disp/mdp_format.c
+14
-16
drivers/gpu/drm/msm/disp/mdp_format.c
···
63
63
};
64
64
65
65
#define FMT(name, a, r, g, b, e0, e1, e2, e3, alpha, tight, c, cnt, fp, cs, yuv) { \
66
-
.base = { \
67
-
.pixel_format = DRM_FORMAT_ ## name, \
68
-
.flags = yuv ? MSM_FORMAT_FLAG_YUV : 0, \
69
-
}, \
66
+
.pixel_format = DRM_FORMAT_ ## name, \
70
67
.bpc_a = BPC ## a ## A, \
71
-
.bpc_r = BPC ## r, \
72
-
.bpc_g = BPC ## g, \
73
-
.bpc_b = BPC ## b, \
74
-
.unpack = { e0, e1, e2, e3 }, \
75
-
.alpha_enable = alpha, \
76
-
.unpack_tight = tight, \
77
-
.cpp = c, \
78
-
.unpack_count = cnt, \
68
+
.bpc_r_cr = BPC ## r, \
69
+
.bpc_g_y = BPC ## g, \
70
+
.bpc_b_cb = BPC ## b, \
71
+
.element = { e0, e1, e2, e3 }, \
79
72
.fetch_type = fp, \
80
73
.chroma_sample = cs, \
74
+
.alpha_enable = alpha, \
75
+
.unpack_tight = tight, \
76
+
.unpack_count = cnt, \
77
+
.bpp = c, \
78
+
.flags = yuv ? MSM_FORMAT_FLAG_YUV : 0, \
81
79
}
82
80
83
81
#define BPC0A 0
84
82
85
-
static const struct mdp_format formats[] = {
83
+
static const struct msm_format formats[] = {
86
84
/* name a r g b e0 e1 e2 e3 alpha tight cpp cnt ... */
87
85
FMT(ARGB8888, 8, 8, 8, 8, 1, 0, 2, 3, true, true, 4, 4,
88
86
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
···
139
141
{
140
142
int i;
141
143
for (i = 0; i < ARRAY_SIZE(formats); i++) {
142
-
const struct mdp_format *f = &formats[i];
143
-
if (f->base.pixel_format == format)
144
-
return &f->base;
144
+
const struct msm_format *f = &formats[i];
145
+
if (f->pixel_format == format)
146
+
return f;
145
147
}
146
148
return NULL;
147
149
}
+28
drivers/gpu/drm/msm/disp/mdp_format.h
+28
drivers/gpu/drm/msm/disp/mdp_format.h
···
20
20
#define MSM_FORMAT_FLAG_DX BIT(MSM_FORMAT_FLAG_DX_BIT)
21
21
#define MSM_FORMAT_FLAG_COMPRESSED BIT(MSM_FORMAT_FLAG_COMPRESSED_BIT)
22
22
23
+
/**
24
+
* struct msm_format: defines the format configuration
25
+
* @pixel_format: format fourcc
26
+
* @element: element color ordering
27
+
* @fetch_type: how the color components are packed in pixel format
28
+
* @chroma_sample: chroma sub-samplng type
29
+
* @alpha_enable: whether the format has an alpha channel
30
+
* @unpack_tight: whether to use tight or loose unpack
31
+
* @unpack_align_msb: unpack aligned to LSB or MSB
32
+
* @unpack_count: number of the components to unpack
33
+
* @bpp: bytes per pixel
34
+
* @flags: usage bit flags
35
+
* @num_planes: number of planes (including meta data planes)
36
+
* @fetch_mode: linear, tiled, or ubwc hw fetch behavior
37
+
* @tile_height: format tile height
38
+
*/
23
39
struct msm_format {
24
40
uint32_t pixel_format;
41
+
enum mdp_bpc bpc_g_y, bpc_b_cb, bpc_r_cr;
42
+
enum mdp_bpc_alpha bpc_a;
43
+
u8 element[4];
44
+
enum mdp_fetch_type fetch_type;
45
+
enum mdp_chroma_samp_type chroma_sample;
46
+
bool alpha_enable;
47
+
u8 unpack_tight;
48
+
u8 unpack_align_msb;
49
+
u8 unpack_count;
50
+
u8 bpp;
25
51
unsigned long flags;
52
+
u8 num_planes;
26
53
enum mdp_fetch_mode fetch_mode;
54
+
u16 tile_height;
27
55
};
28
56
29
57
#define MSM_FORMAT_IS_YUV(X) ((X)->flags & MSM_FORMAT_FLAG_YUV)
-13
drivers/gpu/drm/msm/disp/mdp_kms.h
-13
drivers/gpu/drm/msm/disp/mdp_kms.h
···
78
78
* pixel format helpers:
79
79
*/
80
80
81
-
struct mdp_format {
82
-
struct msm_format base;
83
-
enum mdp_bpc bpc_r, bpc_g, bpc_b;
84
-
enum mdp_bpc_alpha bpc_a;
85
-
uint8_t unpack[4];
86
-
bool alpha_enable, unpack_tight;
87
-
uint8_t cpp, unpack_count;
88
-
enum mdp_fetch_type fetch_type;
89
-
enum mdp_chroma_samp_type chroma_sample;
90
-
};
91
-
#define to_mdp_format(x) container_of(x, struct mdp_format, base)
92
-
#define MDP_FORMAT_IS_YUV(mdp_format) (MSM_FORMAT_IS_YUV(&(mdp_format)->base))
93
-
94
81
const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier);
95
82
96
83
/* MDP capabilities */