Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
spi: axi-spi-engine: support SPI_MULTI_LANE_MODE_STRIPE
Add support for SPI_MULTI_LANE_MODE_STRIPE to the AXI SPI engine driver.
The v2.0.0 version of the AXI SPI Engine IP core supports multiple
lanes. This can be used with SPI_MULTI_LANE_MODE_STRIPE to support
reading from simultaneous sampling ADCs that have a separate SDO line
for each analog channel. This allows reading all channels at the same
time to increase throughput.
Reviewed-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://patch.msgid.link/20260123-spi-add-multi-bus-support-v6-7-12af183c06eb@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>
authored by
David Lechner
and committed by
Mark Brown
0ec5ed7c
2e706f86
+141
-4
+141
-4
drivers/spi/spi-axi-spi-engine.c
+141
-4
drivers/spi/spi-axi-spi-engine.c
···
23
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#include <linux/spi/spi.h>
24
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#include <trace/events/spi.h>
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26
+
#define SPI_ENGINE_REG_DATA_WIDTH 0x0C
27
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#define SPI_ENGINE_REG_DATA_WIDTH_NUM_OF_SDIO_MASK GENMASK(23, 16)
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#define SPI_ENGINE_REG_DATA_WIDTH_MASK GENMASK(15, 0)
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#define SPI_ENGINE_REG_OFFLOAD_MEM_ADDR_WIDTH 0x10
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#define SPI_ENGINE_REG_RESET 0x40
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···
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#define SPI_ENGINE_CMD_REG_CLK_DIV 0x0
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#define SPI_ENGINE_CMD_REG_CONFIG 0x1
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#define SPI_ENGINE_CMD_REG_XFER_BITS 0x2
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+
#define SPI_ENGINE_CMD_REG_SDI_MASK 0x3
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+
#define SPI_ENGINE_CMD_REG_SDO_MASK 0x4
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#define SPI_ENGINE_MISC_SYNC 0x0
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#define SPI_ENGINE_MISC_SLEEP 0x1
···
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/* default sizes - can be changed when SPI Engine firmware is compiled */
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#define SPI_ENGINE_OFFLOAD_CMD_FIFO_SIZE 16
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#define SPI_ENGINE_OFFLOAD_SDO_FIFO_SIZE 16
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/* Extending SPI_MULTI_LANE_MODE values for optimizing messages. */
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#define SPI_ENGINE_MULTI_BUS_MODE_UNKNOWN -1
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#define SPI_ENGINE_MULTI_BUS_MODE_CONFLICTING -2
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struct spi_engine_program {
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unsigned int length;
···
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unsigned long flags;
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unsigned int offload_num;
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unsigned int spi_mode_config;
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unsigned int multi_lane_mode;
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u8 rx_primary_lane_mask;
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u8 tx_primary_lane_mask;
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u8 rx_all_lanes_mask;
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u8 tx_all_lanes_mask;
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u8 bits_per_word;
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};
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···
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u32 offload_caps;
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bool offload_requires_sync;
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};
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static void spi_engine_primary_lane_flag(struct spi_device *spi,
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u8 *rx_lane_flags, u8 *tx_lane_flags)
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{
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*rx_lane_flags = BIT(spi->rx_lane_map[0]);
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*tx_lane_flags = BIT(spi->tx_lane_map[0]);
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}
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static void spi_engine_all_lanes_flags(struct spi_device *spi,
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u8 *rx_lane_flags, u8 *tx_lane_flags)
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{
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int i;
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for (i = 0; i < spi->num_rx_lanes; i++)
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*rx_lane_flags |= BIT(spi->rx_lane_map[i]);
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+
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for (i = 0; i < spi->num_tx_lanes; i++)
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*tx_lane_flags |= BIT(spi->tx_lane_map[i]);
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}
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static void spi_engine_program_add_cmd(struct spi_engine_program *p,
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bool dry, uint16_t cmd)
···
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}
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static void spi_engine_gen_xfer(struct spi_engine_program *p, bool dry,
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-
struct spi_transfer *xfer)
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struct spi_transfer *xfer, u32 num_lanes)
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{
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unsigned int len;
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···
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len = xfer->len / 2;
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else
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len = xfer->len / 4;
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if (xfer->multi_lane_mode == SPI_MULTI_LANE_MODE_STRIPE)
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len /= num_lanes;
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while (len) {
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unsigned int n = min(len, 256U);
···
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{
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unsigned int clk_div, max_hz = msg->spi->controller->max_speed_hz;
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struct spi_transfer *xfer;
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int multi_lane_mode = SPI_ENGINE_MULTI_BUS_MODE_UNKNOWN;
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u8 min_bits_per_word = U8_MAX;
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u8 max_bits_per_word = 0;
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···
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min_bits_per_word = min(min_bits_per_word, xfer->bits_per_word);
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max_bits_per_word = max(max_bits_per_word, xfer->bits_per_word);
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}
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if (xfer->rx_buf || xfer->offload_flags & SPI_OFFLOAD_XFER_RX_STREAM ||
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xfer->tx_buf || xfer->offload_flags & SPI_OFFLOAD_XFER_TX_STREAM) {
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switch (xfer->multi_lane_mode) {
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case SPI_MULTI_LANE_MODE_SINGLE:
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case SPI_MULTI_LANE_MODE_STRIPE:
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break;
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default:
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/* Other modes, like mirror not supported */
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return -EINVAL;
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}
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/* If all xfers have the same multi-lane mode, we can optimize. */
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if (multi_lane_mode == SPI_ENGINE_MULTI_BUS_MODE_UNKNOWN)
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multi_lane_mode = xfer->multi_lane_mode;
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else if (multi_lane_mode != xfer->multi_lane_mode)
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multi_lane_mode = SPI_ENGINE_MULTI_BUS_MODE_CONFLICTING;
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}
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}
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/*
···
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priv->bits_per_word = min_bits_per_word;
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else
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priv->bits_per_word = 0;
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priv->multi_lane_mode = multi_lane_mode;
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spi_engine_primary_lane_flag(msg->spi,
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&priv->rx_primary_lane_mask,
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&priv->tx_primary_lane_mask);
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spi_engine_all_lanes_flags(msg->spi,
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&priv->rx_all_lanes_mask,
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&priv->tx_all_lanes_mask);
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}
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return 0;
···
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struct spi_engine_offload *priv;
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struct spi_transfer *xfer;
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int clk_div, new_clk_div, inst_ns;
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int prev_multi_lane_mode = SPI_MULTI_LANE_MODE_SINGLE;
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bool keep_cs = false;
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u8 bits_per_word = 0;
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···
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* in the same way.
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*/
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bits_per_word = priv->bits_per_word;
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prev_multi_lane_mode = priv->multi_lane_mode;
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} else {
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spi_engine_program_add_cmd(p, dry,
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SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CONFIG,
···
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spi_engine_gen_cs(p, dry, spi, !xfer->cs_off);
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list_for_each_entry(xfer, &msg->transfers, transfer_list) {
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if (xfer->rx_buf || xfer->offload_flags & SPI_OFFLOAD_XFER_RX_STREAM ||
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xfer->tx_buf || xfer->offload_flags & SPI_OFFLOAD_XFER_TX_STREAM) {
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if (xfer->multi_lane_mode != prev_multi_lane_mode) {
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u8 tx_lane_flags, rx_lane_flags;
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if (xfer->multi_lane_mode == SPI_MULTI_LANE_MODE_STRIPE)
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spi_engine_all_lanes_flags(spi, &rx_lane_flags,
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&tx_lane_flags);
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else
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spi_engine_primary_lane_flag(spi, &rx_lane_flags,
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&tx_lane_flags);
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spi_engine_program_add_cmd(p, dry,
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SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK,
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rx_lane_flags));
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spi_engine_program_add_cmd(p, dry,
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SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK,
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tx_lane_flags));
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}
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prev_multi_lane_mode = xfer->multi_lane_mode;
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}
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new_clk_div = host->max_speed_hz / xfer->effective_speed_hz;
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if (new_clk_div != clk_div) {
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clk_div = new_clk_div;
···
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bits_per_word));
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}
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spi_engine_gen_xfer(p, dry, xfer);
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spi_engine_gen_xfer(p, dry, xfer, spi->num_rx_lanes);
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spi_engine_gen_sleep(p, dry, spi_delay_to_ns(&xfer->delay, xfer),
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inst_ns, xfer->effective_speed_hz);
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···
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if (clk_div != 1)
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spi_engine_program_add_cmd(p, dry,
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SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CLK_DIV, 0));
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/* Restore single lane mode unless offload disable will restore it later. */
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if (prev_multi_lane_mode == SPI_MULTI_LANE_MODE_STRIPE &&
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(!msg->offload || priv->multi_lane_mode != SPI_MULTI_LANE_MODE_STRIPE)) {
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u8 rx_lane_flags, tx_lane_flags;
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spi_engine_primary_lane_flag(spi, &rx_lane_flags, &tx_lane_flags);
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spi_engine_program_add_cmd(p, dry,
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SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK, rx_lane_flags));
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spi_engine_program_add_cmd(p, dry,
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SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK, tx_lane_flags));
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}
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}
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static void spi_engine_xfer_next(struct spi_message *msg,
···
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writel_relaxed(SPI_ENGINE_CMD_CS_INV(spi_engine->cs_inv),
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spi_engine->base + SPI_ENGINE_REG_CMD_FIFO);
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if (host->num_data_lanes > 1) {
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u8 rx_lane_flags, tx_lane_flags;
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spi_engine_primary_lane_flag(device, &rx_lane_flags, &tx_lane_flags);
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writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK,
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rx_lane_flags),
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spi_engine->base + SPI_ENGINE_REG_CMD_FIFO);
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writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK,
811
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tx_lane_flags),
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spi_engine->base + SPI_ENGINE_REG_CMD_FIFO);
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}
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/*
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* In addition to setting the flags, we have to do a CS assert command
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* to make the new setting actually take effect.
···
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priv->bits_per_word),
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spi_engine->base + SPI_ENGINE_REG_CMD_FIFO);
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if (priv->multi_lane_mode == SPI_MULTI_LANE_MODE_STRIPE) {
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writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK,
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priv->rx_all_lanes_mask),
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spi_engine->base + SPI_ENGINE_REG_CMD_FIFO);
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writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK,
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priv->tx_all_lanes_mask),
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spi_engine->base + SPI_ENGINE_REG_CMD_FIFO);
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}
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writel_relaxed(SPI_ENGINE_CMD_SYNC(1),
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spi_engine->base + SPI_ENGINE_REG_CMD_FIFO);
1020
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···
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reg &= ~SPI_ENGINE_OFFLOAD_CTRL_ENABLE;
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writel_relaxed(reg, spi_engine->base +
1053
931
SPI_ENGINE_REG_OFFLOAD_CTRL(priv->offload_num));
932
+
933
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/* Restore single-lane mode. */
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if (priv->multi_lane_mode == SPI_MULTI_LANE_MODE_STRIPE) {
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writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK,
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+
priv->rx_primary_lane_mask),
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spi_engine->base + SPI_ENGINE_REG_CMD_FIFO);
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writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK,
939
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priv->tx_primary_lane_mask),
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spi_engine->base + SPI_ENGINE_REG_CMD_FIFO);
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}
1054
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}
1055
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static struct dma_chan
···
1105
973
{
1106
974
struct spi_engine *spi_engine;
1107
975
struct spi_controller *host;
1108
-
unsigned int version;
976
+
unsigned int version, data_width_reg_val;
1109
977
int irq, ret;
1110
978
1111
979
irq = platform_get_irq(pdev, 0);
···
1174
1042
return PTR_ERR(spi_engine->base);
1175
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1176
1044
version = readl(spi_engine->base + ADI_AXI_REG_VERSION);
1177
-
if (ADI_AXI_PCORE_VER_MAJOR(version) != 1) {
1045
+
if (ADI_AXI_PCORE_VER_MAJOR(version) > 2) {
1178
1046
dev_err(&pdev->dev, "Unsupported peripheral version %u.%u.%u\n",
1179
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ADI_AXI_PCORE_VER_MAJOR(version),
1180
1048
ADI_AXI_PCORE_VER_MINOR(version),
1181
1049
ADI_AXI_PCORE_VER_PATCH(version));
1182
1050
return -ENODEV;
1183
1051
}
1052
+
1053
+
data_width_reg_val = readl(spi_engine->base + SPI_ENGINE_REG_DATA_WIDTH);
1184
1054
1185
1055
if (adi_axi_pcore_ver_gteq(version, 1, 1)) {
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unsigned int sizes = readl(spi_engine->base +
···
1231
1097
}
1232
1098
if (adi_axi_pcore_ver_gteq(version, 1, 3))
1233
1099
host->mode_bits |= SPI_MOSI_IDLE_LOW | SPI_MOSI_IDLE_HIGH;
1100
+
if (adi_axi_pcore_ver_gteq(version, 2, 0))
1101
+
host->num_data_lanes = FIELD_GET(SPI_ENGINE_REG_DATA_WIDTH_NUM_OF_SDIO_MASK,
1102
+
data_width_reg_val);
1234
1103
1235
1104
if (host->max_speed_hz == 0)
1236
1105
return dev_err_probe(&pdev->dev, -EINVAL, "spi_clk rate is 0");