+148 -79

arch/arm/configs/omap_h2_1610_defconfig

reviewed

··· 1 1 # 2 2 # Automatically generated make config: don't edit 3 3 - # Linux kernel version: 2.6.23-rc6 4 4 - # Mon Sep 17 14:21:45 2007 3 3 + # Linux kernel version: 2.6.24-rc5 4 4 + # Mon Dec 17 20:04:38 2007 5 5 # 6 6 CONFIG_ARM=y 7 7 CONFIG_SYS_SUPPORTS_APM_EMULATION=y ··· 41 41 # CONFIG_BSD_PROCESS_ACCT is not set 42 42 # CONFIG_TASKSTATS is not set 43 43 # CONFIG_USER_NS is not set 44 44 + # CONFIG_PID_NS is not set 44 45 # CONFIG_AUDIT is not set 45 46 # CONFIG_IKCONFIG is not set 46 47 CONFIG_LOG_BUF_SHIFT=14 48 48 + # CONFIG_CGROUPS is not set 49 49 + CONFIG_FAIR_GROUP_SCHED=y 50 50 + CONFIG_FAIR_USER_SCHED=y 51 51 + # CONFIG_FAIR_CGROUP_SCHED is not set 47 52 # CONFIG_SYSFS_DEPRECATED is not set 48 53 # CONFIG_RELAY is not set 49 54 CONFIG_BLK_DEV_INITRD=y ··· 69 64 CONFIG_ANON_INODES=y 70 65 CONFIG_EPOLL=y 71 66 CONFIG_SIGNALFD=y 72 72 - CONFIG_TIMERFD=y 73 67 CONFIG_EVENTFD=y 74 68 CONFIG_SHMEM=y 75 69 CONFIG_VM_EVENT_COUNTERS=y ··· 228 224 # 229 225 # CONFIG_PCI_SYSCALL is not set 230 226 # CONFIG_ARCH_SUPPORTS_MSI is not set 231 231 - 232 232 - # 233 233 - # PCCARD (PCMCIA/CardBus) support 234 234 - # 235 227 # CONFIG_PCCARD is not set 236 228 237 229 # ··· 236 236 CONFIG_TICK_ONESHOT=y 237 237 CONFIG_NO_HZ=y 238 238 CONFIG_HIGH_RES_TIMERS=y 239 239 + CONFIG_GENERIC_CLOCKEVENTS_BUILD=y 239 240 CONFIG_PREEMPT=y 240 241 CONFIG_HZ=128 241 242 CONFIG_AEABI=y ··· 249 248 CONFIG_FLATMEM=y 250 249 CONFIG_FLAT_NODE_MEM_MAP=y 251 250 # CONFIG_SPARSEMEM_STATIC is not set 251 251 + # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 252 252 CONFIG_SPLIT_PTLOCK_CPUS=4096 253 253 # CONFIG_RESOURCES_64BIT is not set 254 254 CONFIG_ZONE_DMA_FLAG=1 ··· 277 275 # CONFIG_CPU_FREQ_STAT_DETAILS is not set 278 276 # CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set 279 277 CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y 278 278 + # CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set 279 279 + # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set 280 280 # CONFIG_CPU_FREQ_GOV_PERFORMANCE is not set 281 281 # CONFIG_CPU_FREQ_GOV_POWERSAVE is not set 282 282 CONFIG_CPU_FREQ_GOV_USERSPACE=y ··· 351 347 CONFIG_INET_XFRM_MODE_TRANSPORT=y 352 348 CONFIG_INET_XFRM_MODE_TUNNEL=y 353 349 CONFIG_INET_XFRM_MODE_BEET=y 350 350 + # CONFIG_INET_LRO is not set 354 351 CONFIG_INET_DIAG=y 355 352 CONFIG_INET_TCP_DIAG=y 356 353 # CONFIG_TCP_CONG_ADVANCED is not set ··· 377 372 # CONFIG_LAPB is not set 378 373 # CONFIG_ECONET is not set 379 374 # CONFIG_WAN_ROUTER is not set 380 380 - 381 381 - # 382 382 - # QoS and/or fair queueing 383 383 - # 384 375 # CONFIG_NET_SCHED is not set 385 376 386 377 # ··· 405 404 # 406 405 # Generic Driver Options 407 406 # 407 407 + CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 408 408 CONFIG_STANDALONE=y 409 409 CONFIG_PREVENT_FIRMWARE_BUILD=y 410 410 # CONFIG_FW_LOADER is not set ··· 424 422 CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 425 423 # CONFIG_CDROM_PKTCDVD is not set 426 424 CONFIG_ATA_OVER_ETH=m 425 425 + CONFIG_MISC_DEVICES=y 426 426 + # CONFIG_EEPROM_93CX6 is not set 427 427 428 428 # 429 429 # SCSI device support ··· 463 459 # CONFIG_SCSI_FC_ATTRS is not set 464 460 # CONFIG_SCSI_ISCSI_ATTRS is not set 465 461 # CONFIG_SCSI_SAS_LIBSAS is not set 462 462 + # CONFIG_SCSI_SRP_ATTRS is not set 466 463 CONFIG_SCSI_LOWLEVEL=y 467 464 # CONFIG_ISCSI_TCP is not set 468 465 # CONFIG_SCSI_DEBUG is not set ··· 476 471 # CONFIG_MACVLAN is not set 477 472 # CONFIG_EQUALIZER is not set 478 473 # CONFIG_TUN is not set 474 474 + # CONFIG_VETH is not set 479 475 # CONFIG_PHYLIB is not set 480 476 CONFIG_NET_ETHERNET=y 481 477 CONFIG_MII=y 482 478 # CONFIG_AX88796 is not set 483 479 CONFIG_SMC91X=y 484 480 # CONFIG_DM9000 is not set 481 481 + # CONFIG_IBM_NEW_EMAC_ZMII is not set 482 482 + # CONFIG_IBM_NEW_EMAC_RGMII is not set 483 483 + # CONFIG_IBM_NEW_EMAC_TAH is not set 484 484 + # CONFIG_IBM_NEW_EMAC_EMAC4 is not set 485 485 + # CONFIG_B44 is not set 485 486 CONFIG_NETDEV_1000=y 486 487 CONFIG_NETDEV_10000=y 487 488 ··· 533 522 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 534 523 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 535 524 # CONFIG_INPUT_JOYDEV is not set 536 536 - # CONFIG_INPUT_TSDEV is not set 537 525 CONFIG_INPUT_EVDEV=y 538 526 CONFIG_INPUT_EVBUG=y 539 527 ··· 586 576 CONFIG_UNIX98_PTYS=y 587 577 # CONFIG_LEGACY_PTYS is not set 588 578 # CONFIG_IPMI_HANDLER is not set 579 579 + # CONFIG_HW_RANDOM is not set 580 580 + # CONFIG_NVRAM is not set 581 581 + # CONFIG_R3964 is not set 582 582 + # CONFIG_RAW_DRIVER is not set 583 583 + # CONFIG_TCG_TPM is not set 584 584 + CONFIG_I2C=y 585 585 + CONFIG_I2C_BOARDINFO=y 586 586 + # CONFIG_I2C_CHARDEV is not set 587 587 + 588 588 + # 589 589 + # I2C Algorithms 590 590 + # 591 591 + # CONFIG_I2C_ALGOBIT is not set 592 592 + # CONFIG_I2C_ALGOPCF is not set 593 593 + # CONFIG_I2C_ALGOPCA is not set 594 594 + 595 595 + # 596 596 + # I2C Hardware Bus support 597 597 + # 598 598 + # CONFIG_I2C_GPIO is not set 599 599 + # CONFIG_I2C_OCORES is not set 600 600 + CONFIG_I2C_OMAP=y 601 601 + # CONFIG_I2C_PARPORT_LIGHT is not set 602 602 + # CONFIG_I2C_SIMTEC is not set 603 603 + # CONFIG_I2C_TAOS_EVM is not set 604 604 + # CONFIG_I2C_STUB is not set 605 605 + 606 606 + # 607 607 + # Miscellaneous I2C Chip support 608 608 + # 609 609 + # CONFIG_SENSORS_DS1337 is not set 610 610 + # CONFIG_SENSORS_DS1374 is not set 611 611 + # CONFIG_DS1682 is not set 612 612 + # CONFIG_SENSORS_EEPROM is not set 613 613 + # CONFIG_SENSORS_PCF8574 is not set 614 614 + # CONFIG_SENSORS_PCA9539 is not set 615 615 + # CONFIG_SENSORS_PCF8591 is not set 616 616 + # CONFIG_ISP1301_OMAP is not set 617 617 + CONFIG_TPS65010=y 618 618 + # CONFIG_SENSORS_MAX6875 is not set 619 619 + # CONFIG_SENSORS_TSL2550 is not set 620 620 + # CONFIG_I2C_DEBUG_CORE is not set 621 621 + # CONFIG_I2C_DEBUG_ALGO is not set 622 622 + # CONFIG_I2C_DEBUG_BUS is not set 623 623 + # CONFIG_I2C_DEBUG_CHIP is not set 624 624 + 625 625 + # 626 626 + # SPI support 627 627 + # 628 628 + # CONFIG_SPI is not set 629 629 + # CONFIG_SPI_MASTER is not set 630 630 + # CONFIG_W1 is not set 631 631 + # CONFIG_POWER_SUPPLY is not set 632 632 + CONFIG_HWMON=y 633 633 + # CONFIG_HWMON_VID is not set 634 634 + # CONFIG_SENSORS_AD7418 is not set 635 635 + # CONFIG_SENSORS_ADM1021 is not set 636 636 + # CONFIG_SENSORS_ADM1025 is not set 637 637 + # CONFIG_SENSORS_ADM1026 is not set 638 638 + # CONFIG_SENSORS_ADM1029 is not set 639 639 + # CONFIG_SENSORS_ADM1031 is not set 640 640 + # CONFIG_SENSORS_ADM9240 is not set 641 641 + # CONFIG_SENSORS_ADT7470 is not set 642 642 + # CONFIG_SENSORS_ATXP1 is not set 643 643 + # CONFIG_SENSORS_DS1621 is not set 644 644 + # CONFIG_SENSORS_F71805F is not set 645 645 + # CONFIG_SENSORS_F71882FG is not set 646 646 + # CONFIG_SENSORS_F75375S is not set 647 647 + # CONFIG_SENSORS_GL518SM is not set 648 648 + # CONFIG_SENSORS_GL520SM is not set 649 649 + # CONFIG_SENSORS_IT87 is not set 650 650 + # CONFIG_SENSORS_LM63 is not set 651 651 + # CONFIG_SENSORS_LM75 is not set 652 652 + # CONFIG_SENSORS_LM77 is not set 653 653 + # CONFIG_SENSORS_LM78 is not set 654 654 + # CONFIG_SENSORS_LM80 is not set 655 655 + # CONFIG_SENSORS_LM83 is not set 656 656 + # CONFIG_SENSORS_LM85 is not set 657 657 + # CONFIG_SENSORS_LM87 is not set 658 658 + # CONFIG_SENSORS_LM90 is not set 659 659 + # CONFIG_SENSORS_LM92 is not set 660 660 + # CONFIG_SENSORS_LM93 is not set 661 661 + # CONFIG_SENSORS_MAX1619 is not set 662 662 + # CONFIG_SENSORS_MAX6650 is not set 663 663 + # CONFIG_SENSORS_PC87360 is not set 664 664 + # CONFIG_SENSORS_PC87427 is not set 665 665 + # CONFIG_SENSORS_DME1737 is not set 666 666 + # CONFIG_SENSORS_SMSC47M1 is not set 667 667 + # CONFIG_SENSORS_SMSC47M192 is not set 668 668 + # CONFIG_SENSORS_SMSC47B397 is not set 669 669 + # CONFIG_SENSORS_THMC50 is not set 670 670 + # CONFIG_SENSORS_VT1211 is not set 671 671 + # CONFIG_SENSORS_W83781D is not set 672 672 + # CONFIG_SENSORS_W83791D is not set 673 673 + # CONFIG_SENSORS_W83792D is not set 674 674 + # CONFIG_SENSORS_W83793 is not set 675 675 + # CONFIG_SENSORS_W83L785TS is not set 676 676 + # CONFIG_SENSORS_W83627HF is not set 677 677 + # CONFIG_SENSORS_W83627EHF is not set 678 678 + # CONFIG_HWMON_DEBUG_CHIP is not set 589 679 CONFIG_WATCHDOG=y 590 680 CONFIG_WATCHDOG_NOWAYOUT=y 591 681 ··· 694 584 # 695 585 # CONFIG_SOFT_WATCHDOG is not set 696 586 # CONFIG_OMAP_WATCHDOG is not set 697 697 - # CONFIG_HW_RANDOM is not set 698 698 - # CONFIG_NVRAM is not set 699 699 - # CONFIG_R3964 is not set 700 700 - # CONFIG_RAW_DRIVER is not set 701 701 - # CONFIG_TCG_TPM is not set 702 702 - # CONFIG_I2C is not set 703 587 704 588 # 705 705 - # SPI support 589 589 + # Sonics Silicon Backplane 706 590 # 707 707 - # CONFIG_SPI is not set 708 708 - # CONFIG_SPI_MASTER is not set 709 709 - # CONFIG_W1 is not set 710 710 - CONFIG_HWMON=y 711 711 - # CONFIG_HWMON_VID is not set 712 712 - # CONFIG_SENSORS_ABITUGURU is not set 713 713 - # CONFIG_SENSORS_ABITUGURU3 is not set 714 714 - # CONFIG_SENSORS_F71805F is not set 715 715 - # CONFIG_SENSORS_IT87 is not set 716 716 - # CONFIG_SENSORS_PC87360 is not set 717 717 - # CONFIG_SENSORS_PC87427 is not set 718 718 - # CONFIG_SENSORS_SMSC47M1 is not set 719 719 - # CONFIG_SENSORS_SMSC47B397 is not set 720 720 - # CONFIG_SENSORS_VT1211 is not set 721 721 - # CONFIG_SENSORS_W83627HF is not set 722 722 - # CONFIG_SENSORS_W83627EHF is not set 723 723 - # CONFIG_HWMON_DEBUG_CHIP is not set 724 724 - CONFIG_MISC_DEVICES=y 725 725 - # CONFIG_EEPROM_93CX6 is not set 591 591 + CONFIG_SSB_POSSIBLE=y 592 592 + # CONFIG_SSB is not set 726 593 727 594 # 728 595 # Multifunction device drivers 729 596 # 730 597 # CONFIG_MFD_SM501 is not set 731 731 - # CONFIG_NEW_LEDS is not set 732 598 733 599 # 734 600 # Multimedia devices ··· 716 630 # 717 631 # Graphics support 718 632 # 719 719 - # CONFIG_BACKLIGHT_LCD_SUPPORT is not set 720 720 - 721 721 - # 722 722 - # Display device support 723 723 - # 724 724 - # CONFIG_DISPLAY_SUPPORT is not set 725 633 # CONFIG_VGASTATE is not set 726 634 CONFIG_VIDEO_OUTPUT_CONTROL=m 727 635 CONFIG_FB=y ··· 724 644 # CONFIG_FB_CFB_FILLRECT is not set 725 645 # CONFIG_FB_CFB_COPYAREA is not set 726 646 # CONFIG_FB_CFB_IMAGEBLIT is not set 647 647 + # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set 727 648 # CONFIG_FB_SYS_FILLRECT is not set 728 649 # CONFIG_FB_SYS_COPYAREA is not set 729 650 # CONFIG_FB_SYS_IMAGEBLIT is not set ··· 740 659 # Frame buffer hardware drivers 741 660 # 742 661 # CONFIG_FB_S1D13XXX is not set 743 743 - # CONFIG_FB_OMAP is not set 744 662 # CONFIG_FB_VIRTUAL is not set 663 663 + # CONFIG_FB_OMAP is not set 664 664 + # CONFIG_BACKLIGHT_LCD_SUPPORT is not set 665 665 + 666 666 + # 667 667 + # Display device support 668 668 + # 669 669 + # CONFIG_DISPLAY_SUPPORT is not set 745 670 746 671 # 747 672 # Console display driver support ··· 792 705 CONFIG_HID_SUPPORT=y 793 706 CONFIG_HID=y 794 707 CONFIG_HID_DEBUG=y 708 708 + # CONFIG_HIDRAW is not set 795 709 CONFIG_USB_SUPPORT=y 796 710 CONFIG_USB_ARCH_HAS_HCD=y 797 711 CONFIG_USB_ARCH_HAS_OHCI=y ··· 808 720 # 809 721 # CONFIG_USB_GADGET is not set 810 722 # CONFIG_MMC is not set 723 723 + # CONFIG_NEW_LEDS is not set 811 724 CONFIG_RTC_LIB=y 812 725 # CONFIG_RTC_CLASS is not set 813 813 - 814 814 - # 815 815 - # DMA Engine support 816 816 - # 817 817 - # CONFIG_DMA_ENGINE is not set 818 818 - 819 819 - # 820 820 - # DMA Clients 821 821 - # 822 822 - 823 823 - # 824 824 - # DMA Devices 825 825 - # 826 726 827 727 # 828 728 # File systems ··· 847 771 # 848 772 CONFIG_FAT_FS=y 849 773 CONFIG_MSDOS_FS=y 850 850 - # CONFIG_VFAT_FS is not set 774 774 + CONFIG_VFAT_FS=y 851 775 CONFIG_FAT_DEFAULT_CODEPAGE=437 776 776 + CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" 852 777 # CONFIG_NTFS_FS is not set 853 778 854 779 # ··· 860 783 CONFIG_SYSFS=y 861 784 # CONFIG_TMPFS is not set 862 785 # CONFIG_HUGETLB_PAGE is not set 863 863 - CONFIG_RAMFS=y 864 786 # CONFIG_CONFIGFS_FS is not set 865 787 866 788 # ··· 878 802 # CONFIG_QNX4FS_FS is not set 879 803 # CONFIG_SYSV_FS is not set 880 804 # CONFIG_UFS_FS is not set 881 881 - 882 882 - # 883 883 - # Network File Systems 884 884 - # 805 805 + CONFIG_NETWORK_FILESYSTEMS=y 885 806 CONFIG_NFS_FS=y 886 807 CONFIG_NFS_V3=y 887 808 # CONFIG_NFS_V3_ACL is not set ··· 905 832 # 906 833 # CONFIG_PARTITION_ADVANCED is not set 907 834 CONFIG_MSDOS_PARTITION=y 908 908 - 909 909 - # 910 910 - # Native Language Support 911 911 - # 912 835 CONFIG_NLS=y 913 836 CONFIG_NLS_DEFAULT="iso8859-1" 914 914 - # CONFIG_NLS_CODEPAGE_437 is not set 837 837 + CONFIG_NLS_CODEPAGE_437=y 915 838 # CONFIG_NLS_CODEPAGE_737 is not set 916 839 # CONFIG_NLS_CODEPAGE_775 is not set 917 840 # CONFIG_NLS_CODEPAGE_850 is not set ··· 931 862 # CONFIG_NLS_CODEPAGE_1250 is not set 932 863 # CONFIG_NLS_CODEPAGE_1251 is not set 933 864 # CONFIG_NLS_ASCII is not set 934 934 - # CONFIG_NLS_ISO8859_1 is not set 865 865 + CONFIG_NLS_ISO8859_1=y 935 866 # CONFIG_NLS_ISO8859_2 is not set 936 867 # CONFIG_NLS_ISO8859_3 is not set 937 868 # CONFIG_NLS_ISO8859_4 is not set ··· 945 876 # CONFIG_NLS_KOI8_R is not set 946 877 # CONFIG_NLS_KOI8_U is not set 947 878 # CONFIG_NLS_UTF8 is not set 948 948 - 949 949 - # 950 950 - # Distributed Lock Manager 951 951 - # 952 879 # CONFIG_DLM is not set 953 953 - 954 954 - # 955 955 - # Profiling support 956 956 - # 880 880 + CONFIG_INSTRUMENTATION=y 957 881 # CONFIG_PROFILING is not set 882 882 + # CONFIG_MARKERS is not set 958 883 959 884 # 960 885 # Kernel hacking 961 886 # 962 887 # CONFIG_PRINTK_TIME is not set 888 888 + CONFIG_ENABLE_WARN_DEPRECATED=y 963 889 CONFIG_ENABLE_MUST_CHECK=y 964 890 # CONFIG_MAGIC_SYSRQ is not set 965 891 # CONFIG_UNUSED_SYMBOLS is not set ··· 963 899 # CONFIG_DEBUG_KERNEL is not set 964 900 CONFIG_DEBUG_BUGVERBOSE=y 965 901 CONFIG_FRAME_POINTER=y 902 902 + # CONFIG_SAMPLES is not set 966 903 # CONFIG_DEBUG_USER is not set 967 904 968 905 # ··· 971 906 # 972 907 # CONFIG_KEYS is not set 973 908 # CONFIG_SECURITY is not set 909 909 + # CONFIG_SECURITY_FILE_CAPABILITIES is not set 974 910 CONFIG_CRYPTO=y 975 911 CONFIG_CRYPTO_ALGAPI=y 976 912 CONFIG_CRYPTO_BLKCIPHER=y ··· 991 925 CONFIG_CRYPTO_CBC=y 992 926 CONFIG_CRYPTO_PCBC=m 993 927 # CONFIG_CRYPTO_LRW is not set 928 928 + # CONFIG_CRYPTO_XTS is not set 994 929 # CONFIG_CRYPTO_CRYPTD is not set 995 930 CONFIG_CRYPTO_DES=y 996 931 # CONFIG_CRYPTO_FCRYPT is not set ··· 1005 938 # CONFIG_CRYPTO_ARC4 is not set 1006 939 # CONFIG_CRYPTO_KHAZAD is not set 1007 940 # CONFIG_CRYPTO_ANUBIS is not set 941 941 + # CONFIG_CRYPTO_SEED is not set 1008 942 # CONFIG_CRYPTO_DEFLATE is not set 1009 943 # CONFIG_CRYPTO_MICHAEL_MIC is not set 1010 944 # CONFIG_CRYPTO_CRC32C is not set 1011 945 # CONFIG_CRYPTO_CAMELLIA is not set 1012 946 # CONFIG_CRYPTO_TEST is not set 947 947 + # CONFIG_CRYPTO_AUTHENC is not set 1013 948 CONFIG_CRYPTO_HW=y 1014 949 1015 950 #

+51 -59

arch/arm/configs/omap_osk_5912_defconfig

reviewed

··· 1 1 # 2 2 # Automatically generated make config: don't edit 3 3 - # Linux kernel version: 2.6.23-rc6 4 4 - # Mon Sep 17 14:15:05 2007 3 3 + # Linux kernel version: 2.6.24-rc5 4 4 + # Mon Dec 17 21:12:45 2007 5 5 # 6 6 CONFIG_ARM=y 7 7 CONFIG_SYS_SUPPORTS_APM_EMULATION=y ··· 40 40 # CONFIG_BSD_PROCESS_ACCT is not set 41 41 # CONFIG_TASKSTATS is not set 42 42 # CONFIG_USER_NS is not set 43 43 + # CONFIG_PID_NS is not set 43 44 # CONFIG_AUDIT is not set 44 45 # CONFIG_IKCONFIG is not set 45 46 CONFIG_LOG_BUF_SHIFT=14 47 47 + # CONFIG_CGROUPS is not set 48 48 + CONFIG_FAIR_GROUP_SCHED=y 49 49 + CONFIG_FAIR_USER_SCHED=y 50 50 + # CONFIG_FAIR_CGROUP_SCHED is not set 46 51 # CONFIG_SYSFS_DEPRECATED is not set 47 52 # CONFIG_RELAY is not set 48 53 CONFIG_BLK_DEV_INITRD=y ··· 68 63 CONFIG_ANON_INODES=y 69 64 CONFIG_EPOLL=y 70 65 CONFIG_SIGNALFD=y 71 71 - CONFIG_TIMERFD=y 72 66 CONFIG_EVENTFD=y 73 67 CONFIG_SHMEM=y 74 68 CONFIG_VM_EVENT_COUNTERS=y ··· 228 224 # 229 225 # CONFIG_PCI_SYSCALL is not set 230 226 # CONFIG_ARCH_SUPPORTS_MSI is not set 231 231 - 232 232 - # 233 233 - # PCCARD (PCMCIA/CardBus) support 234 234 - # 235 227 CONFIG_PCCARD=y 236 228 # CONFIG_PCMCIA_DEBUG is not set 237 229 CONFIG_PCMCIA=y ··· 245 245 CONFIG_TICK_ONESHOT=y 246 246 CONFIG_NO_HZ=y 247 247 CONFIG_HIGH_RES_TIMERS=y 248 248 + CONFIG_GENERIC_CLOCKEVENTS_BUILD=y 248 249 # CONFIG_PREEMPT is not set 249 250 CONFIG_HZ=128 250 251 CONFIG_AEABI=y ··· 258 257 CONFIG_FLATMEM=y 259 258 CONFIG_FLAT_NODE_MEM_MAP=y 260 259 # CONFIG_SPARSEMEM_STATIC is not set 260 260 + # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 261 261 CONFIG_SPLIT_PTLOCK_CPUS=4096 262 262 # CONFIG_RESOURCES_64BIT is not set 263 263 CONFIG_ZONE_DMA_FLAG=1 ··· 348 346 CONFIG_INET_XFRM_MODE_TRANSPORT=y 349 347 CONFIG_INET_XFRM_MODE_TUNNEL=y 350 348 CONFIG_INET_XFRM_MODE_BEET=y 349 349 + # CONFIG_INET_LRO is not set 351 350 CONFIG_INET_DIAG=y 352 351 CONFIG_INET_TCP_DIAG=y 353 352 # CONFIG_TCP_CONG_ADVANCED is not set ··· 374 371 # CONFIG_LAPB is not set 375 372 # CONFIG_ECONET is not set 376 373 # CONFIG_WAN_ROUTER is not set 377 377 - 378 378 - # 379 379 - # QoS and/or fair queueing 380 380 - # 381 374 # CONFIG_NET_SCHED is not set 382 375 383 376 # ··· 402 403 # 403 404 # Generic Driver Options 404 405 # 406 406 + CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 405 407 CONFIG_STANDALONE=y 406 408 CONFIG_PREVENT_FIRMWARE_BUILD=y 407 409 CONFIG_FW_LOADER=y ··· 427 427 # CONFIG_INFTL is not set 428 428 # CONFIG_RFD_FTL is not set 429 429 # CONFIG_SSFDC is not set 430 430 + # CONFIG_MTD_OOPS is not set 430 431 431 432 # 432 433 # RAM/ROM/Flash chip drivers ··· 496 495 CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 497 496 # CONFIG_CDROM_PKTCDVD is not set 498 497 # CONFIG_ATA_OVER_ETH is not set 498 498 + CONFIG_MISC_DEVICES=y 499 499 + # CONFIG_EEPROM_93CX6 is not set 499 500 CONFIG_IDE=m 500 501 CONFIG_BLK_DEV_IDE=m 501 502 ··· 518 515 # IDE chipset support/bugfixes 519 516 # 520 517 # CONFIG_IDE_GENERIC is not set 521 521 - # CONFIG_IDEPCI_PCIBUS_ORDER is not set 518 518 + # CONFIG_BLK_DEV_PLATFORM is not set 522 519 # CONFIG_IDE_ARM is not set 523 520 # CONFIG_BLK_DEV_IDEDMA is not set 521 521 + CONFIG_IDE_ARCH_OBSOLETE_INIT=y 524 522 # CONFIG_BLK_DEV_HD is not set 525 523 526 524 # ··· 540 536 # CONFIG_MACVLAN is not set 541 537 # CONFIG_EQUALIZER is not set 542 538 # CONFIG_TUN is not set 539 539 + # CONFIG_VETH is not set 543 540 # CONFIG_PHYLIB is not set 544 541 CONFIG_NET_ETHERNET=y 545 542 CONFIG_MII=y 546 543 # CONFIG_AX88796 is not set 547 544 CONFIG_SMC91X=y 548 545 # CONFIG_DM9000 is not set 546 546 + # CONFIG_IBM_NEW_EMAC_ZMII is not set 547 547 + # CONFIG_IBM_NEW_EMAC_RGMII is not set 548 548 + # CONFIG_IBM_NEW_EMAC_TAH is not set 549 549 + # CONFIG_IBM_NEW_EMAC_EMAC4 is not set 550 550 + # CONFIG_B44 is not set 549 551 CONFIG_NETDEV_1000=y 550 552 CONFIG_NETDEV_10000=y 551 553 ··· 595 585 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 596 586 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 597 587 # CONFIG_INPUT_JOYDEV is not set 598 598 - # CONFIG_INPUT_TSDEV is not set 599 588 CONFIG_INPUT_EVDEV=y 600 589 # CONFIG_INPUT_EVBUG is not set 601 590 ··· 660 651 CONFIG_LEGACY_PTYS=y 661 652 CONFIG_LEGACY_PTY_COUNT=256 662 653 # CONFIG_IPMI_HANDLER is not set 663 663 - # CONFIG_WATCHDOG is not set 664 654 CONFIG_HW_RANDOM=m 665 655 CONFIG_HW_RANDOM_OMAP=m 666 656 # CONFIG_NVRAM is not set ··· 720 712 # CONFIG_SPI is not set 721 713 # CONFIG_SPI_MASTER is not set 722 714 # CONFIG_W1 is not set 715 715 + # CONFIG_POWER_SUPPLY is not set 723 716 CONFIG_HWMON=y 724 717 # CONFIG_HWMON_VID is not set 725 725 - # CONFIG_SENSORS_ABITUGURU is not set 726 726 - # CONFIG_SENSORS_ABITUGURU3 is not set 727 718 # CONFIG_SENSORS_AD7418 is not set 728 719 # CONFIG_SENSORS_ADM1021 is not set 729 720 # CONFIG_SENSORS_ADM1025 is not set ··· 730 723 # CONFIG_SENSORS_ADM1029 is not set 731 724 # CONFIG_SENSORS_ADM1031 is not set 732 725 # CONFIG_SENSORS_ADM9240 is not set 733 733 - # CONFIG_SENSORS_ASB100 is not set 726 726 + # CONFIG_SENSORS_ADT7470 is not set 734 727 # CONFIG_SENSORS_ATXP1 is not set 735 728 # CONFIG_SENSORS_DS1621 is not set 736 729 # CONFIG_SENSORS_F71805F is not set 737 737 - # CONFIG_SENSORS_FSCHER is not set 738 738 - # CONFIG_SENSORS_FSCPOS is not set 730 730 + # CONFIG_SENSORS_F71882FG is not set 731 731 + # CONFIG_SENSORS_F75375S is not set 739 732 # CONFIG_SENSORS_GL518SM is not set 740 733 # CONFIG_SENSORS_GL520SM is not set 741 734 # CONFIG_SENSORS_IT87 is not set ··· 768 761 # CONFIG_SENSORS_W83627HF is not set 769 762 # CONFIG_SENSORS_W83627EHF is not set 770 763 # CONFIG_HWMON_DEBUG_CHIP is not set 771 771 - CONFIG_MISC_DEVICES=y 772 772 - # CONFIG_EEPROM_93CX6 is not set 764 764 + # CONFIG_WATCHDOG is not set 765 765 + 766 766 + # 767 767 + # Sonics Silicon Backplane 768 768 + # 769 769 + CONFIG_SSB_POSSIBLE=y 770 770 + # CONFIG_SSB is not set 773 771 774 772 # 775 773 # Multifunction device drivers 776 774 # 777 775 # CONFIG_MFD_SM501 is not set 778 778 - # CONFIG_NEW_LEDS is not set 779 776 780 777 # 781 778 # Multimedia devices ··· 791 780 # 792 781 # Graphics support 793 782 # 794 794 - # CONFIG_BACKLIGHT_LCD_SUPPORT is not set 795 795 - 796 796 - # 797 797 - # Display device support 798 798 - # 799 799 - # CONFIG_DISPLAY_SUPPORT is not set 800 783 # CONFIG_VGASTATE is not set 801 784 CONFIG_VIDEO_OUTPUT_CONTROL=m 802 785 CONFIG_FB=y ··· 799 794 # CONFIG_FB_CFB_FILLRECT is not set 800 795 # CONFIG_FB_CFB_COPYAREA is not set 801 796 # CONFIG_FB_CFB_IMAGEBLIT is not set 797 797 + # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set 802 798 # CONFIG_FB_SYS_FILLRECT is not set 803 799 # CONFIG_FB_SYS_COPYAREA is not set 804 800 # CONFIG_FB_SYS_IMAGEBLIT is not set ··· 815 809 # Frame buffer hardware drivers 816 810 # 817 811 # CONFIG_FB_S1D13XXX is not set 818 818 - # CONFIG_FB_OMAP is not set 819 812 # CONFIG_FB_VIRTUAL is not set 813 813 + # CONFIG_FB_OMAP is not set 814 814 + # CONFIG_BACKLIGHT_LCD_SUPPORT is not set 815 815 + 816 816 + # 817 817 + # Display device support 818 818 + # 819 819 + # CONFIG_DISPLAY_SUPPORT is not set 820 820 821 821 # 822 822 # Console display driver support ··· 855 843 CONFIG_HID_SUPPORT=y 856 844 CONFIG_HID=y 857 845 CONFIG_HID_DEBUG=y 846 846 + # CONFIG_HIDRAW is not set 858 847 CONFIG_USB_SUPPORT=y 859 848 CONFIG_USB_ARCH_HAS_HCD=y 860 849 CONFIG_USB_ARCH_HAS_OHCI=y ··· 871 858 # 872 859 # CONFIG_USB_GADGET is not set 873 860 # CONFIG_MMC is not set 861 861 + # CONFIG_NEW_LEDS is not set 874 862 CONFIG_RTC_LIB=y 875 863 # CONFIG_RTC_CLASS is not set 876 876 - 877 877 - # 878 878 - # DMA Engine support 879 879 - # 880 880 - # CONFIG_DMA_ENGINE is not set 881 881 - 882 882 - # 883 883 - # DMA Clients 884 884 - # 885 885 - 886 886 - # 887 887 - # DMA Devices 888 888 - # 889 864 890 865 # 891 866 # File systems ··· 923 922 CONFIG_SYSFS=y 924 923 # CONFIG_TMPFS is not set 925 924 # CONFIG_HUGETLB_PAGE is not set 926 926 - CONFIG_RAMFS=y 927 925 # CONFIG_CONFIGFS_FS is not set 928 926 929 927 # ··· 938 938 CONFIG_JFFS2_FS=y 939 939 CONFIG_JFFS2_FS_DEBUG=0 940 940 CONFIG_JFFS2_FS_WRITEBUFFER=y 941 941 + # CONFIG_JFFS2_FS_WBUF_VERIFY is not set 941 942 # CONFIG_JFFS2_SUMMARY is not set 942 943 # CONFIG_JFFS2_FS_XATTR is not set 943 944 # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set 944 945 CONFIG_JFFS2_ZLIB=y 946 946 + # CONFIG_JFFS2_LZO is not set 945 947 CONFIG_JFFS2_RTIME=y 946 948 # CONFIG_JFFS2_RUBIN is not set 947 949 # CONFIG_CRAMFS is not set ··· 952 950 # CONFIG_QNX4FS_FS is not set 953 951 # CONFIG_SYSV_FS is not set 954 952 # CONFIG_UFS_FS is not set 955 955 - 956 956 - # 957 957 - # Network File Systems 958 958 - # 953 953 + CONFIG_NETWORK_FILESYSTEMS=y 959 954 CONFIG_NFS_FS=y 960 955 CONFIG_NFS_V3=y 961 956 # CONFIG_NFS_V3_ACL is not set ··· 978 979 # 979 980 # CONFIG_PARTITION_ADVANCED is not set 980 981 CONFIG_MSDOS_PARTITION=y 981 981 - 982 982 - # 983 983 - # Native Language Support 984 984 - # 985 982 CONFIG_NLS=m 986 983 CONFIG_NLS_DEFAULT="iso8859-1" 987 984 CONFIG_NLS_CODEPAGE_437=m ··· 1018 1023 # CONFIG_NLS_KOI8_R is not set 1019 1024 # CONFIG_NLS_KOI8_U is not set 1020 1025 # CONFIG_NLS_UTF8 is not set 1021 1021 - 1022 1022 - # 1023 1023 - # Distributed Lock Manager 1024 1024 - # 1025 1026 # CONFIG_DLM is not set 1026 1026 - 1027 1027 - # 1028 1028 - # Profiling support 1029 1029 - # 1027 1027 + CONFIG_INSTRUMENTATION=y 1030 1028 # CONFIG_PROFILING is not set 1029 1029 + # CONFIG_MARKERS is not set 1031 1030 1032 1031 # 1033 1032 # Kernel hacking 1034 1033 # 1035 1034 # CONFIG_PRINTK_TIME is not set 1035 1035 + CONFIG_ENABLE_WARN_DEPRECATED=y 1036 1036 CONFIG_ENABLE_MUST_CHECK=y 1037 1037 # CONFIG_MAGIC_SYSRQ is not set 1038 1038 # CONFIG_UNUSED_SYMBOLS is not set ··· 1036 1046 # CONFIG_DEBUG_KERNEL is not set 1037 1047 CONFIG_DEBUG_BUGVERBOSE=y 1038 1048 CONFIG_FRAME_POINTER=y 1049 1049 + # CONFIG_SAMPLES is not set 1039 1050 # CONFIG_DEBUG_USER is not set 1040 1051 1041 1052 # ··· 1044 1053 # 1045 1054 # CONFIG_KEYS is not set 1046 1055 # CONFIG_SECURITY is not set 1056 1056 + # CONFIG_SECURITY_FILE_CAPABILITIES is not set 1047 1057 # CONFIG_CRYPTO is not set 1048 1058 1049 1059 #

+46 -47

arch/arm/configs/orion_defconfig

reviewed

··· 1 1 # 2 2 # Automatically generated make config: don't edit 3 3 - # Linux kernel version: 2.6.24-rc3 4 4 - # Wed Nov 28 15:13:57 2007 3 3 + # Linux kernel version: 2.6.24 4 4 + # Thu Feb 7 14:10:30 2008 5 5 # 6 6 CONFIG_ARM=y 7 7 CONFIG_SYS_SUPPORTS_APM_EMULATION=y ··· 63 63 CONFIG_PRINTK=y 64 64 CONFIG_BUG=y 65 65 CONFIG_ELF_CORE=y 66 66 + CONFIG_COMPAT_BRK=y 66 67 CONFIG_BASE_FULL=y 67 68 CONFIG_FUTEX=y 68 69 CONFIG_ANON_INODES=y 69 70 CONFIG_EPOLL=y 70 71 CONFIG_SIGNALFD=y 72 72 + CONFIG_TIMERFD=y 71 73 CONFIG_EVENTFD=y 72 74 CONFIG_SHMEM=y 73 75 CONFIG_VM_EVENT_COUNTERS=y 74 76 CONFIG_SLAB=y 75 77 # CONFIG_SLUB is not set 76 78 # CONFIG_SLOB is not set 79 79 + # CONFIG_PROFILING is not set 80 80 + # CONFIG_MARKERS is not set 81 81 + CONFIG_HAVE_OPROFILE=y 82 82 + # CONFIG_KPROBES is not set 83 83 + CONFIG_HAVE_KPROBES=y 84 84 + CONFIG_PROC_PAGE_MONITOR=y 85 85 + CONFIG_SLABINFO=y 77 86 CONFIG_RT_MUTEXES=y 78 87 # CONFIG_TINY_SHMEM is not set 79 88 CONFIG_BASE_SMALL=0 ··· 110 101 CONFIG_DEFAULT_CFQ=y 111 102 # CONFIG_DEFAULT_NOOP is not set 112 103 CONFIG_DEFAULT_IOSCHED="cfq" 104 104 + CONFIG_CLASSIC_RCU=y 105 105 + # CONFIG_PREEMPT_RCU is not set 113 106 114 107 # 115 108 # System Type ··· 150 139 # CONFIG_ARCH_LH7A40X is not set 151 140 # CONFIG_ARCH_DAVINCI is not set 152 141 # CONFIG_ARCH_OMAP is not set 142 142 + # CONFIG_ARCH_MSM7X00A is not set 153 143 154 144 # 155 145 # Orion Implementations ··· 238 226 CONFIG_CMDLINE="" 239 227 # CONFIG_XIP_KERNEL is not set 240 228 # CONFIG_KEXEC is not set 229 229 + # CONFIG_ATAGS_PROC is not set 241 230 242 231 # 243 232 # Floating point emulation ··· 263 250 # Power management options 264 251 # 265 252 # CONFIG_PM is not set 266 266 - CONFIG_SUSPEND_UP_POSSIBLE=y 253 253 + CONFIG_ARCH_SUSPEND_POSSIBLE=y 267 254 268 255 # 269 256 # Networking ··· 280 267 # CONFIG_XFRM_USER is not set 281 268 # CONFIG_XFRM_SUB_POLICY is not set 282 269 # CONFIG_XFRM_MIGRATE is not set 270 270 + # CONFIG_XFRM_STATISTICS is not set 283 271 # CONFIG_NET_KEY is not set 284 272 CONFIG_INET=y 285 273 CONFIG_IP_MULTICAST=y ··· 336 322 # 337 323 CONFIG_NET_PKTGEN=m 338 324 # CONFIG_HAMRADIO is not set 325 325 + # CONFIG_CAN is not set 339 326 # CONFIG_IRDA is not set 340 327 # CONFIG_BT is not set 341 328 # CONFIG_AF_RXRPC is not set ··· 490 475 CONFIG_SCSI_DMA=y 491 476 # CONFIG_SCSI_TGT is not set 492 477 # CONFIG_SCSI_NETLINK is not set 493 493 - CONFIG_SCSI_PROC_FS=y 478 478 + # CONFIG_SCSI_PROC_FS is not set 494 479 495 480 # 496 481 # SCSI support type (disk, tape, CD-ROM) ··· 498 483 CONFIG_BLK_DEV_SD=y 499 484 # CONFIG_CHR_DEV_ST is not set 500 485 # CONFIG_CHR_DEV_OSST is not set 501 501 - CONFIG_BLK_DEV_SR=y 486 486 + CONFIG_BLK_DEV_SR=m 502 487 # CONFIG_BLK_DEV_SR_VENDOR is not set 503 503 - CONFIG_CHR_DEV_SG=y 488 488 + CONFIG_CHR_DEV_SG=m 504 489 # CONFIG_CHR_DEV_SCH is not set 505 490 506 491 # 507 492 # Some SCSI devices (e.g. CD jukebox) support multiple LUNs 508 493 # 509 509 - CONFIG_SCSI_MULTI_LUN=y 494 494 + # CONFIG_SCSI_MULTI_LUN is not set 510 495 # CONFIG_SCSI_CONSTANTS is not set 511 496 # CONFIG_SCSI_LOGGING is not set 512 497 # CONFIG_SCSI_SCAN_ASYNC is not set ··· 543 528 # CONFIG_SCSI_INITIO is not set 544 529 # CONFIG_SCSI_INIA100 is not set 545 530 # CONFIG_SCSI_STEX is not set 546 546 - CONFIG_SCSI_MVSATA=y 547 547 - 548 548 - # 549 549 - # Sata options 550 550 - # 551 551 - # CONFIG_MV_SATA_SUPPORT_ATAPI is not set 552 552 - # CONFIG_MV_SATA_ENABLE_1MB_IOS is not set 553 553 - CONFIG_SATA_NO_DEBUG=y 554 554 - # CONFIG_SATA_DEBUG_ON_ERROR is not set 555 555 - # CONFIG_SATA_FULL_DEBUG is not set 556 531 # CONFIG_SCSI_SYM53C8XX_2 is not set 557 532 # CONFIG_SCSI_IPR is not set 558 533 # CONFIG_SCSI_QLOGIC_1280 is not set ··· 554 549 # CONFIG_SCSI_NSP32 is not set 555 550 # CONFIG_SCSI_DEBUG is not set 556 551 # CONFIG_SCSI_SRP is not set 557 557 - CONFIG_ATA=m 552 552 + CONFIG_ATA=y 558 553 # CONFIG_ATA_NONSTANDARD is not set 559 554 # CONFIG_SATA_AHCI is not set 560 555 # CONFIG_SATA_SVW is not set 561 556 # CONFIG_ATA_PIIX is not set 562 562 - # CONFIG_SATA_MV is not set 557 557 + CONFIG_SATA_MV=y 563 558 # CONFIG_SATA_NV is not set 564 559 # CONFIG_PDC_ADMA is not set 565 560 # CONFIG_SATA_QSTOR is not set ··· 595 590 # CONFIG_PATA_MPIIX is not set 596 591 # CONFIG_PATA_OLDPIIX is not set 597 592 # CONFIG_PATA_NETCELL is not set 593 593 + # CONFIG_PATA_NINJA32 is not set 598 594 # CONFIG_PATA_NS87410 is not set 599 595 # CONFIG_PATA_NS87415 is not set 600 596 # CONFIG_PATA_OPTI is not set ··· 628 622 # CONFIG_EQUALIZER is not set 629 623 # CONFIG_TUN is not set 630 624 # CONFIG_VETH is not set 631 631 - # CONFIG_IP1000 is not set 632 625 # CONFIG_ARCNET is not set 633 626 # CONFIG_PHYLIB is not set 634 627 CONFIG_NET_ETHERNET=y ··· 658 653 # CONFIG_NE2K_PCI is not set 659 654 # CONFIG_8139CP is not set 660 655 # CONFIG_8139TOO is not set 656 656 + # CONFIG_R6040 is not set 661 657 # CONFIG_SIS900 is not set 662 658 # CONFIG_EPIC100 is not set 663 659 # CONFIG_SUNDANCE is not set ··· 672 666 CONFIG_E1000_NAPI=y 673 667 # CONFIG_E1000_DISABLE_PACKET_SPLIT is not set 674 668 # CONFIG_E1000E is not set 669 669 + # CONFIG_E1000E_ENABLED is not set 670 670 + # CONFIG_IP1000 is not set 671 671 + # CONFIG_IGB is not set 675 672 # CONFIG_NS83820 is not set 676 673 # CONFIG_HAMACHI is not set 677 674 # CONFIG_YELLOWFIN is not set ··· 700 691 # CONFIG_NIU is not set 701 692 # CONFIG_MLX4_CORE is not set 702 693 # CONFIG_TEHUTI is not set 694 694 + # CONFIG_BNX2X is not set 703 695 # CONFIG_TR is not set 704 696 705 697 # ··· 723 713 # CONFIG_PPP is not set 724 714 # CONFIG_SLIP is not set 725 715 # CONFIG_NET_FC is not set 726 726 - # CONFIG_SHAPER is not set 727 716 # CONFIG_NETCONSOLE is not set 728 717 # CONFIG_NETPOLL is not set 729 718 # CONFIG_NET_POLL_CONTROLLER is not set ··· 770 761 CONFIG_HW_CONSOLE=y 771 762 # CONFIG_VT_HW_CONSOLE_BINDING is not set 772 763 # CONFIG_SERIAL_NONSTANDARD is not set 764 764 + # CONFIG_NOZOMI is not set 773 765 774 766 # 775 767 # Serial drivers ··· 842 832 # 843 833 # Miscellaneous I2C Chip support 844 834 # 845 845 - # CONFIG_SENSORS_DS1337 is not set 846 846 - # CONFIG_SENSORS_DS1374 is not set 847 835 # CONFIG_DS1682 is not set 848 836 # CONFIG_SENSORS_EEPROM is not set 849 837 # CONFIG_SENSORS_PCF8574 is not set 850 850 - # CONFIG_SENSORS_PCA9539 is not set 838 838 + # CONFIG_PCF8575 is not set 851 839 # CONFIG_SENSORS_PCF8591 is not set 840 840 + # CONFIG_TPS65010 is not set 852 841 # CONFIG_SENSORS_MAX6875 is not set 853 842 # CONFIG_SENSORS_TSL2550 is not set 854 843 # CONFIG_I2C_DEBUG_CORE is not set ··· 976 967 CONFIG_USB_ARCH_HAS_EHCI=y 977 968 CONFIG_USB=y 978 969 # CONFIG_USB_DEBUG is not set 970 970 + # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set 979 971 980 972 # 981 973 # Miscellaneous USB options ··· 990 980 # USB Host Controller Drivers 991 981 # 992 982 CONFIG_USB_EHCI_HCD=y 993 993 - CONFIG_USB_EHCI_SPLIT_ISO=y 994 983 CONFIG_USB_EHCI_ROOT_HUB_TT=y 995 984 CONFIG_USB_EHCI_TT_NEWSCHED=y 996 985 # CONFIG_USB_ISP116X_HCD is not set 997 997 - CONFIG_USB_OHCI_HCD=y 998 998 - # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set 999 999 - # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set 1000 1000 - CONFIG_USB_OHCI_LITTLE_ENDIAN=y 1001 1001 - CONFIG_USB_UHCI_HCD=y 1002 1002 - CONFIG_USB_SL811_HCD=y 986 986 + # CONFIG_USB_OHCI_HCD is not set 987 987 + # CONFIG_USB_UHCI_HCD is not set 988 988 + # CONFIG_USB_SL811_HCD is not set 1003 989 # CONFIG_USB_R8A66597_HCD is not set 1004 990 1005 991 # ··· 1035 1029 # 1036 1030 # USB port drivers 1037 1031 # 1038 1038 - 1039 1039 - # 1040 1040 - # USB Serial Converter support 1041 1041 - # 1042 1032 # CONFIG_USB_SERIAL is not set 1043 1033 1044 1034 # ··· 1060 1058 # CONFIG_USB_TRANCEVIBRATOR is not set 1061 1059 # CONFIG_USB_IOWARRIOR is not set 1062 1060 # CONFIG_USB_TEST is not set 1063 1063 - 1064 1064 - # 1065 1065 - # USB DSL modem support 1066 1066 - # 1067 1067 - 1068 1068 - # 1069 1069 - # USB Gadget Support 1070 1070 - # 1071 1061 # CONFIG_USB_GADGET is not set 1072 1062 # CONFIG_MMC is not set 1073 1063 CONFIG_NEW_LEDS=y ··· 1114 1120 # Platform RTC drivers 1115 1121 # 1116 1122 # CONFIG_RTC_DRV_CMOS is not set 1123 1123 + # CONFIG_RTC_DRV_DS1511 is not set 1117 1124 # CONFIG_RTC_DRV_DS1553 is not set 1118 1118 - # CONFIG_RTC_DRV_STK17TA8 is not set 1119 1125 # CONFIG_RTC_DRV_DS1742 is not set 1126 1126 + # CONFIG_RTC_DRV_STK17TA8 is not set 1120 1127 # CONFIG_RTC_DRV_M48T86 is not set 1121 1128 # CONFIG_RTC_DRV_M48T59 is not set 1122 1129 # CONFIG_RTC_DRV_V3020 is not set ··· 1293 1298 # CONFIG_NLS_KOI8_U is not set 1294 1299 # CONFIG_NLS_UTF8 is not set 1295 1300 # CONFIG_DLM is not set 1296 1296 - CONFIG_INSTRUMENTATION=y 1297 1297 - # CONFIG_PROFILING is not set 1298 1298 - # CONFIG_MARKERS is not set 1299 1301 1300 1302 # 1301 1303 # Kernel hacking ··· 1319 1327 CONFIG_CRYPTO=y 1320 1328 CONFIG_CRYPTO_ALGAPI=m 1321 1329 CONFIG_CRYPTO_BLKCIPHER=m 1330 1330 + # CONFIG_CRYPTO_SEQIV is not set 1322 1331 CONFIG_CRYPTO_MANAGER=m 1323 1332 # CONFIG_CRYPTO_HMAC is not set 1324 1333 # CONFIG_CRYPTO_XCBC is not set ··· 1337 1344 CONFIG_CRYPTO_PCBC=m 1338 1345 # CONFIG_CRYPTO_LRW is not set 1339 1346 # CONFIG_CRYPTO_XTS is not set 1347 1347 + # CONFIG_CRYPTO_CTR is not set 1348 1348 + # CONFIG_CRYPTO_GCM is not set 1349 1349 + # CONFIG_CRYPTO_CCM is not set 1340 1350 # CONFIG_CRYPTO_CRYPTD is not set 1341 1351 # CONFIG_CRYPTO_DES is not set 1342 1352 # CONFIG_CRYPTO_FCRYPT is not set ··· 1354 1358 # CONFIG_CRYPTO_KHAZAD is not set 1355 1359 # CONFIG_CRYPTO_ANUBIS is not set 1356 1360 # CONFIG_CRYPTO_SEED is not set 1361 1361 + # CONFIG_CRYPTO_SALSA20 is not set 1357 1362 # CONFIG_CRYPTO_DEFLATE is not set 1358 1363 # CONFIG_CRYPTO_MICHAEL_MIC is not set 1359 1364 # CONFIG_CRYPTO_CRC32C is not set 1360 1365 # CONFIG_CRYPTO_CAMELLIA is not set 1361 1366 # CONFIG_CRYPTO_TEST is not set 1362 1367 # CONFIG_CRYPTO_AUTHENC is not set 1368 1368 + # CONFIG_CRYPTO_LZO is not set 1363 1369 CONFIG_CRYPTO_HW=y 1370 1370 + # CONFIG_CRYPTO_DEV_HIFN_795X is not set 1364 1371 1365 1372 # 1366 1373 # Library routines

+1 -1

arch/arm/kernel/setup.c

reviewed

··· 1001 1001 { 1002 1002 } 1003 1003 1004 1004 - struct seq_operations cpuinfo_op = { 1004 1004 + const struct seq_operations cpuinfo_op = { 1005 1005 .start = c_start, 1006 1006 .next = c_next, 1007 1007 .stop = c_stop,

+1 -1

arch/arm/mach-at91/clock.c

reviewed

··· 343 343 EXPORT_SYMBOL(clk_set_parent); 344 344 345 345 /* establish PCK0..PCK3 parentage and rate */ 346 346 - static void init_programmable_clock(struct clk *clk) 346 346 + static void __init init_programmable_clock(struct clk *clk) 347 347 { 348 348 struct clk *parent; 349 349 u32 pckr;

+2 -2

arch/arm/mach-davinci/clock.c

reviewed

··· 290 290 return 0; 291 291 } 292 292 293 293 - static struct seq_operations davinci_ck_op = { 293 293 + static const struct seq_operations davinci_ck_op = { 294 294 .start = davinci_ck_start, 295 295 .next = davinci_ck_next, 296 296 .stop = davinci_ck_stop, ··· 302 302 return seq_open(file, &davinci_ck_op); 303 303 } 304 304 305 305 - static struct file_operations proc_davinci_ck_operations = { 305 305 + static const struct file_operations proc_davinci_ck_operations = { 306 306 .open = davinci_ck_open, 307 307 .read = seq_read, 308 308 .llseek = seq_lseek,

+3 -3

arch/arm/mach-omap1/Makefile

reviewed

··· 13 13 led-y := leds.o 14 14 15 15 # Specific board support 16 16 - obj-$(CONFIG_MACH_OMAP_H2) += board-h2.o 16 16 + obj-$(CONFIG_MACH_OMAP_H2) += board-h2.o board-h2-mmc.o 17 17 obj-$(CONFIG_MACH_OMAP_INNOVATOR) += board-innovator.o 18 18 obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o 19 19 obj-$(CONFIG_MACH_OMAP_PERSEUS2) += board-perseus2.o 20 20 obj-$(CONFIG_MACH_OMAP_FSAMPLE) += board-fsample.o 21 21 obj-$(CONFIG_MACH_OMAP_OSK) += board-osk.o 22 22 - obj-$(CONFIG_MACH_OMAP_H3) += board-h3.o 22 22 + obj-$(CONFIG_MACH_OMAP_H3) += board-h3.o board-h3-mmc.o 23 23 obj-$(CONFIG_MACH_VOICEBLUE) += board-voiceblue.o 24 24 obj-$(CONFIG_MACH_OMAP_PALMTE) += board-palmte.o 25 25 obj-$(CONFIG_MACH_OMAP_PALMZ71) += board-palmz71.o 26 26 obj-$(CONFIG_MACH_OMAP_PALMTT) += board-palmtt.o 27 27 obj-$(CONFIG_MACH_NOKIA770) += board-nokia770.o 28 28 obj-$(CONFIG_MACH_AMS_DELTA) += board-ams-delta.o 29 29 - obj-$(CONFIG_MACH_SX1) += board-sx1.o 29 29 + obj-$(CONFIG_MACH_SX1) += board-sx1.o board-sx1-mmc.o 30 30 31 31 ifeq ($(CONFIG_ARCH_OMAP15XX),y) 32 32 # Innovator-1510 FPGA

+4 -3

arch/arm/mach-omap1/board-ams-delta.c

reviewed

··· 135 135 } 136 136 137 137 static struct map_desc ams_delta_io_desc[] __initdata = { 138 138 - // AMS_DELTA_LATCH1 138 138 + /* AMS_DELTA_LATCH1 */ 139 139 { 140 140 .virtual = AMS_DELTA_LATCH1_VIRT, 141 141 .pfn = __phys_to_pfn(AMS_DELTA_LATCH1_PHYS), 142 142 .length = 0x01000000, 143 143 .type = MT_DEVICE 144 144 }, 145 145 - // AMS_DELTA_LATCH2 145 145 + /* AMS_DELTA_LATCH2 */ 146 146 { 147 147 .virtual = AMS_DELTA_LATCH2_VIRT, 148 148 .pfn = __phys_to_pfn(AMS_DELTA_LATCH2_PHYS), 149 149 .length = 0x01000000, 150 150 .type = MT_DEVICE 151 151 }, 152 152 - // AMS_DELTA_MODEM 152 152 + /* AMS_DELTA_MODEM */ 153 153 { 154 154 .virtual = AMS_DELTA_MODEM_VIRT, 155 155 .pfn = __phys_to_pfn(AMS_DELTA_MODEM_PHYS), ··· 227 227 omap_board_config = ams_delta_config; 228 228 omap_board_config_size = ARRAY_SIZE(ams_delta_config); 229 229 omap_serial_init(); 230 230 + omap_register_i2c_bus(1, 100, NULL, 0); 230 231 231 232 /* Clear latch2 (NAND, LCD, modem enable) */ 232 233 ams_delta_latch2_write(~0, 0);

+4 -2

arch/arm/mach-omap1/board-fsample.c

reviewed

··· 30 30 #include <asm/arch/gpio.h> 31 31 #include <asm/arch/mux.h> 32 32 #include <asm/arch/fpga.h> 33 33 + #include <asm/arch/nand.h> 33 34 #include <asm/arch/keypad.h> 34 35 #include <asm/arch/common.h> 35 36 #include <asm/arch/board.h> ··· 135 134 .resource = &nor_resource, 136 135 }; 137 136 138 138 - static struct nand_platform_data nand_data = { 137 137 + static struct omap_nand_platform_data nand_data = { 139 138 .options = NAND_SAMSUNG_LP_OPTIONS, 140 139 }; 141 140 ··· 203 202 204 203 #define P2_NAND_RB_GPIO_PIN 62 205 204 206 206 - static int nand_dev_ready(struct nand_platform_data *data) 205 205 + static int nand_dev_ready(struct omap_nand_platform_data *data) 207 206 { 208 207 return omap_get_gpio_datain(P2_NAND_RB_GPIO_PIN); 209 208 } ··· 234 233 omap_board_config = fsample_config; 235 234 omap_board_config_size = ARRAY_SIZE(fsample_config); 236 235 omap_serial_init(); 236 236 + omap_register_i2c_bus(1, 100, NULL, 0); 237 237 } 238 238 239 239 static void __init fsample_init_smc91x(void)

+3 -21

arch/arm/mach-omap1/board-generic.c

reviewed

··· 55 55 .hmc_mode = 16, 56 56 .pins[0] = 6, 57 57 }; 58 58 - 59 59 - static struct omap_mmc_config generic_mmc_config __initdata = { 60 60 - .mmc [0] = { 61 61 - .enabled = 0, 62 62 - .wire4 = 0, 63 63 - .wp_pin = -1, 64 64 - .power_pin = -1, 65 65 - .switch_pin = -1, 66 66 - }, 67 67 - .mmc [1] = { 68 68 - .enabled = 0, 69 69 - .wire4 = 0, 70 70 - .wp_pin = -1, 71 71 - .power_pin = -1, 72 72 - .switch_pin = -1, 73 73 - }, 74 74 - }; 75 75 - 76 58 #endif 77 59 78 60 static struct omap_uart_config generic_uart_config __initdata = { 79 61 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), 80 62 }; 81 63 82 82 - static struct omap_board_config_kernel generic_config[] = { 83 83 - { OMAP_TAG_USB, NULL }, 84 84 - { OMAP_TAG_MMC, &generic_mmc_config }, 64 64 + static struct omap_board_config_kernel generic_config[] __initdata = { 65 65 + { OMAP_TAG_USB, NULL }, 85 66 { OMAP_TAG_UART, &generic_uart_config }, 86 67 }; 87 68 ··· 82 101 omap_board_config = generic_config; 83 102 omap_board_config_size = ARRAY_SIZE(generic_config); 84 103 omap_serial_init(); 104 104 + omap_register_i2c_bus(1, 100, NULL, 0); 85 105 } 86 106 87 107 static void __init omap_generic_map_io(void)

+110

arch/arm/mach-omap1/board-h2-mmc.c

reviewed

··· 1 1 + /* 2 2 + * linux/arch/arm/mach-omap1/board-h2-mmc.c 3 3 + * 4 4 + * Copyright (C) 2007 Instituto Nokia de Tecnologia - INdT 5 5 + * Author: Felipe Balbi <felipe.lima@indt.org.br> 6 6 + * 7 7 + * This code is based on linux/arch/arm/mach-omap2/board-n800-mmc.c, which is: 8 8 + * Copyright (C) 2006 Nokia Corporation 9 9 + * 10 10 + * This program is free software; you can redistribute it and/or modify 11 11 + * it under the terms of the GNU General Public License version 2 as 12 12 + * published by the Free Software Foundation. 13 13 + */ 14 14 + 15 15 + #include <asm/arch/mmc.h> 16 16 + #include <asm/arch/gpio.h> 17 17 + 18 18 + #ifdef CONFIG_MMC_OMAP 19 19 + static int slot_cover_open; 20 20 + static struct device *mmc_device; 21 21 + 22 22 + static int h2_mmc_set_power(struct device *dev, int slot, int power_on, 23 23 + int vdd) 24 24 + { 25 25 + #ifdef CONFIG_MMC_DEBUG 26 26 + dev_dbg(dev, "Set slot %d power: %s (vdd %d)\n", slot + 1, 27 27 + power_on ? "on" : "off", vdd); 28 28 + #endif 29 29 + if (slot != 0) { 30 30 + dev_err(dev, "No such slot %d\n", slot + 1); 31 31 + return -ENODEV; 32 32 + } 33 33 + 34 34 + return 0; 35 35 + } 36 36 + 37 37 + static int h2_mmc_set_bus_mode(struct device *dev, int slot, int bus_mode) 38 38 + { 39 39 + #ifdef CONFIG_MMC_DEBUG 40 40 + dev_dbg(dev, "Set slot %d bus_mode %s\n", slot + 1, 41 41 + bus_mode == MMC_BUSMODE_OPENDRAIN ? "open-drain" : "push-pull"); 42 42 + #endif 43 43 + if (slot != 0) { 44 44 + dev_err(dev, "No such slot %d\n", slot + 1); 45 45 + return -ENODEV; 46 46 + } 47 47 + 48 48 + return 0; 49 49 + } 50 50 + 51 51 + static int h2_mmc_get_cover_state(struct device *dev, int slot) 52 52 + { 53 53 + BUG_ON(slot != 0); 54 54 + 55 55 + return slot_cover_open; 56 56 + } 57 57 + 58 58 + void h2_mmc_slot_cover_handler(void *arg, int state) 59 59 + { 60 60 + if (mmc_device == NULL) 61 61 + return; 62 62 + 63 63 + slot_cover_open = state; 64 64 + omap_mmc_notify_cover_event(mmc_device, 0, state); 65 65 + } 66 66 + 67 67 + static int h2_mmc_late_init(struct device *dev) 68 68 + { 69 69 + int ret = 0; 70 70 + 71 71 + mmc_device = dev; 72 72 + 73 73 + return ret; 74 74 + } 75 75 + 76 76 + static void h2_mmc_cleanup(struct device *dev) 77 77 + { 78 78 + } 79 79 + 80 80 + static struct omap_mmc_platform_data h2_mmc_data = { 81 81 + .nr_slots = 1, 82 82 + .switch_slot = NULL, 83 83 + .init = h2_mmc_late_init, 84 84 + .cleanup = h2_mmc_cleanup, 85 85 + .slots[0] = { 86 86 + .set_power = h2_mmc_set_power, 87 87 + .set_bus_mode = h2_mmc_set_bus_mode, 88 88 + .get_ro = NULL, 89 89 + .get_cover_state = h2_mmc_get_cover_state, 90 90 + .ocr_mask = MMC_VDD_28_29 | MMC_VDD_30_31 | 91 91 + MMC_VDD_32_33 | MMC_VDD_33_34, 92 92 + .name = "mmcblk", 93 93 + }, 94 94 + }; 95 95 + 96 96 + void __init h2_mmc_init(void) 97 97 + { 98 98 + omap_set_mmc_info(1, &h2_mmc_data); 99 99 + } 100 100 + 101 101 + #else 102 102 + 103 103 + void __init h2_mmc_init(void) 104 104 + { 105 105 + } 106 106 + 107 107 + void h2_mmc_slot_cover_handler(void *arg, int state) 108 108 + { 109 109 + } 110 110 + #endif

+33 -70

arch/arm/mach-omap1/board-h2.c

reviewed

··· 37 37 #include <asm/mach/flash.h> 38 38 #include <asm/mach/map.h> 39 39 40 40 + #include <asm/arch/gpio-switch.h> 40 41 #include <asm/arch/mux.h> 41 42 #include <asm/arch/tc.h> 43 43 + #include <asm/arch/nand.h> 42 44 #include <asm/arch/irda.h> 43 45 #include <asm/arch/usb.h> 44 46 #include <asm/arch/keypad.h> 45 47 #include <asm/arch/common.h> 46 48 #include <asm/arch/mcbsp.h> 47 49 #include <asm/arch/omap-alsa.h> 48 48 - 49 49 - extern int omap_gpio_init(void); 50 50 51 51 static int h2_keymap[] = { 52 52 KEY(0, 0, KEY_LEFT), ··· 140 140 .resource = &h2_nor_resource, 141 141 }; 142 142 143 143 - #if 0 /* REVISIT: Enable when nand_platform_data is applied */ 144 144 - 145 143 static struct mtd_partition h2_nand_partitions[] = { 146 144 #if 0 147 145 /* REVISIT: enable these partitions if you make NAND BOOT ··· 177 179 }; 178 180 179 181 /* dip switches control NAND chip access: 8 bit, 16 bit, or neither */ 180 180 - static struct nand_platform_data h2_nand_data = { 182 182 + static struct omap_nand_platform_data h2_nand_data = { 181 183 .options = NAND_SAMSUNG_LP_OPTIONS, 182 184 .parts = h2_nand_partitions, 183 185 .nr_parts = ARRAY_SIZE(h2_nand_partitions), ··· 196 198 .num_resources = 1, 197 199 .resource = &h2_nand_resource, 198 200 }; 199 199 - #endif 200 201 201 202 static struct resource h2_smc91x_resources[] = { 202 203 [0] = { ··· 308 311 .srgr2 = GSYNC | CLKSP | FSGM | FPER(31), 309 312 310 313 .pcr0 = CLKXM | CLKRM | FSXP | FSRP | CLKXP | CLKRP, 311 311 - //.pcr0 = CLKXP | CLKRP, /* mcbsp: slave */ 314 314 + /*.pcr0 = CLKXP | CLKRP,*/ /* mcbsp: slave */ 312 315 }; 313 316 314 317 static struct omap_alsa_codec_config alsa_config = { 315 318 .name = "H2 TSC2101", 316 319 .mcbsp_regs_alsa = &mcbsp_regs, 317 317 - .codec_configure_dev = NULL, // tsc2101_configure, 318 318 - .codec_set_samplerate = NULL, // tsc2101_set_samplerate, 319 319 - .codec_clock_setup = NULL, // tsc2101_clock_setup, 320 320 - .codec_clock_on = NULL, // tsc2101_clock_on, 321 321 - .codec_clock_off = NULL, // tsc2101_clock_off, 322 322 - .get_default_samplerate = NULL, // tsc2101_get_default_samplerate, 320 320 + .codec_configure_dev = NULL, /* tsc2101_configure, */ 321 321 + .codec_set_samplerate = NULL, /* tsc2101_set_samplerate, */ 322 322 + .codec_clock_setup = NULL, /* tsc2101_clock_setup, */ 323 323 + .codec_clock_on = NULL, /* tsc2101_clock_on, */ 324 324 + .codec_clock_off = NULL, /* tsc2101_clock_off, */ 325 325 + .get_default_samplerate = NULL, /* tsc2101_get_default_samplerate, */ 323 326 }; 324 327 325 328 static struct platform_device h2_mcbsp1_device = { ··· 332 335 333 336 static struct platform_device *h2_devices[] __initdata = { 334 337 &h2_nor_device, 335 335 - //&h2_nand_device, 338 338 + &h2_nand_device, 336 339 &h2_smc91x_device, 337 340 &h2_irda_device, 338 341 &h2_kp_device, 339 342 &h2_lcd_device, 340 343 &h2_mcbsp1_device, 341 344 }; 342 342 - 343 343 - #ifdef CONFIG_I2C_BOARDINFO 344 344 - static struct i2c_board_info __initdata h2_i2c_board_info[] = { 345 345 - { 346 346 - I2C_BOARD_INFO("tps65010", 0x48), 347 347 - .type = "tps65010", 348 348 - .irq = OMAP_GPIO_IRQ(58), 349 349 - }, 350 350 - /* TODO when driver support is ready: 351 351 - * - isp1301 OTG transceiver 352 352 - * - optional ov9640 camera sensor at 0x30 353 353 - * - pcf9754 for aGPS control 354 354 - * - ... etc 355 355 - */ 356 356 - }; 357 357 - #endif 358 345 359 346 static void __init h2_init_smc91x(void) 360 347 { ··· 347 366 return; 348 367 } 349 368 } 369 369 + 370 370 + static struct i2c_board_info __initdata h2_i2c_board_info[] = { 371 371 + { 372 372 + I2C_BOARD_INFO("isp1301_omap", 0x2d), 373 373 + .type = "isp1301_omap", 374 374 + .irq = OMAP_GPIO_IRQ(2), 375 375 + }, 376 376 + }; 350 377 351 378 static void __init h2_init_irq(void) 352 379 { ··· 369 380 .otg = 2, 370 381 371 382 #ifdef CONFIG_USB_GADGET_OMAP 372 372 - .hmc_mode = 19, // 0:host(off) 1:dev|otg 2:disabled 373 373 - // .hmc_mode = 21, // 0:host(off) 1:dev(loopback) 2:host(loopback) 383 383 + .hmc_mode = 19, /* 0:host(off) 1:dev|otg 2:disabled */ 384 384 + /* .hmc_mode = 21,*/ /* 0:host(off) 1:dev(loopback) 2:host(loopback) */ 374 385 #elif defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 375 386 /* needs OTG cable, or NONSTANDARD (B-to-MiniB) */ 376 376 - .hmc_mode = 20, // 1:dev|otg(off) 1:host 2:disabled 387 387 + .hmc_mode = 20, /* 1:dev|otg(off) 1:host 2:disabled */ 377 388 #endif 378 389 379 390 .pins[1] = 3, 380 391 }; 381 392 382 393 static struct omap_mmc_config h2_mmc_config __initdata = { 383 383 - .mmc [0] = { 384 384 - .enabled = 1, 394 394 + .mmc[0] = { 395 395 + .enabled = 1, 385 396 .wire4 = 1, 386 386 - .wp_pin = OMAP_MPUIO(3), 387 387 - .power_pin = -1, /* tps65010 gpio3 */ 388 388 - .switch_pin = OMAP_MPUIO(1), 389 397 }, 390 398 }; 399 399 + 400 400 + extern struct omap_mmc_platform_data h2_mmc_data; 391 401 392 402 static struct omap_uart_config h2_uart_config __initdata = { 393 403 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), ··· 397 409 }; 398 410 399 411 static struct omap_board_config_kernel h2_config[] __initdata = { 400 400 - { OMAP_TAG_USB, &h2_usb_config }, 401 401 - { OMAP_TAG_MMC, &h2_mmc_config }, 412 412 + { OMAP_TAG_USB, &h2_usb_config }, 413 413 + { OMAP_TAG_MMC, &h2_mmc_config }, 402 414 { OMAP_TAG_UART, &h2_uart_config }, 403 415 { OMAP_TAG_LCD, &h2_lcd_config }, 404 416 }; 405 417 406 418 #define H2_NAND_RB_GPIO_PIN 62 407 419 408 408 - static int h2_nand_dev_ready(struct nand_platform_data *data) 420 420 + static int h2_nand_dev_ready(struct omap_nand_platform_data *data) 409 421 { 410 422 return omap_get_gpio_datain(H2_NAND_RB_GPIO_PIN); 411 423 } ··· 424 436 h2_nor_resource.end = h2_nor_resource.start = omap_cs3_phys(); 425 437 h2_nor_resource.end += SZ_32M - 1; 426 438 427 427 - #if 0 /* REVISIT: Enable when nand_platform_data is applied */ 428 439 h2_nand_resource.end = h2_nand_resource.start = OMAP_CS2B_PHYS; 429 440 h2_nand_resource.end += SZ_4K - 1; 430 441 if (!(omap_request_gpio(H2_NAND_RB_GPIO_PIN))) 431 442 h2_nand_data.dev_ready = h2_nand_dev_ready; 432 432 - #endif 433 443 434 444 omap_cfg_reg(L3_1610_FLASH_CS2B_OE); 435 445 omap_cfg_reg(M8_1610_FLASH_CS2B_WE); 436 446 437 447 /* MMC: card detect and WP */ 438 438 - // omap_cfg_reg(U19_ARMIO1); /* CD */ 448 448 + /* omap_cfg_reg(U19_ARMIO1); */ /* CD */ 439 449 omap_cfg_reg(BALLOUT_V8_ARMIO3); /* WP */ 440 450 441 451 /* Irda */ ··· 449 463 omap_board_config = h2_config; 450 464 omap_board_config_size = ARRAY_SIZE(h2_config); 451 465 omap_serial_init(); 452 452 - 453 453 - /* irq for tps65010 chip */ 454 454 - omap_cfg_reg(W4_GPIO58); 455 455 - if (gpio_request(58, "tps65010") == 0) 456 456 - gpio_direction_input(58); 457 457 - 458 458 - #ifdef CONFIG_I2C_BOARDINFO 459 459 - i2c_register_board_info(1, h2_i2c_board_info, 460 460 - ARRAY_SIZE(h2_i2c_board_info)); 461 461 - #endif 466 466 + omap_register_i2c_bus(1, 100, h2_i2c_board_info, 467 467 + ARRAY_SIZE(h2_i2c_board_info)); 468 468 + h2_mmc_init(); 462 469 } 463 470 464 471 static void __init h2_map_io(void) 465 472 { 466 473 omap1_map_common_io(); 467 474 } 468 468 - 469 469 - #ifdef CONFIG_TPS65010 470 470 - static int __init h2_tps_init(void) 471 471 - { 472 472 - if (!machine_is_omap_h2()) 473 473 - return 0; 474 474 - 475 475 - /* gpio3 for SD, gpio4 for VDD_DSP */ 476 476 - /* FIXME send power to DSP iff it's configured */ 477 477 - 478 478 - /* Enable LOW_PWR */ 479 479 - tps65010_set_low_pwr(ON); 480 480 - return 0; 481 481 - } 482 482 - fs_initcall(h2_tps_init); 483 483 - #endif 484 475 485 476 MACHINE_START(OMAP_H2, "TI-H2") 486 477 /* Maintainer: Imre Deak <imre.deak@nokia.com> */

+114

arch/arm/mach-omap1/board-h3-mmc.c

reviewed

··· 1 1 + /* 2 2 + * linux/arch/arm/mach-omap1/board-h3-mmc.c 3 3 + * 4 4 + * Copyright (C) 2007 Instituto Nokia de Tecnologia - INdT 5 5 + * Author: Felipe Balbi <felipe.lima@indt.org.br> 6 6 + * 7 7 + * This code is based on linux/arch/arm/mach-omap2/board-n800-mmc.c, which is: 8 8 + * Copyright (C) 2006 Nokia Corporation 9 9 + * 10 10 + * This program is free software; you can redistribute it and/or modify 11 11 + * it under the terms of the GNU General Public License version 2 as 12 12 + * published by the Free Software Foundation. 13 13 + */ 14 14 + 15 15 + #include <asm/arch/mmc.h> 16 16 + #include <asm/arch/gpio.h> 17 17 + 18 18 + #ifdef CONFIG_MMC_OMAP 19 19 + static int slot_cover_open; 20 20 + static struct device *mmc_device; 21 21 + 22 22 + static int h3_mmc_set_power(struct device *dev, int slot, int power_on, 23 23 + int vdd) 24 24 + { 25 25 + #ifdef CONFIG_MMC_DEBUG 26 26 + dev_dbg(dev, "Set slot %d power: %s (vdd %d)\n", slot + 1, 27 27 + power_on ? "on" : "off", vdd); 28 28 + #endif 29 29 + if (slot != 0) { 30 30 + dev_err(dev, "No such slot %d\n", slot + 1); 31 31 + return -ENODEV; 32 32 + } 33 33 + 34 34 + return 0; 35 35 + } 36 36 + 37 37 + static int h3_mmc_set_bus_mode(struct device *dev, int slot, int bus_mode) 38 38 + { 39 39 + int ret = 0; 40 40 + 41 41 + #ifdef CONFIG_MMC_DEBUG 42 42 + dev_dbg(dev, "Set slot %d bus_mode %s\n", slot + 1, 43 43 + bus_mode == MMC_BUSMODE_OPENDRAIN ? "open-drain" : "push-pull"); 44 44 + #endif 45 45 + if (slot != 0) { 46 46 + dev_err(dev, "No such slot %d\n", slot + 1); 47 47 + return -ENODEV; 48 48 + } 49 49 + 50 50 + /* Treated on upper level */ 51 51 + 52 52 + return bus_mode; 53 53 + } 54 54 + 55 55 + static int h3_mmc_get_cover_state(struct device *dev, int slot) 56 56 + { 57 57 + BUG_ON(slot != 0); 58 58 + 59 59 + return slot_cover_open; 60 60 + } 61 61 + 62 62 + void h3_mmc_slot_cover_handler(void *arg, int state) 63 63 + { 64 64 + if (mmc_device == NULL) 65 65 + return; 66 66 + 67 67 + slot_cover_open = state; 68 68 + omap_mmc_notify_cover_event(mmc_device, 0, state); 69 69 + } 70 70 + 71 71 + static int h3_mmc_late_init(struct device *dev) 72 72 + { 73 73 + int ret = 0; 74 74 + 75 75 + mmc_device = dev; 76 76 + 77 77 + return ret; 78 78 + } 79 79 + 80 80 + static void h3_mmc_cleanup(struct device *dev) 81 81 + { 82 82 + } 83 83 + 84 84 + static struct omap_mmc_platform_data h3_mmc_data = { 85 85 + .nr_slots = 1, 86 86 + .switch_slot = NULL, 87 87 + .init = h3_mmc_late_init, 88 88 + .cleanup = h3_mmc_cleanup, 89 89 + .slots[0] = { 90 90 + .set_power = h3_mmc_set_power, 91 91 + .set_bus_mode = h3_mmc_set_bus_mode, 92 92 + .get_ro = NULL, 93 93 + .get_cover_state = h3_mmc_get_cover_state, 94 94 + .ocr_mask = MMC_VDD_28_29 | MMC_VDD_30_31 | 95 95 + MMC_VDD_32_33 | MMC_VDD_33_34, 96 96 + .name = "mmcblk", 97 97 + }, 98 98 + }; 99 99 + 100 100 + void __init h3_mmc_init(void) 101 101 + { 102 102 + omap_set_mmc_info(1, &h3_mmc_data); 103 103 + } 104 104 + 105 105 + #else 106 106 + 107 107 + void __init h3_mmc_init(void) 108 108 + { 109 109 + } 110 110 + 111 111 + void h3_mmc_slot_cover_handler(void *arg, int state) 112 112 + { 113 113 + } 114 114 + #endif

+29 -46

arch/arm/mach-omap1/board-h3.c

reviewed

··· 42 42 #include <asm/arch/irqs.h> 43 43 #include <asm/arch/mux.h> 44 44 #include <asm/arch/tc.h> 45 45 + #include <asm/arch/nand.h> 45 46 #include <asm/arch/irda.h> 46 47 #include <asm/arch/usb.h> 47 48 #include <asm/arch/keypad.h> ··· 50 49 #include <asm/arch/common.h> 51 50 #include <asm/arch/mcbsp.h> 52 51 #include <asm/arch/omap-alsa.h> 53 53 - 54 54 - extern int omap_gpio_init(void); 55 52 56 53 static int h3_keymap[] = { 57 54 KEY(0, 0, KEY_LEFT), ··· 178 179 }; 179 180 180 181 /* dip switches control NAND chip access: 8 bit, 16 bit, or neither */ 181 181 - static struct nand_platform_data nand_data = { 182 182 + static struct omap_nand_platform_data nand_data = { 182 183 .options = NAND_SAMSUNG_LP_OPTIONS, 183 184 .parts = nand_partitions, 184 185 .nr_parts = ARRAY_SIZE(nand_partitions), ··· 386 387 .srgr2 = GSYNC | CLKSP | FSGM | FPER(31), 387 388 388 389 .pcr0 = CLKRM | SCLKME | FSXP | FSRP | CLKXP | CLKRP, 389 389 - //.pcr0 = CLKXP | CLKRP, /* mcbsp: slave */ 390 390 + /*.pcr0 = CLKXP | CLKRP,*/ /* mcbsp: slave */ 390 391 }; 391 392 392 393 static struct omap_alsa_codec_config alsa_config = { 393 394 .name = "H3 TSC2101", 394 395 .mcbsp_regs_alsa = &mcbsp_regs, 395 395 - .codec_configure_dev = NULL, // tsc2101_configure, 396 396 - .codec_set_samplerate = NULL, // tsc2101_set_samplerate, 397 397 - .codec_clock_setup = NULL, // tsc2101_clock_setup, 398 398 - .codec_clock_on = NULL, // tsc2101_clock_on, 399 399 - .codec_clock_off = NULL, // tsc2101_clock_off, 400 400 - .get_default_samplerate = NULL, // tsc2101_get_default_samplerate, 396 396 + .codec_configure_dev = NULL, /* tsc2101_configure, */ 397 397 + .codec_set_samplerate = NULL, /* tsc2101_set_samplerate, */ 398 398 + .codec_clock_setup = NULL, /* tsc2101_clock_setup, */ 399 399 + .codec_clock_on = NULL, /* tsc2101_clock_on, */ 400 400 + .codec_clock_off = NULL, /* tsc2101_clock_off, */ 401 401 + .get_default_samplerate = NULL, /* tsc2101_get_default_samplerate, */ 401 402 }; 402 403 403 404 static struct platform_device h3_mcbsp1_device = { ··· 435 436 436 437 static struct omap_mmc_config h3_mmc_config __initdata = { 437 438 .mmc[0] = { 438 438 - .enabled = 1, 439 439 - .power_pin = -1, /* tps65010 GPIO4 */ 440 440 - .switch_pin = OMAP_MPUIO(1), 441 441 - }, 439 439 + .enabled = 1, 440 440 + .wire4 = 1, 441 441 + }, 442 442 }; 443 443 + 444 444 + extern struct omap_mmc_platform_data h3_mmc_data; 443 445 444 446 static struct omap_uart_config h3_uart_config __initdata = { 445 447 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), ··· 450 450 .ctrl_name = "internal", 451 451 }; 452 452 453 453 - static struct omap_board_config_kernel h3_config[] = { 453 453 + static struct omap_board_config_kernel h3_config[] __initdata = { 454 454 { OMAP_TAG_USB, &h3_usb_config }, 455 455 { OMAP_TAG_MMC, &h3_mmc_config }, 456 456 { OMAP_TAG_UART, &h3_uart_config }, 457 457 { OMAP_TAG_LCD, &h3_lcd_config }, 458 458 }; 459 459 460 460 - static struct i2c_board_info __initdata h3_i2c_board_info[] = { 460 460 + static struct omap_gpio_switch h3_gpio_switches[] __initdata = { 461 461 { 462 462 - I2C_BOARD_INFO("tps65010", 0x48), 463 463 - .type = "tps65013", 464 464 - /* .irq = OMAP_GPIO_IRQ(??), */ 462 462 + .name = "mmc_slot", 463 463 + .gpio = OMAP_MPUIO(1), 464 464 + .type = OMAP_GPIO_SWITCH_TYPE_COVER, 465 465 + .debounce_rising = 100, 466 466 + .debounce_falling = 0, 467 467 + .notify = h3_mmc_slot_cover_handler, 468 468 + .notify_data = NULL, 465 469 }, 466 466 - /* TODO when driver support is ready: 467 467 - * - isp1301 OTG transceiver 468 468 - * - optional ov9640 camera sensor at 0x30 469 469 - * - ... 470 470 - */ 471 470 }; 472 471 473 472 #define H3_NAND_RB_GPIO_PIN 10 474 473 475 475 - static int nand_dev_ready(struct nand_platform_data *data) 474 474 + static int nand_dev_ready(struct omap_nand_platform_data *data) 476 475 { 477 476 return omap_get_gpio_datain(H3_NAND_RB_GPIO_PIN); 478 477 } ··· 499 500 omap_cfg_reg(V2_1710_GPIO10); 500 501 501 502 platform_add_devices(devices, ARRAY_SIZE(devices)); 503 503 + spi_register_board_info(h3_spi_board_info, 504 504 + ARRAY_SIZE(h3_spi_board_info)); 502 505 omap_board_config = h3_config; 503 506 omap_board_config_size = ARRAY_SIZE(h3_config); 504 507 omap_serial_init(); 505 505 - 506 506 - /* FIXME setup irq for tps65013 chip */ 507 507 - i2c_register_board_info(1, h3_i2c_board_info, 508 508 - ARRAY_SIZE(h3_i2c_board_info)); 508 508 + omap_register_i2c_bus(1, 100, h3_i2c_board_info, 509 509 + ARRAY_SIZE(h3_i2c_board_info)); 510 510 + h3_mmc_init(); 509 511 } 510 512 511 513 static void __init h3_init_smc91x(void) ··· 530 530 { 531 531 omap1_map_common_io(); 532 532 } 533 533 - 534 534 - #ifdef CONFIG_TPS65010 535 535 - static int __init h3_tps_init(void) 536 536 - { 537 537 - if (!machine_is_omap_h3()) 538 538 - return 0; 539 539 - 540 540 - /* gpio4 for SD, gpio3 for VDD_DSP */ 541 541 - /* FIXME send power to DSP iff it's configured */ 542 542 - 543 543 - /* Enable LOW_PWR */ 544 544 - tps65013_set_low_pwr(ON); 545 545 - 546 546 - return 0; 547 547 - } 548 548 - fs_initcall(h3_tps_init); 549 549 - #endif 550 533 551 534 MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board") 552 535 /* Maintainer: Texas Instruments, Inc. */

+10 -9

arch/arm/mach-omap1/board-innovator.c

reviewed

··· 134 134 static struct omap_alsa_codec_config alsa_config = { 135 135 .name = "OMAP Innovator AIC23", 136 136 .mcbsp_regs_alsa = &mcbsp_regs, 137 137 - .codec_configure_dev = NULL, // aic23_configure, 138 138 - .codec_set_samplerate = NULL, // aic23_set_samplerate, 139 139 - .codec_clock_setup = NULL, // aic23_clock_setup, 140 140 - .codec_clock_on = NULL, // aic23_clock_on, 141 141 - .codec_clock_off = NULL, // aic23_clock_off, 142 142 - .get_default_samplerate = NULL, // aic23_get_default_samplerate, 137 137 + .codec_configure_dev = NULL, /* aic23_configure, */ 138 138 + .codec_set_samplerate = NULL, /* aic23_set_samplerate, */ 139 139 + .codec_clock_setup = NULL, /* aic23_clock_setup, */ 140 140 + .codec_clock_on = NULL, /* aic23_clock_on, */ 141 141 + .codec_clock_off = NULL, /* aic23_clock_off, */ 142 142 + .get_default_samplerate = NULL, /* aic23_get_default_samplerate, */ 143 143 }; 144 144 145 145 static struct platform_device innovator_mcbsp1_device = { ··· 345 345 .otg = 2, 346 346 347 347 #ifdef CONFIG_USB_GADGET_OMAP 348 348 - .hmc_mode = 19, // 0:host(off) 1:dev|otg 2:disabled 349 349 - // .hmc_mode = 21, // 0:host(off) 1:dev(loopback) 2:host(loopback) 348 348 + .hmc_mode = 19, /* 0:host(off) 1:dev|otg 2:disabled */ 349 349 + /* .hmc_mode = 21,*/ /* 0:host(off) 1:dev(loopback) 2:host(loopback) */ 350 350 #elif defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 351 351 /* NONSTANDARD CABLE NEEDED (B-to-Mini-B) */ 352 352 - .hmc_mode = 20, // 1:dev|otg(off) 1:host 2:disabled 352 352 + .hmc_mode = 20, /* 1:dev|otg(off) 1:host 2:disabled */ 353 353 #endif 354 354 355 355 .pins[1] = 3, ··· 411 411 omap_board_config = innovator_config; 412 412 omap_board_config_size = ARRAY_SIZE(innovator_config); 413 413 omap_serial_init(); 414 414 + omap_register_i2c_bus(1, 100, NULL, 0); 414 415 } 415 416 416 417 static void __init innovator_map_io(void)

+2 -1

arch/arm/mach-omap1/board-nokia770.c

reviewed

··· 189 189 }, 190 190 }; 191 191 192 192 - static struct omap_board_config_kernel nokia770_config[] = { 192 192 + static struct omap_board_config_kernel nokia770_config[] __initdata = { 193 193 { OMAP_TAG_USB, NULL }, 194 194 { OMAP_TAG_MMC, &nokia770_mmc_config }, 195 195 }; ··· 330 330 omap_board_config_size = ARRAY_SIZE(nokia770_config); 331 331 omap_gpio_init(); 332 332 omap_serial_init(); 333 333 + omap_register_i2c_bus(1, 100, NULL, 0); 333 334 omap_dsp_init(); 334 335 ads7846_dev_init(); 335 336 mipid_dev_init();

+12 -13

arch/arm/mach-omap1/board-osk.c

reviewed

··· 160 160 static struct omap_alsa_codec_config alsa_config = { 161 161 .name = "OSK AIC23", 162 162 .mcbsp_regs_alsa = &mcbsp_regs, 163 163 - .codec_configure_dev = NULL, // aic23_configure, 164 164 - .codec_set_samplerate = NULL, // aic23_set_samplerate, 165 165 - .codec_clock_setup = NULL, // aic23_clock_setup, 166 166 - .codec_clock_on = NULL, // aic23_clock_on, 167 167 - .codec_clock_off = NULL, // aic23_clock_off, 168 168 - .get_default_samplerate = NULL, // aic23_get_default_samplerate, 163 163 + .codec_configure_dev = NULL, /* aic23_configure, */ 164 164 + .codec_set_samplerate = NULL, /* aic23_set_samplerate, */ 165 165 + .codec_clock_setup = NULL, /* aic23_clock_setup, */ 166 166 + .codec_clock_on = NULL, /* aic23_clock_on, */ 167 167 + .codec_clock_off = NULL, /* aic23_clock_off, */ 168 168 + .get_default_samplerate = NULL, /* aic23_get_default_samplerate, */ 169 169 }; 170 170 171 171 static struct platform_device osk5912_mcbsp1_device = { ··· 253 253 }; 254 254 #endif 255 255 256 256 - static struct omap_board_config_kernel osk_config[] = { 256 256 + static struct omap_board_config_kernel osk_config[] __initdata = { 257 257 { OMAP_TAG_USB, &osk_usb_config }, 258 258 { OMAP_TAG_UART, &osk_uart_config }, 259 259 #ifdef CONFIG_OMAP_OSK_MISTRAL ··· 392 392 omap_cfg_reg(W13_1610_CCP_CLKM); 393 393 omap_cfg_reg(Y12_1610_CCP_CLKP); 394 394 /* CCP_DATAM CONFLICTS WITH UART1.TX (and serial console) */ 395 395 - // omap_cfg_reg(Y14_1610_CCP_DATAM); 395 395 + /* omap_cfg_reg(Y14_1610_CCP_DATAM); */ 396 396 omap_cfg_reg(W14_1610_CCP_DATAP); 397 397 398 398 /* CAM_PWDN */ ··· 404 404 pr_debug("OSK+Mistral: CAM_PWDN is awol\n"); 405 405 406 406 407 407 - // omap_cfg_reg(P19_1610_GPIO6); // BUSY 408 408 - omap_cfg_reg(P20_1610_GPIO4); // PENIRQ 407 407 + /* omap_cfg_reg(P19_1610_GPIO6); */ /* BUSY */ 408 408 + omap_cfg_reg(P20_1610_GPIO4); /* PENIRQ */ 409 409 set_irq_type(OMAP_GPIO_IRQ(4), IRQT_FALLING); 410 410 spi_register_board_info(mistral_boardinfo, 411 411 ARRAY_SIZE(mistral_boardinfo)); ··· 473 473 if (gpio_request(OMAP_MPUIO(1), "tps65010") == 0) 474 474 gpio_direction_input(OMAP_MPUIO(1)); 475 475 476 476 - i2c_register_board_info(1, osk_i2c_board_info, 477 477 - ARRAY_SIZE(osk_i2c_board_info)); 478 478 - 479 476 omap_serial_init(); 477 477 + omap_register_i2c_bus(1, 400, osk_i2c_board_info, 478 478 + ARRAY_SIZE(osk_i2c_board_info)); 480 479 osk_mistral_init(); 481 480 } 482 481

+23 -61

arch/arm/mach-omap1/board-palmte.c

reviewed

··· 10 10 * Maintainers : http://palmtelinux.sf.net 11 11 * palmtelinux-developpers@lists.sf.net 12 12 * 13 13 + * Copyright (c) 2006 Andrzej Zaborowski <balrog@zabor.org> 14 14 + * 13 15 * This program is free software; you can redistribute it and/or modify 14 16 * it under the terms of the GNU General Public License version 2 as 15 17 * published by the Free Software Foundation. ··· 26 24 #include <linux/spi/spi.h> 27 25 #include <linux/spi/tsc2102.h> 28 26 #include <linux/interrupt.h> 27 27 + #include <linux/apm-emulation.h> 29 28 30 30 - #include <asm/apm.h> 31 29 #include <asm/hardware.h> 32 30 #include <asm/mach-types.h> 33 31 #include <asm/mach/arch.h> ··· 53 51 omap_gpio_init(); 54 52 } 55 53 56 56 - static int palmte_keymap[] = { 57 57 - KEY(0, 0, KEY_F1), 58 58 - KEY(0, 1, KEY_F2), 59 59 - KEY(0, 2, KEY_F3), 60 60 - KEY(0, 3, KEY_F4), 54 54 + static const int palmte_keymap[] = { 55 55 + KEY(0, 0, KEY_F1), /* Calendar */ 56 56 + KEY(0, 1, KEY_F2), /* Contacts */ 57 57 + KEY(0, 2, KEY_F3), /* Tasks List */ 58 58 + KEY(0, 3, KEY_F4), /* Note Pad */ 61 59 KEY(0, 4, KEY_POWER), 62 60 KEY(1, 0, KEY_LEFT), 63 61 KEY(1, 1, KEY_DOWN), ··· 70 68 static struct omap_kp_platform_data palmte_kp_data = { 71 69 .rows = 8, 72 70 .cols = 8, 73 73 - .keymap = palmte_keymap, 71 71 + .keymap = (int *) palmte_keymap, 74 72 .rep = 1, 75 73 .delay = 12, 76 74 }; ··· 182 180 .resource = palmte_irda_resources, 183 181 }; 184 182 185 185 - static struct platform_device *devices[] __initdata = { 183 183 + static struct platform_device *palmte_devices[] __initdata = { 186 184 &palmte_rom_device, 187 185 &palmte_kp_device, 188 186 &palmte_lcd_device, ··· 275 273 info->time = 0; 276 274 } else { 277 275 while (hi > lo + 1) { 278 278 - mid = (hi + lo) >> 2; 276 276 + mid = (hi + lo) >> 1; 279 277 if (batt <= palmte_battery_sample[mid]) 280 278 lo = mid; 281 279 else ··· 323 321 .alsa_config = &palmte_alsa_config, 324 322 }; 325 323 326 326 - static struct omap_board_config_kernel palmte_config[] = { 324 324 + static struct omap_board_config_kernel palmte_config[] __initdata = { 327 325 { OMAP_TAG_USB, &palmte_usb_config }, 328 326 { OMAP_TAG_MMC, &palmte_mmc_config }, 329 327 { OMAP_TAG_LCD, &palmte_lcd_config }, ··· 341 339 }, 342 340 }; 343 341 344 344 - /* Periodically check for changes on important input pins */ 345 345 - struct timer_list palmte_pin_timer; 346 346 - int prev_power, prev_headphones; 347 347 - 348 348 - static void palmte_pin_handler(unsigned long data) { 349 349 - int power, headphones; 350 350 - 351 351 - power = !omap_get_gpio_datain(PALMTE_DC_GPIO); 352 352 - headphones = omap_get_gpio_datain(PALMTE_HEADPHONES_GPIO); 353 353 - 354 354 - if (power && !prev_power) 355 355 - printk(KERN_INFO "PM: cable connected\n"); 356 356 - else if (!power && prev_power) 357 357 - printk(KERN_INFO "PM: cable disconnected\n"); 358 358 - 359 359 - if (headphones && !prev_headphones) { 342 342 + static void palmte_headphones_detect(void *data, int state) 343 343 + { 344 344 + if (state) { 360 345 /* Headphones connected, disable speaker */ 361 346 omap_set_gpio_dataout(PALMTE_SPEAKER_GPIO, 0); 362 347 printk(KERN_INFO "PM: speaker off\n"); 363 363 - } else if (!headphones && prev_headphones) { 348 348 + } else { 364 349 /* Headphones unplugged, re-enable speaker */ 365 350 omap_set_gpio_dataout(PALMTE_SPEAKER_GPIO, 1); 366 351 printk(KERN_INFO "PM: speaker on\n"); 367 352 } 368 368 - 369 369 - prev_power = power; 370 370 - prev_headphones = headphones; 371 371 - mod_timer(&palmte_pin_timer, jiffies + msecs_to_jiffies(500)); 372 353 } 373 354 374 374 - static void __init palmte_gpio_setup(void) 355 355 + static void __init palmte_misc_gpio_setup(void) 375 356 { 376 376 - /* Set TSC2102 PINTDAV pin as input */ 357 357 + /* Set TSC2102 PINTDAV pin as input (used by TSC2102 driver) */ 377 358 if (omap_request_gpio(PALMTE_PINTDAV_GPIO)) { 378 359 printk(KERN_ERR "Could not reserve PINTDAV GPIO!\n"); 379 360 return; 380 361 } 381 362 omap_set_gpio_direction(PALMTE_PINTDAV_GPIO, 1); 382 363 383 383 - /* Monitor cable-connected signals */ 384 384 - if (omap_request_gpio(PALMTE_DC_GPIO) || 385 385 - omap_request_gpio(PALMTE_USB_OR_DC_GPIO) || 386 386 - omap_request_gpio(PALMTE_USBDETECT_GPIO)) { 364 364 + /* Set USB-or-DC-IN pin as input (unused) */ 365 365 + if (omap_request_gpio(PALMTE_USB_OR_DC_GPIO)) { 387 366 printk(KERN_ERR "Could not reserve cable signal GPIO!\n"); 388 367 return; 389 368 } 390 390 - omap_set_gpio_direction(PALMTE_DC_GPIO, 1); 391 369 omap_set_gpio_direction(PALMTE_USB_OR_DC_GPIO, 1); 392 392 - omap_set_gpio_direction(PALMTE_USBDETECT_GPIO, 1); 393 393 - 394 394 - /* Set speaker-enable pin as output */ 395 395 - if (omap_request_gpio(PALMTE_SPEAKER_GPIO)) { 396 396 - printk(KERN_ERR "Could not reserve speaker GPIO!\n"); 397 397 - return; 398 398 - } 399 399 - omap_set_gpio_direction(PALMTE_SPEAKER_GPIO, 0); 400 400 - 401 401 - /* Monitor the headphones-connected signal */ 402 402 - if (omap_request_gpio(PALMTE_HEADPHONES_GPIO)) { 403 403 - printk(KERN_ERR "Could not reserve headphones signal GPIO!\n"); 404 404 - return; 405 405 - } 406 406 - omap_set_gpio_direction(PALMTE_HEADPHONES_GPIO, 1); 407 407 - 408 408 - prev_power = omap_get_gpio_datain(PALMTE_DC_GPIO); 409 409 - prev_headphones = !omap_get_gpio_datain(PALMTE_HEADPHONES_GPIO); 410 410 - setup_timer(&palmte_pin_timer, palmte_pin_handler, 0); 411 411 - palmte_pin_handler(0); 412 370 } 413 371 414 372 static void __init omap_palmte_init(void) ··· 376 414 omap_board_config = palmte_config; 377 415 omap_board_config_size = ARRAY_SIZE(palmte_config); 378 416 379 379 - platform_add_devices(devices, ARRAY_SIZE(devices)); 417 417 + platform_add_devices(palmte_devices, ARRAY_SIZE(palmte_devices)); 380 418 381 419 spi_register_board_info(palmte_spi_info, ARRAY_SIZE(palmte_spi_info)); 382 382 - 420 420 + palmte_misc_gpio_setup(); 383 421 omap_serial_init(); 384 384 - palmte_gpio_setup(); 422 422 + omap_register_i2c_bus(1, 100, NULL, 0); 385 423 } 386 424 387 425 static void __init omap_palmte_map_io(void)

+8 -7

arch/arm/mach-omap1/board-palmtt.c

reviewed

··· 144 144 static struct omap_alsa_codec_config alsa_config = { 145 145 .name = "PalmTT AIC23", 146 146 .mcbsp_regs_alsa = &mcbsp_regs, 147 147 - .codec_configure_dev = NULL, // aic23_configure, 148 148 - .codec_set_samplerate = NULL, // aic23_set_samplerate, 149 149 - .codec_clock_setup = NULL, // aic23_clock_setup, 150 150 - .codec_clock_on = NULL, // aic23_clock_on, 151 151 - .codec_clock_off = NULL, // aic23_clock_off, 152 152 - .get_default_samplerate = NULL, // aic23_get_default_samplerate, 147 147 + .codec_configure_dev = NULL, /* aic23_configure, */ 148 148 + .codec_set_samplerate = NULL, /* aic23_set_samplerate, */ 149 149 + .codec_clock_setup = NULL, /* aic23_clock_setup, */ 150 150 + .codec_clock_on = NULL, /* aic23_clock_on, */ 151 151 + .codec_clock_off = NULL, /* aic23_clock_off, */ 152 152 + .get_default_samplerate = NULL, /* aic23_get_default_samplerate, */ 153 153 }; 154 154 155 155 static struct platform_device palmtt_mcbsp1_device = { ··· 312 312 .enabled_uarts = (1 << 0) | (1 << 1) | (0 << 2), 313 313 }; 314 314 315 315 - static struct omap_board_config_kernel palmtt_config[] = { 315 315 + static struct omap_board_config_kernel palmtt_config[] __initdata = { 316 316 { OMAP_TAG_USB, &palmtt_usb_config }, 317 317 { OMAP_TAG_LCD, &palmtt_lcd_config }, 318 318 { OMAP_TAG_UART, &palmtt_uart_config }, ··· 338 338 339 339 spi_register_board_info(palmtt_boardinfo,ARRAY_SIZE(palmtt_boardinfo)); 340 340 omap_serial_init(); 341 341 + omap_register_i2c_bus(1, 100, NULL, 0); 341 342 } 342 343 343 344 static void __init omap_palmtt_map_io(void)

+2 -1

arch/arm/mach-omap1/board-palmz71.c

reviewed

··· 285 285 .enabled_uarts = (1 << 0) | (1 << 1) | (0 << 2), 286 286 }; 287 287 288 288 - static struct omap_board_config_kernel palmz71_config[] = { 288 288 + static struct omap_board_config_kernel palmz71_config[] __initdata = { 289 289 {OMAP_TAG_USB, &palmz71_usb_config}, 290 290 {OMAP_TAG_MMC, &palmz71_mmc_config}, 291 291 {OMAP_TAG_LCD, &palmz71_lcd_config}, ··· 363 363 spi_register_board_info(palmz71_boardinfo, 364 364 ARRAY_SIZE(palmz71_boardinfo)); 365 365 omap_serial_init(); 366 366 + omap_register_i2c_bus(1, 100, NULL, 0); 366 367 palmz71_gpio_setup(0); 367 368 } 368 369

+5 -3

arch/arm/mach-omap1/board-perseus2.c

reviewed

··· 30 30 #include <asm/arch/gpio.h> 31 31 #include <asm/arch/mux.h> 32 32 #include <asm/arch/fpga.h> 33 33 + #include <asm/arch/nand.h> 33 34 #include <asm/arch/keypad.h> 34 35 #include <asm/arch/common.h> 35 36 #include <asm/arch/board.h> ··· 134 133 .resource = &nor_resource, 135 134 }; 136 135 137 137 - static struct nand_platform_data nand_data = { 136 136 + static struct omap_nand_platform_data nand_data = { 138 137 .options = NAND_SAMSUNG_LP_OPTIONS, 139 138 }; 140 139 ··· 203 202 204 203 #define P2_NAND_RB_GPIO_PIN 62 205 204 206 206 - static int nand_dev_ready(struct nand_platform_data *data) 205 205 + static int nand_dev_ready(struct omap_nand_platform_data *data) 207 206 { 208 207 return omap_get_gpio_datain(P2_NAND_RB_GPIO_PIN); 209 208 } ··· 216 215 .ctrl_name = "internal", 217 216 }; 218 217 219 219 - static struct omap_board_config_kernel perseus2_config[] = { 218 218 + static struct omap_board_config_kernel perseus2_config[] __initdata = { 220 219 { OMAP_TAG_UART, &perseus2_uart_config }, 221 220 { OMAP_TAG_LCD, &perseus2_lcd_config }, 222 221 }; ··· 234 233 omap_board_config = perseus2_config; 235 234 omap_board_config_size = ARRAY_SIZE(perseus2_config); 236 235 omap_serial_init(); 236 236 + omap_register_i2c_bus(1, 100, NULL, 0); 237 237 } 238 238 239 239 static void __init perseus2_init_smc91x(void)

+124

arch/arm/mach-omap1/board-sx1-mmc.c

reviewed

··· 1 1 + /* 2 2 + * linux/arch/arm/mach-omap1/board-sx1-mmc.c 3 3 + * 4 4 + * Copyright (C) 2007 Instituto Nokia de Tecnologia - INdT 5 5 + * Author: Carlos Eduardo Aguiar <carlos.aguiar@indt.org.br> 6 6 + * 7 7 + * This code is based on linux/arch/arm/mach-omap1/board-h2-mmc.c, which is: 8 8 + * Copyright (C) 2007 Instituto Nokia de Tecnologia - INdT 9 9 + * 10 10 + * This program is free software; you can redistribute it and/or modify 11 11 + * it under the terms of the GNU General Public License version 2 as 12 12 + * published by the Free Software Foundation. 13 13 + */ 14 14 + 15 15 + #include <asm/arch/hardware.h> 16 16 + #include <asm/arch/mmc.h> 17 17 + #include <asm/arch/gpio.h> 18 18 + 19 19 + #ifdef CONFIG_MMC_OMAP 20 20 + static int slot_cover_open; 21 21 + static struct device *mmc_device; 22 22 + 23 23 + static int sx1_mmc_set_power(struct device *dev, int slot, int power_on, 24 24 + int vdd) 25 25 + { 26 26 + int err; 27 27 + u8 dat = 0; 28 28 + 29 29 + #ifdef CONFIG_MMC_DEBUG 30 30 + dev_dbg(dev, "Set slot %d power: %s (vdd %d)\n", slot + 1, 31 31 + power_on ? "on" : "off", vdd); 32 32 + #endif 33 33 + 34 34 + if (slot != 0) { 35 35 + dev_err(dev, "No such slot %d\n", slot + 1); 36 36 + return -ENODEV; 37 37 + } 38 38 + 39 39 + err = sx1_i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, &dat); 40 40 + if (err < 0) 41 41 + return err; 42 42 + 43 43 + if (power_on) 44 44 + dat |= SOFIA_MMC_POWER; 45 45 + else 46 46 + dat &= ~SOFIA_MMC_POWER; 47 47 + 48 48 + return sx1_i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, dat); 49 49 + } 50 50 + 51 51 + static int sx1_mmc_set_bus_mode(struct device *dev, int slot, int bus_mode) 52 52 + { 53 53 + #ifdef CONFIG_MMC_DEBUG 54 54 + dev_dbg(dev, "Set slot %d bus_mode %s\n", slot + 1, 55 55 + bus_mode == MMC_BUSMODE_OPENDRAIN ? "open-drain" : "push-pull"); 56 56 + #endif 57 57 + if (slot != 0) { 58 58 + dev_err(dev, "No such slot %d\n", slot + 1); 59 59 + return -ENODEV; 60 60 + } 61 61 + 62 62 + return 0; 63 63 + } 64 64 + 65 65 + static int sx1_mmc_get_cover_state(struct device *dev, int slot) 66 66 + { 67 67 + BUG_ON(slot != 0); 68 68 + 69 69 + return slot_cover_open; 70 70 + } 71 71 + 72 72 + void sx1_mmc_slot_cover_handler(void *arg, int state) 73 73 + { 74 74 + if (mmc_device == NULL) 75 75 + return; 76 76 + 77 77 + slot_cover_open = state; 78 78 + omap_mmc_notify_cover_event(mmc_device, 0, state); 79 79 + } 80 80 + 81 81 + static int sx1_mmc_late_init(struct device *dev) 82 82 + { 83 83 + int ret = 0; 84 84 + 85 85 + mmc_device = dev; 86 86 + 87 87 + return ret; 88 88 + } 89 89 + 90 90 + static void sx1_mmc_cleanup(struct device *dev) 91 91 + { 92 92 + } 93 93 + 94 94 + static struct omap_mmc_platform_data sx1_mmc_data = { 95 95 + .nr_slots = 1, 96 96 + .switch_slot = NULL, 97 97 + .init = sx1_mmc_late_init, 98 98 + .cleanup = sx1_mmc_cleanup, 99 99 + .slots[0] = { 100 100 + .set_power = sx1_mmc_set_power, 101 101 + .set_bus_mode = sx1_mmc_set_bus_mode, 102 102 + .get_ro = NULL, 103 103 + .get_cover_state = sx1_mmc_get_cover_state, 104 104 + .ocr_mask = MMC_VDD_28_29 | MMC_VDD_30_31 | 105 105 + MMC_VDD_32_33 | MMC_VDD_33_34, 106 106 + .name = "mmcblk", 107 107 + }, 108 108 + }; 109 109 + 110 110 + void __init sx1_mmc_init(void) 111 111 + { 112 112 + omap_set_mmc_info(1, &sx1_mmc_data); 113 113 + } 114 114 + 115 115 + #else 116 116 + 117 117 + void __init sx1_mmc_init(void) 118 118 + { 119 119 + } 120 120 + 121 121 + void sx1_mmc_slot_cover_handler(void *arg, int state) 122 122 + { 123 123 + } 124 124 + #endif

+19 -45

arch/arm/mach-omap1/board-sx1.c

reviewed

··· 44 44 #include <asm/arch/keypad.h> 45 45 46 46 /* Write to I2C device */ 47 47 - int i2c_write_byte(u8 devaddr, u8 regoffset, u8 value) 47 47 + int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value) 48 48 { 49 49 struct i2c_adapter *adap; 50 50 int err; ··· 67 67 } 68 68 69 69 /* Read from I2C device */ 70 70 - int i2c_read_byte(u8 devaddr, u8 regoffset, u8 * value) 70 70 + int sx1_i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value) 71 71 { 72 72 struct i2c_adapter *adap; 73 73 int err; ··· 101 101 { 102 102 if (keylight > SOFIA_MAX_LIGHT_VAL) 103 103 keylight = SOFIA_MAX_LIGHT_VAL; 104 104 - return i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_KEYLIGHT_REG, keylight); 104 104 + return sx1_i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_KEYLIGHT_REG, keylight); 105 105 } 106 106 /* get current keylight intensity */ 107 107 int sx1_getkeylight(u8 * keylight) 108 108 { 109 109 - return i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_KEYLIGHT_REG, keylight); 109 109 + return sx1_i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_KEYLIGHT_REG, keylight); 110 110 } 111 111 /* set LCD backlight intensity */ 112 112 int sx1_setbacklight(u8 backlight) 113 113 { 114 114 if (backlight > SOFIA_MAX_LIGHT_VAL) 115 115 backlight = SOFIA_MAX_LIGHT_VAL; 116 116 - return i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_BACKLIGHT_REG, backlight); 116 116 + return sx1_i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_BACKLIGHT_REG, 117 117 + backlight); 117 118 } 118 119 /* get current LCD backlight intensity */ 119 120 int sx1_getbacklight (u8 * backlight) 120 121 { 121 121 - return i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_BACKLIGHT_REG, backlight); 122 122 + return sx1_i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_BACKLIGHT_REG, 123 123 + backlight); 122 124 } 123 125 /* set LCD backlight power on/off */ 124 126 int sx1_setmmipower(u8 onoff) 125 127 { 126 128 int err; 127 129 u8 dat = 0; 128 128 - err = i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, &dat); 130 130 + err = sx1_i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, &dat); 129 131 if (err < 0) 130 132 return err; 131 133 if (onoff) 132 134 dat |= SOFIA_MMILIGHT_POWER; 133 135 else 134 136 dat &= ~SOFIA_MMILIGHT_POWER; 135 135 - return i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, dat); 137 137 + return sx1_i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, dat); 136 138 } 137 137 - /* set MMC power on/off */ 138 138 - int sx1_setmmcpower(u8 onoff) 139 139 - { 140 140 - int err; 141 141 - u8 dat = 0; 142 142 - err = i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, &dat); 143 143 - if (err < 0) 144 144 - return err; 145 145 - if (onoff) 146 146 - dat |= SOFIA_MMC_POWER; 147 147 - else 148 148 - dat &= ~SOFIA_MMC_POWER; 149 149 - return i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, dat); 150 150 - } 139 139 + 151 140 /* set USB power on/off */ 152 141 int sx1_setusbpower(u8 onoff) 153 142 { 154 143 int err; 155 144 u8 dat = 0; 156 156 - err = i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, &dat); 145 145 + err = sx1_i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, &dat); 157 146 if (err < 0) 158 147 return err; 159 148 if (onoff) 160 149 dat |= SOFIA_USB_POWER; 161 150 else 162 151 dat &= ~SOFIA_USB_POWER; 163 163 - return i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, dat); 152 152 + return sx1_i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, dat); 164 153 } 165 154 166 155 EXPORT_SYMBOL(sx1_setkeylight); ··· 157 168 EXPORT_SYMBOL(sx1_setbacklight); 158 169 EXPORT_SYMBOL(sx1_getbacklight); 159 170 EXPORT_SYMBOL(sx1_setmmipower); 160 160 - EXPORT_SYMBOL(sx1_setmmcpower); 161 171 EXPORT_SYMBOL(sx1_setusbpower); 162 172 163 173 /*----------- Keypad -------------------------*/ ··· 266 278 .srgr2 = FSGM | FPER(31), /* SRGR2=101f */ 267 279 .pcr0 = FSXM | FSRM | CLKXM | CLKRM | FSXP | FSRP | CLKXP | CLKRP, 268 280 /* PCR0 =0f0f */ 269 269 - }; 270 270 - 271 271 - /* TODO: PCM interface - McBSP2 */ 272 272 - static struct omap_mcbsp_reg_cfg mcbsp2_regs = { 273 273 - .spcr2 = FRST | GRST | XRST | XINTM(3), /* SPCR2=F1 */ 274 274 - .spcr1 = RINTM(3) | RRST, /* SPCR1=30 */ 275 275 - .rcr2 = 0, /* RCR2 =00 */ 276 276 - .rcr1 = RFRLEN1(1) | RWDLEN1(OMAP_MCBSP_WORD_16), /* RCR1 = 140 */ 277 277 - .xcr2 = 0, /* XCR2 = 0 */ 278 278 - .xcr1 = XFRLEN1(1) | XWDLEN1(OMAP_MCBSP_WORD_16), /* XCR1 = 140 */ 279 279 - .srgr1 = FWID(15) | CLKGDV(12), /* SRGR1=0f0c */ 280 280 - .srgr2 = FSGM | FPER(31), /* SRGR2=101f */ 281 281 - .pcr0 = FSXM | FSRM | CLKXM | CLKRM | FSXP | FSRP | CLKXP | CLKRP, 282 282 - /* PCR0=0f0f */ 283 283 - /* mcbsp: slave */ 284 281 }; 285 282 286 283 static struct omap_alsa_codec_config sx1_alsa_config = { ··· 380 407 381 408 static struct omap_mmc_config sx1_mmc_config __initdata = { 382 409 .mmc [0] = { 383 383 - .enabled = 1, 410 410 + .enabled = 1, 384 411 .wire4 = 0, 385 385 - .wp_pin = -1, 386 386 - .power_pin = -1, /* power is in Sofia */ 387 387 - .switch_pin = OMAP_MPUIO(3), 388 412 }, 389 413 }; 390 414 ··· 410 440 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), 411 441 }; 412 442 413 413 - static struct omap_board_config_kernel sx1_config[] = { 443 443 + static struct omap_board_config_kernel sx1_config[] __initdata = { 414 444 { OMAP_TAG_USB, &sx1_usb_config }, 415 445 { OMAP_TAG_MMC, &sx1_mmc_config }, 416 446 { OMAP_TAG_LCD, &sx1_lcd_config }, 417 447 { OMAP_TAG_UART, &sx1_uart_config }, 418 448 }; 449 449 + 419 450 /*-----------------------------------------*/ 451 451 + 420 452 static void __init omap_sx1_init(void) 421 453 { 422 454 platform_add_devices(sx1_devices, ARRAY_SIZE(sx1_devices)); ··· 426 454 omap_board_config = sx1_config; 427 455 omap_board_config_size = ARRAY_SIZE(sx1_config); 428 456 omap_serial_init(); 457 457 + omap_register_i2c_bus(1, 100, NULL, 0); 458 458 + sx1_mmc_init(); 429 459 430 460 /* turn on USB power */ 431 461 /* sx1_setusbpower(1); cant do it here because i2c is not ready */

+1 -3

arch/arm/mach-omap1/board-voiceblue.c

reviewed

··· 34 34 #include <asm/arch/tc.h> 35 35 #include <asm/arch/usb.h> 36 36 37 37 - extern void omap_init_time(void); 38 38 - extern int omap_gpio_init(void); 39 39 - 40 37 static struct plat_serial8250_port voiceblue_ports[] = { 41 38 { 42 39 .mapbase = (unsigned long)(OMAP_CS1_PHYS + 0x40000), ··· 195 198 omap_board_config = voiceblue_config; 196 199 omap_board_config_size = ARRAY_SIZE(voiceblue_config); 197 200 omap_serial_init(); 201 201 + omap_register_i2c_bus(1, 100, NULL, 0); 198 202 199 203 /* There is a good chance board is going up, so enable power LED 200 204 * (it is connected through invertor) */

+3 -4

arch/arm/mach-omap1/clock.c

reviewed

··· 1 1 - //kernel/linux-omap-fsample/arch/arm/mach-omap1/clock.c#2 - edit change 3808 (text) 2 1 /* 3 2 * linux/arch/arm/mach-omap1/clock.c 4 3 * ··· 649 650 650 651 /* FIXME: This clock seems to be necessary but no-one 651 652 * has asked for its activation. */ 652 652 - if (clk == &tc2_ck // FIX: pm.c (SRAM), CCP, Camera 653 653 - || clk == &ck_dpll1out.clk // FIX: SoSSI, SSR 654 654 - || clk == &arm_gpio_ck // FIX: GPIO code for 1510 653 653 + if (clk == &tc2_ck /* FIX: pm.c (SRAM), CCP, Camera */ 654 654 + || clk == &ck_dpll1out.clk /* FIX: SoSSI, SSR */ 655 655 + || clk == &arm_gpio_ck /* FIX: GPIO code for 1510 */ 655 656 ) { 656 657 printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n", 657 658 clk->name);

+2 -2

arch/arm/mach-omap1/leds-osk.c

reviewed

··· 82 82 red = 1; 83 83 else if (hw_led_state & IDLE_LED) 84 84 green = 1; 85 85 - // else both sides are disabled 85 85 + /* else both sides are disabled */ 86 86 87 87 omap_set_gpio_dataout(GPIO_LED_GREEN, green); 88 88 omap_set_gpio_dataout(GPIO_LED_RED, red); ··· 112 112 case led_stop: 113 113 led_state &= ~LED_STATE_ENABLED; 114 114 hw_led_state = 0; 115 115 - // NOTE: work may still be pending!! 115 115 + /* NOTE: work may still be pending!! */ 116 116 break; 117 117 118 118 case led_claim:

+7 -7

arch/arm/mach-omap1/mailbox.c

reviewed

··· 51 51 } 52 52 53 53 /* msg */ 54 54 - static inline mbox_msg_t omap1_mbox_fifo_read(struct omap_mbox *mbox) 54 54 + static mbox_msg_t omap1_mbox_fifo_read(struct omap_mbox *mbox) 55 55 { 56 56 struct omap_mbox1_fifo *fifo = 57 57 &((struct omap_mbox1_priv *)mbox->priv)->rx_fifo; ··· 63 63 return msg; 64 64 } 65 65 66 66 - static inline void 66 66 + static void 67 67 omap1_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg) 68 68 { 69 69 struct omap_mbox1_fifo *fifo = ··· 73 73 mbox_write_reg(msg >> 16, fifo->cmd); 74 74 } 75 75 76 76 - static inline int omap1_mbox_fifo_empty(struct omap_mbox *mbox) 76 76 + static int omap1_mbox_fifo_empty(struct omap_mbox *mbox) 77 77 { 78 78 return 0; 79 79 } 80 80 81 81 - static inline int omap1_mbox_fifo_full(struct omap_mbox *mbox) 81 81 + static int omap1_mbox_fifo_full(struct omap_mbox *mbox) 82 82 { 83 83 struct omap_mbox1_fifo *fifo = 84 84 &((struct omap_mbox1_priv *)mbox->priv)->rx_fifo; ··· 87 87 } 88 88 89 89 /* irq */ 90 90 - static inline void 90 90 + static void 91 91 omap1_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) 92 92 { 93 93 if (irq == IRQ_RX) 94 94 enable_irq(mbox->irq); 95 95 } 96 96 97 97 - static inline void 97 97 + static void 98 98 omap1_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) 99 99 { 100 100 if (irq == IRQ_RX) 101 101 disable_irq(mbox->irq); 102 102 } 103 103 104 104 - static inline int 104 104 + static int 105 105 omap1_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) 106 106 { 107 107 if (irq == IRQ_TX)

+13 -14

arch/arm/mach-omap1/pm.c

reviewed

··· 57 57 #include <asm/arch/pm.h> 58 58 #include <asm/arch/mux.h> 59 59 #include <asm/arch/dma.h> 60 60 - #include <asm/arch/dsp_common.h> 61 60 #include <asm/arch/dmtimer.h> 62 61 63 62 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE]; ··· 65 66 static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE]; 66 67 static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE]; 67 68 static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE]; 69 69 + 70 70 + #ifdef CONFIG_OMAP_32K_TIMER 68 71 69 72 static unsigned short enable_dyn_sleep = 1; 70 73 ··· 92 91 static struct kobj_attribute sleep_while_idle_attr = 93 92 __ATTR(sleep_while_idle, 0644, idle_show, idle_store); 94 93 95 95 - static void (*omap_sram_idle)(void) = NULL; 94 94 + #endif 95 95 + 96 96 static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL; 97 97 98 98 /* ··· 106 104 { 107 105 extern __u32 arm_idlect1_mask; 108 106 __u32 use_idlect1 = arm_idlect1_mask; 109 109 - #ifndef CONFIG_OMAP_MPU_TIMER 110 110 - int do_sleep; 111 111 - #endif 107 107 + int do_sleep = 0; 112 108 113 109 local_irq_disable(); 114 110 local_fiq_disable(); ··· 128 128 use_idlect1 = use_idlect1 & ~(1 << 9); 129 129 #else 130 130 131 131 - do_sleep = 0; 132 131 while (enable_dyn_sleep) { 133 132 134 133 #ifdef CONFIG_CBUS_TAHVO_USB ··· 139 140 do_sleep = 1; 140 141 break; 141 142 } 143 143 + 144 144 + #endif 142 145 143 146 #ifdef CONFIG_OMAP_DM_TIMER 144 147 use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1); ··· 169 168 } 170 169 omap_sram_suspend(omap_readl(ARM_IDLECT1), 171 170 omap_readl(ARM_IDLECT2)); 172 172 - #endif 173 171 174 172 local_fiq_enable(); 175 173 local_irq_enable(); ··· 661 661 662 662 static int __init omap_pm_init(void) 663 663 { 664 664 + 665 665 + #ifdef CONFIG_OMAP_32K_TIMER 664 666 int error; 667 667 + #endif 665 668 666 669 printk("Power Management for TI OMAP.\n"); 667 670 ··· 674 671 * memory the MPU can see when it wakes up. 675 672 */ 676 673 if (cpu_is_omap730()) { 677 677 - omap_sram_idle = omap_sram_push(omap730_idle_loop_suspend, 678 678 - omap730_idle_loop_suspend_sz); 679 674 omap_sram_suspend = omap_sram_push(omap730_cpu_suspend, 680 675 omap730_cpu_suspend_sz); 681 676 } else if (cpu_is_omap15xx()) { 682 682 - omap_sram_idle = omap_sram_push(omap1510_idle_loop_suspend, 683 683 - omap1510_idle_loop_suspend_sz); 684 677 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend, 685 678 omap1510_cpu_suspend_sz); 686 679 } else if (cpu_is_omap16xx()) { 687 687 - omap_sram_idle = omap_sram_push(omap1610_idle_loop_suspend, 688 688 - omap1610_idle_loop_suspend_sz); 689 680 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend, 690 681 omap1610_cpu_suspend_sz); 691 682 } 692 683 693 693 - if (omap_sram_idle == NULL || omap_sram_suspend == NULL) { 684 684 + if (omap_sram_suspend == NULL) { 694 685 printk(KERN_ERR "PM not initialized: Missing SRAM support\n"); 695 686 return -ENODEV; 696 687 } ··· 716 719 omap_pm_init_proc(); 717 720 #endif 718 721 722 722 + #ifdef CONFIG_OMAP_32K_TIMER 719 723 error = sysfs_create_file(power_kobj, &sleep_while_idle_attr); 720 724 if (error) 721 725 printk(KERN_ERR "sysfs_create_file failed: %d\n", error); 726 726 + #endif 722 727 723 728 if (cpu_is_omap16xx()) { 724 729 /* configure LOW_PWR pin */

-161

arch/arm/mach-omap1/sleep.S

reviewed

··· 39 39 40 40 .text 41 41 42 42 - /* 43 43 - * Forces OMAP into idle state 44 44 - * 45 45 - * omapXXXX_idle_loop_suspend() 46 46 - * 47 47 - * Note: This code get's copied to internal SRAM at boot. When the OMAP 48 48 - * wakes up it continues execution at the point it went to sleep. 49 49 - * 50 50 - * Note: Because of slightly different configuration values we have 51 51 - * processor specific functions here. 52 52 - */ 53 53 - 54 54 - #if defined(CONFIG_ARCH_OMAP730) 55 55 - ENTRY(omap730_idle_loop_suspend) 56 56 - 57 57 - stmfd sp!, {r0 - r12, lr} @ save registers on stack 58 58 - 59 59 - @ load base address of ARM_IDLECT1 and ARM_IDLECT2 60 60 - mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000 61 61 - orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000 62 62 - orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00 63 63 - 64 64 - @ turn off clock domains 65 65 - @ get ARM_IDLECT2 into r2 66 66 - ldrh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff] 67 67 - mov r5, #OMAP730_IDLECT2_SLEEP_VAL & 0xff 68 68 - orr r5, r5, #OMAP730_IDLECT2_SLEEP_VAL & 0xff00 69 69 - strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff] 70 70 - 71 71 - @ request ARM idle 72 72 - @ get ARM_IDLECT1 into r1 73 73 - ldrh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff] 74 74 - orr r3, r1, #OMAP730_IDLE_LOOP_REQUEST & 0xffff 75 75 - strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff] 76 76 - 77 77 - mov r5, #IDLE_WAIT_CYCLES & 0xff 78 78 - orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00 79 79 - l_730: subs r5, r5, #1 80 80 - bne l_730 81 81 - /* 82 82 - * Let's wait for the next clock tick to wake us up. 83 83 - */ 84 84 - mov r0, #0 85 85 - mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt 86 86 - /* 87 87 - * omap730_idle_loop_suspend()'s resume point. 88 88 - * 89 89 - * It will just start executing here, so we'll restore stuff from the 90 90 - * stack, reset the ARM_IDLECT1 and ARM_IDLECT2. 91 91 - */ 92 92 - 93 93 - @ restore ARM_IDLECT1 and ARM_IDLECT2 and return 94 94 - @ r1 has ARM_IDLECT1 and r2 still has ARM_IDLECT2 95 95 - strh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff] 96 96 - strh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff] 97 97 - 98 98 - ldmfd sp!, {r0 - r12, pc} @ restore regs and return 99 99 - 100 100 - ENTRY(omap730_idle_loop_suspend_sz) 101 101 - .word . - omap730_idle_loop_suspend 102 102 - #endif /* CONFIG_ARCH_OMAP730 */ 103 103 - 104 104 - #ifdef CONFIG_ARCH_OMAP15XX 105 105 - ENTRY(omap1510_idle_loop_suspend) 106 106 - 107 107 - stmfd sp!, {r0 - r12, lr} @ save registers on stack 108 108 - 109 109 - @ load base address of ARM_IDLECT1 and ARM_IDLECT2 110 110 - mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000 111 111 - orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000 112 112 - orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00 113 113 - 114 114 - @ turn off clock domains 115 115 - @ get ARM_IDLECT2 into r2 116 116 - ldrh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff] 117 117 - mov r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff 118 118 - orr r5, r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff00 119 119 - strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff] 120 120 - 121 121 - @ request ARM idle 122 122 - @ get ARM_IDLECT1 into r1 123 123 - ldrh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff] 124 124 - orr r3, r1, #OMAP1510_IDLE_LOOP_REQUEST & 0xffff 125 125 - strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff] 126 126 - 127 127 - mov r5, #IDLE_WAIT_CYCLES & 0xff 128 128 - orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00 129 129 - l_1510: subs r5, r5, #1 130 130 - bne l_1510 131 131 - /* 132 132 - * Let's wait for the next clock tick to wake us up. 133 133 - */ 134 134 - mov r0, #0 135 135 - mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt 136 136 - /* 137 137 - * omap1510_idle_loop_suspend()'s resume point. 138 138 - * 139 139 - * It will just start executing here, so we'll restore stuff from the 140 140 - * stack, reset the ARM_IDLECT1 and ARM_IDLECT2. 141 141 - */ 142 142 - 143 143 - @ restore ARM_IDLECT1 and ARM_IDLECT2 and return 144 144 - @ r1 has ARM_IDLECT1 and r2 still has ARM_IDLECT2 145 145 - strh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff] 146 146 - strh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff] 147 147 - 148 148 - ldmfd sp!, {r0 - r12, pc} @ restore regs and return 149 149 - 150 150 - ENTRY(omap1510_idle_loop_suspend_sz) 151 151 - .word . - omap1510_idle_loop_suspend 152 152 - #endif /* CONFIG_ARCH_OMAP15XX */ 153 153 - 154 154 - #if defined(CONFIG_ARCH_OMAP16XX) 155 155 - ENTRY(omap1610_idle_loop_suspend) 156 156 - 157 157 - stmfd sp!, {r0 - r12, lr} @ save registers on stack 158 158 - 159 159 - @ load base address of ARM_IDLECT1 and ARM_IDLECT2 160 160 - mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000 161 161 - orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000 162 162 - orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00 163 163 - 164 164 - @ turn off clock domains 165 165 - @ get ARM_IDLECT2 into r2 166 166 - ldrh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff] 167 167 - mov r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff 168 168 - orr r5, r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff00 169 169 - strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff] 170 170 - 171 171 - @ request ARM idle 172 172 - @ get ARM_IDLECT1 into r1 173 173 - ldrh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff] 174 174 - orr r3, r1, #OMAP1610_IDLE_LOOP_REQUEST & 0xffff 175 175 - strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff] 176 176 - 177 177 - mov r5, #IDLE_WAIT_CYCLES & 0xff 178 178 - orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00 179 179 - l_1610: subs r5, r5, #1 180 180 - bne l_1610 181 181 - /* 182 182 - * Let's wait for the next clock tick to wake us up. 183 183 - */ 184 184 - mov r0, #0 185 185 - mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt 186 186 - /* 187 187 - * omap1610_idle_loop_suspend()'s resume point. 188 188 - * 189 189 - * It will just start executing here, so we'll restore stuff from the 190 190 - * stack, reset the ARM_IDLECT1 and ARM_IDLECT2. 191 191 - */ 192 192 - 193 193 - @ restore ARM_IDLECT1 and ARM_IDLECT2 and return 194 194 - @ r1 has ARM_IDLECT1 and r2 still has ARM_IDLECT2 195 195 - strh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff] 196 196 - strh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff] 197 197 - 198 198 - ldmfd sp!, {r0 - r12, pc} @ restore regs and return 199 199 - 200 200 - ENTRY(omap1610_idle_loop_suspend_sz) 201 201 - .word . - omap1610_idle_loop_suspend 202 202 - #endif /* CONFIG_ARCH_OMAP16XX */ 203 42 204 43 /* 205 44 * Forces OMAP into deep sleep state

+7 -7

arch/arm/mach-orion/addr-map.c

reviewed

··· 265 265 } 266 266 267 267 /* 268 268 - * Setup windows for PCI+PCIE IO+MAM space 268 268 + * Setup windows for PCI+PCIe IO+MEM space. 269 269 */ 270 270 - orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_BASE, 271 271 - ORION_PCIE_IO_SIZE, ORION_PCIE_IO_REMAP); 272 272 - orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_BASE, 273 273 - ORION_PCI_IO_SIZE, ORION_PCI_IO_REMAP); 274 274 - orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_BASE, 270 270 + orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_PHYS_BASE, 271 271 + ORION_PCIE_IO_SIZE, ORION_PCIE_IO_BUS_BASE); 272 272 + orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_PHYS_BASE, 273 273 + ORION_PCI_IO_SIZE, ORION_PCI_IO_BUS_BASE); 274 274 + orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_PHYS_BASE, 275 275 ORION_PCIE_MEM_SIZE, -1); 276 276 - orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_BASE, 276 276 + orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_PHYS_BASE, 277 277 ORION_PCI_MEM_SIZE, -1); 278 278 } 279 279

+59 -25

arch/arm/mach-orion/common.c

reviewed

··· 19 19 #include <asm/page.h> 20 20 #include <asm/timex.h> 21 21 #include <asm/mach/map.h> 22 22 - #include <asm/arch/orion.h> 22 22 + #include <asm/arch/hardware.h> 23 23 #include "common.h" 24 24 25 25 /***************************************************************************** ··· 27 27 ****************************************************************************/ 28 28 static struct map_desc orion_io_desc[] __initdata = { 29 29 { 30 30 - .virtual = ORION_REGS_BASE, 31 31 - .pfn = __phys_to_pfn(ORION_REGS_BASE), 30 30 + .virtual = ORION_REGS_VIRT_BASE, 31 31 + .pfn = __phys_to_pfn(ORION_REGS_PHYS_BASE), 32 32 .length = ORION_REGS_SIZE, 33 33 .type = MT_DEVICE 34 34 }, 35 35 { 36 36 - .virtual = ORION_PCIE_IO_BASE, 37 37 - .pfn = __phys_to_pfn(ORION_PCIE_IO_BASE), 36 36 + .virtual = ORION_PCIE_IO_VIRT_BASE, 37 37 + .pfn = __phys_to_pfn(ORION_PCIE_IO_PHYS_BASE), 38 38 .length = ORION_PCIE_IO_SIZE, 39 39 .type = MT_DEVICE 40 40 }, 41 41 { 42 42 - .virtual = ORION_PCI_IO_BASE, 43 43 - .pfn = __phys_to_pfn(ORION_PCI_IO_BASE), 42 42 + .virtual = ORION_PCI_IO_VIRT_BASE, 43 43 + .pfn = __phys_to_pfn(ORION_PCI_IO_PHYS_BASE), 44 44 .length = ORION_PCI_IO_SIZE, 45 45 .type = MT_DEVICE 46 46 }, 47 47 { 48 48 - .virtual = ORION_PCIE_WA_BASE, 49 49 - .pfn = __phys_to_pfn(ORION_PCIE_WA_BASE), 48 48 + .virtual = ORION_PCIE_WA_VIRT_BASE, 49 49 + .pfn = __phys_to_pfn(ORION_PCIE_WA_PHYS_BASE), 50 50 .length = ORION_PCIE_WA_SIZE, 51 51 .type = MT_DEVICE 52 52 }, ··· 63 63 64 64 static struct resource orion_uart_resources[] = { 65 65 { 66 66 - .start = UART0_BASE, 67 67 - .end = UART0_BASE + 0xff, 66 66 + .start = UART0_PHYS_BASE, 67 67 + .end = UART0_PHYS_BASE + 0xff, 68 68 .flags = IORESOURCE_MEM, 69 69 }, 70 70 { ··· 73 73 .flags = IORESOURCE_IRQ, 74 74 }, 75 75 { 76 76 - .start = UART1_BASE, 77 77 - .end = UART1_BASE + 0xff, 76 76 + .start = UART1_PHYS_BASE, 77 77 + .end = UART1_PHYS_BASE + 0xff, 78 78 .flags = IORESOURCE_MEM, 79 79 }, 80 80 { ··· 86 86 87 87 static struct plat_serial8250_port orion_uart_data[] = { 88 88 { 89 89 - .mapbase = UART0_BASE, 90 90 - .membase = (char *)UART0_BASE, 89 89 + .mapbase = UART0_PHYS_BASE, 90 90 + .membase = (char *)UART0_VIRT_BASE, 91 91 .irq = IRQ_ORION_UART0, 92 92 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, 93 93 .iotype = UPIO_MEM, ··· 95 95 .uartclk = ORION_TCLK, 96 96 }, 97 97 { 98 98 - .mapbase = UART1_BASE, 99 99 - .membase = (char *)UART1_BASE, 98 98 + .mapbase = UART1_PHYS_BASE, 99 99 + .membase = (char *)UART1_VIRT_BASE, 100 100 .irq = IRQ_ORION_UART1, 101 101 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, 102 102 .iotype = UPIO_MEM, ··· 122 122 123 123 static struct resource orion_ehci0_resources[] = { 124 124 { 125 125 - .start = ORION_USB0_REG_BASE, 126 126 - .end = ORION_USB0_REG_BASE + SZ_4K, 125 125 + .start = ORION_USB0_PHYS_BASE, 126 126 + .end = ORION_USB0_PHYS_BASE + SZ_4K, 127 127 .flags = IORESOURCE_MEM, 128 128 }, 129 129 { ··· 135 135 136 136 static struct resource orion_ehci1_resources[] = { 137 137 { 138 138 - .start = ORION_USB1_REG_BASE, 139 139 - .end = ORION_USB1_REG_BASE + SZ_4K, 138 138 + .start = ORION_USB1_PHYS_BASE, 139 139 + .end = ORION_USB1_PHYS_BASE + SZ_4K, 140 140 .flags = IORESOURCE_MEM, 141 141 }, 142 142 { ··· 177 177 178 178 static struct resource orion_eth_shared_resources[] = { 179 179 { 180 180 - .start = ORION_ETH_REG_BASE, 181 181 - .end = ORION_ETH_REG_BASE + 0xffff, 180 180 + .start = ORION_ETH_PHYS_BASE, 181 181 + .end = ORION_ETH_PHYS_BASE + 0xffff, 182 182 .flags = IORESOURCE_MEM, 183 183 }, 184 184 }; ··· 227 227 static struct resource orion_i2c_resources[] = { 228 228 { 229 229 .name = "i2c base", 230 230 - .start = I2C_BASE, 231 231 - .end = I2C_BASE + 0x20 -1, 230 230 + .start = I2C_PHYS_BASE, 231 231 + .end = I2C_PHYS_BASE + 0x20 -1, 232 232 .flags = IORESOURCE_MEM, 233 233 }, 234 234 { ··· 248 248 .platform_data = &orion_i2c_pdata, 249 249 }, 250 250 }; 251 251 + 252 252 + /***************************************************************************** 253 253 + * Sata port 254 254 + ****************************************************************************/ 255 255 + static struct resource orion_sata_resources[] = { 256 256 + { 257 257 + .name = "sata base", 258 258 + .start = ORION_SATA_PHYS_BASE, 259 259 + .end = ORION_SATA_PHYS_BASE + 0x5000 - 1, 260 260 + .flags = IORESOURCE_MEM, 261 261 + }, 262 262 + { 263 263 + .name = "sata irq", 264 264 + .start = IRQ_ORION_SATA, 265 265 + .end = IRQ_ORION_SATA, 266 266 + .flags = IORESOURCE_IRQ, 267 267 + }, 268 268 + }; 269 269 + 270 270 + static struct platform_device orion_sata = { 271 271 + .name = "sata_mv", 272 272 + .id = 0, 273 273 + .dev = { 274 274 + .coherent_dma_mask = 0xffffffff, 275 275 + }, 276 276 + .num_resources = ARRAY_SIZE(orion_sata_resources), 277 277 + .resource = orion_sata_resources, 278 278 + }; 279 279 + 280 280 + void __init orion_sata_init(struct mv_sata_platform_data *sata_data) 281 281 + { 282 282 + orion_sata.dev.platform_data = sata_data; 283 283 + platform_device_register(&orion_sata); 284 284 + } 251 285 252 286 /***************************************************************************** 253 287 * General

+8

arch/arm/mach-orion/common.h

reviewed

··· 75 75 76 76 void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data); 77 77 78 78 + /* 79 79 + * Orion Sata platform_data, used by machine-setup 80 80 + */ 81 81 + 82 82 + struct mv_sata_platform_data; 83 83 + 84 84 + void __init orion_sata_init(struct mv_sata_platform_data *sata_data); 85 85 + 78 86 #endif /* __ARCH_ORION_COMMON_H__ */

+2 -2

arch/arm/mach-orion/db88f5281-setup.c

reviewed

··· 354 354 355 355 MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board") 356 356 /* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */ 357 357 - .phys_io = ORION_REGS_BASE, 358 358 - .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xfffc, 357 357 + .phys_io = ORION_REGS_PHYS_BASE, 358 358 + .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xfffc, 359 359 .boot_params = 0x00000100, 360 360 .init_machine = db88f5281_init, 361 361 .map_io = orion_map_io,

+4 -4

arch/arm/mach-orion/dns323-setup.c

reviewed

··· 259 259 * 260 260 * Open a special address decode windows for the PCIE WA. 261 261 */ 262 262 - orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE); 263 263 - orion_write(ORION_REGS_BASE | 0x20070, 262 262 + orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); 263 263 + orion_write(ORION_REGS_VIRT_BASE | 0x20070, 264 264 (0x7941 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); 265 265 266 266 /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */ ··· 312 312 /* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */ 313 313 MACHINE_START(DNS323, "D-Link DNS-323") 314 314 /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */ 315 315 - .phys_io = ORION_REGS_BASE, 316 316 - .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC, 315 315 + .phys_io = ORION_REGS_PHYS_BASE, 316 316 + .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, 317 317 .boot_params = 0x00000100, 318 318 .init_machine = dns323_init, 319 319 .map_io = orion_map_io,

+13 -4

arch/arm/mach-orion/kurobox_pro-setup.c

reviewed

··· 17 17 #include <linux/mtd/nand.h> 18 18 #include <linux/mv643xx_eth.h> 19 19 #include <linux/i2c.h> 20 20 + #include <linux/ata_platform.h> 20 21 #include <asm/mach-types.h> 21 22 #include <asm/gpio.h> 22 23 #include <asm/mach/arch.h> ··· 168 167 }; 169 168 170 169 /***************************************************************************** 170 170 + * SATA 171 171 + ****************************************************************************/ 172 172 + static struct mv_sata_platform_data kurobox_pro_sata_data = { 173 173 + .n_ports = 2, 174 174 + }; 175 175 + 176 176 + /***************************************************************************** 171 177 * General Setup 172 178 ****************************************************************************/ 173 179 ··· 200 192 /* 201 193 * Open a special address decode windows for the PCIE WA. 202 194 */ 203 203 - orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE); 204 204 - orion_write(ORION_REGS_BASE | 0x20070, (0x7941 | 195 195 + orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); 196 196 + orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 | 205 197 (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); 206 198 207 199 /* ··· 228 220 platform_add_devices(kurobox_pro_devices, ARRAY_SIZE(kurobox_pro_devices)); 229 221 i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1); 230 222 orion_eth_init(&kurobox_pro_eth_data); 223 223 + orion_sata_init(&kurobox_pro_sata_data); 231 224 } 232 225 233 226 MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro") 234 227 /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */ 235 235 - .phys_io = ORION_REGS_BASE, 236 236 - .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC, 228 228 + .phys_io = ORION_REGS_PHYS_BASE, 229 229 + .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, 237 230 .boot_params = 0x00000100, 238 231 .init_machine = kurobox_pro_init, 239 232 .map_io = orion_map_io,

+5 -5

arch/arm/mach-orion/pci.c

reviewed

··· 156 156 orion_pcie_id(&dev, &rev); 157 157 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { 158 158 /* extended register space */ 159 159 - pcie_addr = ORION_PCIE_WA_BASE; 159 159 + pcie_addr = ORION_PCIE_WA_VIRT_BASE; 160 160 pcie_addr |= PCIE_CONF_BUS(bus->number) | 161 161 PCIE_CONF_DEV(PCI_SLOT(devfn)) | 162 162 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | ··· 241 241 */ 242 242 res[0].name = "PCI-EX I/O Space"; 243 243 res[0].flags = IORESOURCE_IO; 244 244 - res[0].start = ORION_PCIE_IO_REMAP; 244 244 + res[0].start = ORION_PCIE_IO_BUS_BASE; 245 245 res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1; 246 246 if (request_resource(&ioport_resource, &res[0])) 247 247 panic("Request PCIE IO resource failed\n"); ··· 252 252 */ 253 253 res[1].name = "PCI-EX Memory Space"; 254 254 res[1].flags = IORESOURCE_MEM; 255 255 - res[1].start = ORION_PCIE_MEM_BASE; 255 255 + res[1].start = ORION_PCIE_MEM_PHYS_BASE; 256 256 res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1; 257 257 if (request_resource(&iomem_resource, &res[1])) 258 258 panic("Request PCIE Memory resource failed\n"); ··· 477 477 */ 478 478 res[0].name = "PCI I/O Space"; 479 479 res[0].flags = IORESOURCE_IO; 480 480 - res[0].start = ORION_PCI_IO_REMAP; 480 480 + res[0].start = ORION_PCI_IO_BUS_BASE; 481 481 res[0].end = res[0].start + ORION_PCI_IO_SIZE - 1; 482 482 if (request_resource(&ioport_resource, &res[0])) 483 483 panic("Request PCI IO resource failed\n"); ··· 488 488 */ 489 489 res[1].name = "PCI Memory Space"; 490 490 res[1].flags = IORESOURCE_MEM; 491 491 - res[1].start = ORION_PCI_MEM_BASE; 491 491 + res[1].start = ORION_PCI_MEM_PHYS_BASE; 492 492 res[1].end = res[1].start + ORION_PCI_MEM_SIZE - 1; 493 493 if (request_resource(&iomem_resource, &res[1])) 494 494 panic("Request PCI Memory resource failed\n");

+13 -4

arch/arm/mach-orion/rd88f5182-setup.c

reviewed

··· 17 17 #include <linux/irq.h> 18 18 #include <linux/mtd/physmap.h> 19 19 #include <linux/mv643xx_eth.h> 20 20 + #include <linux/ata_platform.h> 20 21 #include <linux/i2c.h> 21 22 #include <asm/mach-types.h> 22 23 #include <asm/gpio.h> ··· 231 230 }; 232 231 233 232 /***************************************************************************** 233 233 + * Sata 234 234 + ****************************************************************************/ 235 235 + static struct mv_sata_platform_data rd88f5182_sata_data = { 236 236 + .n_ports = 2, 237 237 + }; 238 238 + 239 239 + /***************************************************************************** 234 240 * General Setup 235 241 ****************************************************************************/ 236 242 ··· 263 255 /* 264 256 * Open a special address decode windows for the PCIE WA. 265 257 */ 266 266 - orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE); 267 267 - orion_write(ORION_REGS_BASE | 0x20070, (0x7941 | 258 258 + orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); 259 259 + orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 | 268 260 (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); 269 261 270 262 /* ··· 300 292 platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices)); 301 293 i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1); 302 294 orion_eth_init(&rd88f5182_eth_data); 295 295 + orion_sata_init(&rd88f5182_sata_data); 303 296 } 304 297 305 298 MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design") 306 299 /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */ 307 307 - .phys_io = ORION_REGS_BASE, 308 308 - .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC, 300 300 + .phys_io = ORION_REGS_PHYS_BASE, 301 301 + .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, 309 302 .boot_params = 0x00000100, 310 303 .init_machine = rd88f5182_init, 311 304 .map_io = orion_map_io,

+15 -5

arch/arm/mach-orion/ts209-setup.c

reviewed

··· 21 21 #include <linux/input.h> 22 22 #include <linux/i2c.h> 23 23 #include <linux/serial_reg.h> 24 24 + #include <linux/ata_platform.h> 24 25 #include <asm/mach-types.h> 25 26 #include <asm/gpio.h> 26 27 #include <asm/mach/arch.h> ··· 233 232 }; 234 233 235 234 /***************************************************************************** 235 235 + * SATA 236 236 + ****************************************************************************/ 237 237 + static struct mv_sata_platform_data qnap_ts209_sata_data = { 238 238 + .n_ports = 2, 239 239 + }; 240 240 + 241 241 + /***************************************************************************** 242 242 + 236 243 * General Setup 237 244 ****************************************************************************/ 238 245 ··· 253 244 * QNAP TS-[12]09 specific power off method via UART1-attached PIC 254 245 */ 255 246 256 256 - #define UART1_REG(x) (UART1_BASE + ((UART_##x) << 2)) 247 247 + #define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2)) 257 248 258 249 static void qnap_ts209_power_off(void) 259 250 { ··· 291 282 /* 292 283 * Open a special address decode windows for the PCIE WA. 293 284 */ 294 294 - orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE); 295 295 - orion_write(ORION_REGS_BASE | 0x20070, (0x7941 | 285 285 + orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); 286 286 + orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 | 296 287 (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); 297 288 298 289 /* ··· 330 321 ARRAY_SIZE(qnap_ts209_devices)); 331 322 i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1); 332 323 orion_eth_init(&qnap_ts209_eth_data); 324 324 + orion_sata_init(&qnap_ts209_sata_data); 333 325 } 334 326 335 327 MACHINE_START(TS209, "QNAP TS-109/TS-209") 336 328 /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */ 337 337 - .phys_io = ORION_REGS_BASE, 338 338 - .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC, 329 329 + .phys_io = ORION_REGS_PHYS_BASE, 330 330 + .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, 339 331 .boot_params = 0x00000100, 340 332 .init_machine = qnap_ts209_init, 341 333 .map_io = orion_map_io,

+8 -2

arch/arm/mach-pxa/pxa3xx.c

reviewed

··· 266 266 267 267 AD2D0ER = 0; 268 268 AD2D1ER = 0; 269 269 - 270 270 - printk("PM: AD2D0SR=%08x ASCR=%08x\n", AD2D0SR, ASCR); 271 269 } 272 270 273 271 /* ··· 513 515 int i, ret = 0; 514 516 515 517 if (cpu_is_pxa3xx()) { 518 518 + /* 519 519 + * clear RDH bit every time after reset 520 520 + * 521 521 + * Note: the last 3 bits DxS are write-1-to-clear so carefully 522 522 + * preserve them here in case they will be referenced later 523 523 + */ 524 524 + ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); 525 525 + 516 526 clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks)); 517 527 518 528 if ((ret = pxa_init_dma(32)))

+1

arch/arm/plat-omap/Makefile

reviewed

··· 19 19 obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o 20 20 obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o 21 21 obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o 22 22 + obj-$(CONFIG_I2C_OMAP) += i2c.o

+804 -40

arch/arm/plat-omap/dma.c

reviewed

··· 6 6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com> 7 7 * Graphics DMA and LCD DMA graphics tranformations 8 8 * by Imre Deak <imre.deak@nokia.com> 9 9 - * OMAP2 support Copyright (C) 2004-2005 Texas Instruments, Inc. 9 9 + * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc. 10 10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com> 11 11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc. 12 12 * ··· 33 33 34 34 #include <asm/arch/tc.h> 35 35 36 36 - #define DEBUG_PRINTS 37 37 - #undef DEBUG_PRINTS 38 38 - #ifdef DEBUG_PRINTS 39 39 - #define debug_printk(x) printk x 40 40 - #else 41 41 - #define debug_printk(x) 36 36 + #undef DEBUG 37 37 + 38 38 + #ifndef CONFIG_ARCH_OMAP1 39 39 + enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED, 40 40 + DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED 41 41 + }; 42 42 + 43 43 + enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED }; 42 44 #endif 43 45 44 46 #define OMAP_DMA_ACTIVE 0x01 ··· 59 57 const char *dev_name; 60 58 void (* callback)(int lch, u16 ch_status, void *data); 61 59 void *data; 60 60 + 61 61 + #ifndef CONFIG_ARCH_OMAP1 62 62 + /* required for Dynamic chaining */ 63 63 + int prev_linked_ch; 64 64 + int next_linked_ch; 65 65 + int state; 66 66 + int chain_id; 67 67 + 68 68 + int status; 69 69 + #endif 62 70 long flags; 63 71 }; 64 72 73 73 + #ifndef CONFIG_ARCH_OMAP1 74 74 + struct dma_link_info { 75 75 + int *linked_dmach_q; 76 76 + int no_of_lchs_linked; 77 77 + 78 78 + int q_count; 79 79 + int q_tail; 80 80 + int q_head; 81 81 + 82 82 + int chain_state; 83 83 + int chain_mode; 84 84 + 85 85 + }; 86 86 + 87 87 + static struct dma_link_info dma_linked_lch[OMAP_LOGICAL_DMA_CH_COUNT]; 88 88 + 89 89 + /* Chain handling macros */ 90 90 + #define OMAP_DMA_CHAIN_QINIT(chain_id) \ 91 91 + do { \ 92 92 + dma_linked_lch[chain_id].q_head = \ 93 93 + dma_linked_lch[chain_id].q_tail = \ 94 94 + dma_linked_lch[chain_id].q_count = 0; \ 95 95 + } while (0) 96 96 + #define OMAP_DMA_CHAIN_QFULL(chain_id) \ 97 97 + (dma_linked_lch[chain_id].no_of_lchs_linked == \ 98 98 + dma_linked_lch[chain_id].q_count) 99 99 + #define OMAP_DMA_CHAIN_QLAST(chain_id) \ 100 100 + do { \ 101 101 + ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \ 102 102 + dma_linked_lch[chain_id].q_count) \ 103 103 + } while (0) 104 104 + #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \ 105 105 + (0 == dma_linked_lch[chain_id].q_count) 106 106 + #define __OMAP_DMA_CHAIN_INCQ(end) \ 107 107 + ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked) 108 108 + #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \ 109 109 + do { \ 110 110 + __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \ 111 111 + dma_linked_lch[chain_id].q_count--; \ 112 112 + } while (0) 113 113 + 114 114 + #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \ 115 115 + do { \ 116 116 + __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \ 117 117 + dma_linked_lch[chain_id].q_count++; \ 118 118 + } while (0) 119 119 + #endif 65 120 static int dma_chan_count; 66 121 67 122 static spinlock_t dma_chan_lock; ··· 131 72 INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13, 132 73 INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD 133 74 }; 75 75 + 76 76 + static inline void disable_lnk(int lch); 77 77 + static void omap_disable_channel_irq(int lch); 78 78 + static inline void omap_enable_channel_irq(int lch); 134 79 135 80 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \ 136 81 __FUNCTION__); ··· 211 148 omap_writel(l, reg); 212 149 } 213 150 214 214 - if (cpu_is_omap24xx()) { 151 151 + if (cpu_class_is_omap2()) { 215 152 if (priority) 216 153 OMAP_DMA_CCR_REG(lch) |= (1 << 6); 217 154 else ··· 236 173 OMAP1_DMA_CCR2_REG(lch) |= 1 << 2; 237 174 } 238 175 239 239 - if (cpu_is_omap24xx() && dma_trigger) { 176 176 + if (cpu_class_is_omap2() && dma_trigger) { 240 177 u32 val = OMAP_DMA_CCR_REG(lch); 241 178 242 179 val &= ~(3 << 19); ··· 276 213 277 214 BUG_ON(omap_dma_in_1510_mode()); 278 215 279 279 - if (cpu_is_omap24xx()) { 216 216 + if (cpu_class_is_omap2()) { 280 217 REVISIT_24XX(); 281 218 return; 282 219 } ··· 308 245 309 246 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode) 310 247 { 311 311 - if (cpu_is_omap24xx()) { 248 248 + if (cpu_class_is_omap2()) { 312 249 OMAP_DMA_CSDP_REG(lch) &= ~(0x3 << 16); 313 250 OMAP_DMA_CSDP_REG(lch) |= (mode << 16); 314 251 } ··· 332 269 OMAP1_DMA_CSSA_L_REG(lch) = src_start; 333 270 } 334 271 335 335 - if (cpu_is_omap24xx()) 272 272 + if (cpu_class_is_omap2()) 336 273 OMAP2_DMA_CSSA_REG(lch) = src_start; 337 274 338 275 OMAP_DMA_CSEI_REG(lch) = src_ei; ··· 352 289 omap_set_dma_dest_params(lch, params->dst_port, 353 290 params->dst_amode, params->dst_start, 354 291 params->dst_ei, params->dst_fi); 292 292 + if (params->read_prio || params->write_prio) 293 293 + omap_dma_set_prio_lch(lch, params->read_prio, 294 294 + params->write_prio); 355 295 } 356 296 357 297 void omap_set_dma_src_index(int lch, int eidx, int fidx) 358 298 { 359 359 - if (cpu_is_omap24xx()) { 299 299 + if (cpu_class_is_omap2()) { 360 300 REVISIT_24XX(); 361 301 return; 362 302 } ··· 383 317 case OMAP_DMA_DATA_BURST_DIS: 384 318 break; 385 319 case OMAP_DMA_DATA_BURST_4: 386 386 - if (cpu_is_omap24xx()) 320 320 + if (cpu_class_is_omap2()) 387 321 burst = 0x1; 388 322 else 389 323 burst = 0x2; 390 324 break; 391 325 case OMAP_DMA_DATA_BURST_8: 392 392 - if (cpu_is_omap24xx()) { 326 326 + if (cpu_class_is_omap2()) { 393 327 burst = 0x2; 394 328 break; 395 329 } ··· 398 332 * fall through 399 333 */ 400 334 case OMAP_DMA_DATA_BURST_16: 401 401 - if (cpu_is_omap24xx()) { 335 335 + if (cpu_class_is_omap2()) { 402 336 burst = 0x3; 403 337 break; 404 338 } ··· 429 363 OMAP1_DMA_CDSA_L_REG(lch) = dest_start; 430 364 } 431 365 432 432 - if (cpu_is_omap24xx()) 366 366 + if (cpu_class_is_omap2()) 433 367 OMAP2_DMA_CDSA_REG(lch) = dest_start; 434 368 435 369 OMAP_DMA_CDEI_REG(lch) = dst_ei; ··· 438 372 439 373 void omap_set_dma_dest_index(int lch, int eidx, int fidx) 440 374 { 441 441 - if (cpu_is_omap24xx()) { 375 375 + if (cpu_class_is_omap2()) { 442 376 REVISIT_24XX(); 443 377 return; 444 378 } ··· 462 396 case OMAP_DMA_DATA_BURST_DIS: 463 397 break; 464 398 case OMAP_DMA_DATA_BURST_4: 465 465 - if (cpu_is_omap24xx()) 399 399 + if (cpu_class_is_omap2()) 466 400 burst = 0x1; 467 401 else 468 402 burst = 0x2; 469 403 break; 470 404 case OMAP_DMA_DATA_BURST_8: 471 471 - if (cpu_is_omap24xx()) 405 405 + if (cpu_class_is_omap2()) 472 406 burst = 0x2; 473 407 else 474 408 burst = 0x3; 475 409 break; 476 410 case OMAP_DMA_DATA_BURST_16: 477 477 - if (cpu_is_omap24xx()) { 411 411 + if (cpu_class_is_omap2()) { 478 412 burst = 0x3; 479 413 break; 480 414 } ··· 496 430 /* Clear CSR */ 497 431 if (cpu_class_is_omap1()) 498 432 status = OMAP_DMA_CSR_REG(lch); 499 499 - else if (cpu_is_omap24xx()) 433 433 + else if (cpu_class_is_omap2()) 500 434 OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK; 501 435 502 436 /* Enable some nice interrupts. */ ··· 507 441 508 442 static void omap_disable_channel_irq(int lch) 509 443 { 510 510 - if (cpu_is_omap24xx()) 444 444 + if (cpu_class_is_omap2()) 511 445 OMAP_DMA_CICR_REG(lch) = 0; 512 446 } 513 447 ··· 530 464 if (dma_chan[lch].next_lch != -1) 531 465 OMAP_DMA_CLNK_CTRL_REG(lch) = 532 466 dma_chan[lch].next_lch | (1 << 15); 467 467 + 468 468 + #ifndef CONFIG_ARCH_OMAP1 469 469 + if (dma_chan[lch].next_linked_ch != -1) 470 470 + OMAP_DMA_CLNK_CTRL_REG(lch) = 471 471 + dma_chan[lch].next_linked_ch | (1 << 15); 472 472 + #endif 533 473 } 534 474 535 475 static inline void disable_lnk(int lch) ··· 547 475 OMAP_DMA_CLNK_CTRL_REG(lch) |= 1 << 14; 548 476 } 549 477 550 550 - if (cpu_is_omap24xx()) { 478 478 + if (cpu_class_is_omap2()) { 551 479 omap_disable_channel_irq(lch); 552 480 /* Clear the ENABLE_LNK bit */ 553 481 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 15); ··· 560 488 { 561 489 u32 val; 562 490 563 563 - if (!cpu_is_omap24xx()) 491 491 + if (!cpu_class_is_omap2()) 564 492 return; 565 493 566 494 val = omap_readl(OMAP_DMA4_IRQENABLE_L0); ··· 594 522 if (cpu_class_is_omap1()) 595 523 clear_lch_regs(free_ch); 596 524 597 597 - if (cpu_is_omap24xx()) 525 525 + if (cpu_class_is_omap2()) 598 526 omap_clear_dma(free_ch); 599 527 600 528 spin_unlock_irqrestore(&dma_chan_lock, flags); ··· 602 530 chan->dev_name = dev_name; 603 531 chan->callback = callback; 604 532 chan->data = data; 533 533 + #ifndef CONFIG_ARCH_OMAP1 534 534 + chan->chain_id = -1; 535 535 + #endif 605 536 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ; 606 537 607 538 if (cpu_class_is_omap1()) 608 539 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ; 609 609 - else if (cpu_is_omap24xx()) 540 540 + else if (cpu_class_is_omap2()) 610 541 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ | 611 542 OMAP2_DMA_TRANS_ERR_IRQ; 612 543 ··· 626 551 OMAP_DMA_CCR_REG(free_ch) = dev_id; 627 552 } 628 553 629 629 - if (cpu_is_omap24xx()) { 554 554 + if (cpu_class_is_omap2()) { 630 555 omap2_enable_irq_lch(free_ch); 631 556 632 557 omap_enable_channel_irq(free_ch); ··· 663 588 OMAP_DMA_CCR_REG(lch) = 0; 664 589 } 665 590 666 666 - if (cpu_is_omap24xx()) { 591 591 + if (cpu_class_is_omap2()) { 667 592 u32 val; 668 593 /* Disable interrupts */ 669 594 val = omap_readl(OMAP_DMA4_IRQENABLE_L0); ··· 683 608 } 684 609 } 685 610 611 611 + /** 612 612 + * @brief omap_dma_set_global_params : Set global priority settings for dma 613 613 + * 614 614 + * @param arb_rate 615 615 + * @param max_fifo_depth 616 616 + * @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM 617 617 + * DMA_THREAD_RESERVE_ONET 618 618 + * DMA_THREAD_RESERVE_TWOT 619 619 + * DMA_THREAD_RESERVE_THREET 620 620 + */ 621 621 + void 622 622 + omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams) 623 623 + { 624 624 + u32 reg; 625 625 + 626 626 + if (!cpu_class_is_omap2()) { 627 627 + printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __FUNCTION__); 628 628 + return; 629 629 + } 630 630 + 631 631 + if (arb_rate == 0) 632 632 + arb_rate = 1; 633 633 + 634 634 + reg = (arb_rate & 0xff) << 16; 635 635 + reg |= (0xff & max_fifo_depth); 636 636 + 637 637 + omap_writel(reg, OMAP_DMA4_GCR_REG); 638 638 + } 639 639 + EXPORT_SYMBOL(omap_dma_set_global_params); 640 640 + 641 641 + /** 642 642 + * @brief omap_dma_set_prio_lch : Set channel wise priority settings 643 643 + * 644 644 + * @param lch 645 645 + * @param read_prio - Read priority 646 646 + * @param write_prio - Write priority 647 647 + * Both of the above can be set with one of the following values : 648 648 + * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW 649 649 + */ 650 650 + int 651 651 + omap_dma_set_prio_lch(int lch, unsigned char read_prio, 652 652 + unsigned char write_prio) 653 653 + { 654 654 + u32 w; 655 655 + 656 656 + if (unlikely((lch < 0 || lch >= OMAP_LOGICAL_DMA_CH_COUNT))) { 657 657 + printk(KERN_ERR "Invalid channel id\n"); 658 658 + return -EINVAL; 659 659 + } 660 660 + w = OMAP_DMA_CCR_REG(lch); 661 661 + w &= ~((1 << 6) | (1 << 26)); 662 662 + if (cpu_is_omap2430() || cpu_is_omap34xx()) 663 663 + w |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26); 664 664 + else 665 665 + w |= ((read_prio & 0x1) << 6); 666 666 + 667 667 + OMAP_DMA_CCR_REG(lch) = w; 668 668 + return 0; 669 669 + } 670 670 + EXPORT_SYMBOL(omap_dma_set_prio_lch); 671 671 + 686 672 /* 687 673 * Clears any DMA state so the DMA engine is ready to restart with new buffers 688 674 * through omap_start_dma(). Any buffers in flight are discarded. ··· 762 626 status = OMAP_DMA_CSR_REG(lch); 763 627 } 764 628 765 765 - if (cpu_is_omap24xx()) { 629 629 + if (cpu_class_is_omap2()) { 766 630 int i; 767 767 - u32 lch_base = OMAP24XX_DMA_BASE + lch * 0x60 + 0x80; 631 631 + u32 lch_base = OMAP_DMA4_BASE + lch * 0x60 + 0x80; 768 632 for (i = 0; i < 0x44; i += 4) 769 633 omap_writel(0, lch_base + i); 770 634 } ··· 798 662 799 663 cur_lch = next_lch; 800 664 } while (next_lch != -1); 801 801 - } else if (cpu_is_omap24xx()) { 665 665 + } else if (cpu_class_is_omap2()) { 802 666 /* Errata: Need to write lch even if not using chaining */ 803 667 OMAP_DMA_CLNK_CTRL_REG(lch) = lch; 804 668 } ··· 889 753 offset = (dma_addr_t) (OMAP1_DMA_CSSA_L_REG(lch) | 890 754 (OMAP1_DMA_CSSA_U_REG(lch) << 16)); 891 755 892 892 - if (cpu_is_omap24xx()) 756 756 + if (cpu_class_is_omap2()) 893 757 offset = OMAP_DMA_CSAC_REG(lch); 894 758 895 759 return offset; ··· 911 775 offset = (dma_addr_t) (OMAP1_DMA_CDSA_L_REG(lch) | 912 776 (OMAP1_DMA_CDSA_U_REG(lch) << 16)); 913 777 914 914 - if (cpu_is_omap24xx()) 915 915 - offset = OMAP2_DMA_CDSA_REG(lch); 778 778 + if (cpu_class_is_omap2()) 779 779 + offset = OMAP_DMA_CDAC_REG(lch); 916 780 917 781 return offset; 918 782 } ··· 995 859 dma_chan[lch_head].next_lch = -1; 996 860 } 997 861 862 862 + #ifndef CONFIG_ARCH_OMAP1 863 863 + /* Create chain of DMA channesls */ 864 864 + static void create_dma_lch_chain(int lch_head, int lch_queue) 865 865 + { 866 866 + u32 w; 867 867 + 868 868 + /* Check if this is the first link in chain */ 869 869 + if (dma_chan[lch_head].next_linked_ch == -1) { 870 870 + dma_chan[lch_head].next_linked_ch = lch_queue; 871 871 + dma_chan[lch_head].prev_linked_ch = lch_queue; 872 872 + dma_chan[lch_queue].next_linked_ch = lch_head; 873 873 + dma_chan[lch_queue].prev_linked_ch = lch_head; 874 874 + } 875 875 + 876 876 + /* a link exists, link the new channel in circular chain */ 877 877 + else { 878 878 + dma_chan[lch_queue].next_linked_ch = 879 879 + dma_chan[lch_head].next_linked_ch; 880 880 + dma_chan[lch_queue].prev_linked_ch = lch_head; 881 881 + dma_chan[lch_head].next_linked_ch = lch_queue; 882 882 + dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch = 883 883 + lch_queue; 884 884 + } 885 885 + 886 886 + w = OMAP_DMA_CLNK_CTRL_REG(lch_head); 887 887 + w &= ~(0x0f); 888 888 + w |= lch_queue; 889 889 + OMAP_DMA_CLNK_CTRL_REG(lch_head) = w; 890 890 + 891 891 + w = OMAP_DMA_CLNK_CTRL_REG(lch_queue); 892 892 + w &= ~(0x0f); 893 893 + w |= (dma_chan[lch_queue].next_linked_ch); 894 894 + OMAP_DMA_CLNK_CTRL_REG(lch_queue) = w; 895 895 + } 896 896 + 897 897 + /** 898 898 + * @brief omap_request_dma_chain : Request a chain of DMA channels 899 899 + * 900 900 + * @param dev_id - Device id using the dma channel 901 901 + * @param dev_name - Device name 902 902 + * @param callback - Call back function 903 903 + * @chain_id - 904 904 + * @no_of_chans - Number of channels requested 905 905 + * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN 906 906 + * OMAP_DMA_DYNAMIC_CHAIN 907 907 + * @params - Channel parameters 908 908 + * 909 909 + * @return - Succes : 0 910 910 + * Failure: -EINVAL/-ENOMEM 911 911 + */ 912 912 + int omap_request_dma_chain(int dev_id, const char *dev_name, 913 913 + void (*callback) (int chain_id, u16 ch_status, 914 914 + void *data), 915 915 + int *chain_id, int no_of_chans, int chain_mode, 916 916 + struct omap_dma_channel_params params) 917 917 + { 918 918 + int *channels; 919 919 + int i, err; 920 920 + 921 921 + /* Is the chain mode valid ? */ 922 922 + if (chain_mode != OMAP_DMA_STATIC_CHAIN 923 923 + && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) { 924 924 + printk(KERN_ERR "Invalid chain mode requested\n"); 925 925 + return -EINVAL; 926 926 + } 927 927 + 928 928 + if (unlikely((no_of_chans < 1 929 929 + || no_of_chans > OMAP_LOGICAL_DMA_CH_COUNT))) { 930 930 + printk(KERN_ERR "Invalid Number of channels requested\n"); 931 931 + return -EINVAL; 932 932 + } 933 933 + 934 934 + /* Allocate a queue to maintain the status of the channels 935 935 + * in the chain */ 936 936 + channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL); 937 937 + if (channels == NULL) { 938 938 + printk(KERN_ERR "omap_dma: No memory for channel queue\n"); 939 939 + return -ENOMEM; 940 940 + } 941 941 + 942 942 + /* request and reserve DMA channels for the chain */ 943 943 + for (i = 0; i < no_of_chans; i++) { 944 944 + err = omap_request_dma(dev_id, dev_name, 945 945 + callback, 0, &channels[i]); 946 946 + if (err < 0) { 947 947 + int j; 948 948 + for (j = 0; j < i; j++) 949 949 + omap_free_dma(channels[j]); 950 950 + kfree(channels); 951 951 + printk(KERN_ERR "omap_dma: Request failed %d\n", err); 952 952 + return err; 953 953 + } 954 954 + dma_chan[channels[i]].next_linked_ch = -1; 955 955 + dma_chan[channels[i]].prev_linked_ch = -1; 956 956 + dma_chan[channels[i]].state = DMA_CH_NOTSTARTED; 957 957 + 958 958 + /* 959 959 + * Allowing client drivers to set common parameters now, 960 960 + * so that later only relevant (src_start, dest_start 961 961 + * and element count) can be set 962 962 + */ 963 963 + omap_set_dma_params(channels[i], &params); 964 964 + } 965 965 + 966 966 + *chain_id = channels[0]; 967 967 + dma_linked_lch[*chain_id].linked_dmach_q = channels; 968 968 + dma_linked_lch[*chain_id].chain_mode = chain_mode; 969 969 + dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED; 970 970 + dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans; 971 971 + 972 972 + for (i = 0; i < no_of_chans; i++) 973 973 + dma_chan[channels[i]].chain_id = *chain_id; 974 974 + 975 975 + /* Reset the Queue pointers */ 976 976 + OMAP_DMA_CHAIN_QINIT(*chain_id); 977 977 + 978 978 + /* Set up the chain */ 979 979 + if (no_of_chans == 1) 980 980 + create_dma_lch_chain(channels[0], channels[0]); 981 981 + else { 982 982 + for (i = 0; i < (no_of_chans - 1); i++) 983 983 + create_dma_lch_chain(channels[i], channels[i + 1]); 984 984 + } 985 985 + return 0; 986 986 + } 987 987 + EXPORT_SYMBOL(omap_request_dma_chain); 988 988 + 989 989 + /** 990 990 + * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the 991 991 + * params after setting it. Dont do this while dma is running!! 992 992 + * 993 993 + * @param chain_id - Chained logical channel id. 994 994 + * @param params 995 995 + * 996 996 + * @return - Success : 0 997 997 + * Failure : -EINVAL 998 998 + */ 999 999 + int omap_modify_dma_chain_params(int chain_id, 1000 1000 + struct omap_dma_channel_params params) 1001 1001 + { 1002 1002 + int *channels; 1003 1003 + u32 i; 1004 1004 + 1005 1005 + /* Check for input params */ 1006 1006 + if (unlikely((chain_id < 0 1007 1007 + || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1008 1008 + printk(KERN_ERR "Invalid chain id\n"); 1009 1009 + return -EINVAL; 1010 1010 + } 1011 1011 + 1012 1012 + /* Check if the chain exists */ 1013 1013 + if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { 1014 1014 + printk(KERN_ERR "Chain doesn't exists\n"); 1015 1015 + return -EINVAL; 1016 1016 + } 1017 1017 + channels = dma_linked_lch[chain_id].linked_dmach_q; 1018 1018 + 1019 1019 + for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) { 1020 1020 + /* 1021 1021 + * Allowing client drivers to set common parameters now, 1022 1022 + * so that later only relevant (src_start, dest_start 1023 1023 + * and element count) can be set 1024 1024 + */ 1025 1025 + omap_set_dma_params(channels[i], &params); 1026 1026 + } 1027 1027 + return 0; 1028 1028 + } 1029 1029 + EXPORT_SYMBOL(omap_modify_dma_chain_params); 1030 1030 + 1031 1031 + /** 1032 1032 + * @brief omap_free_dma_chain - Free all the logical channels in a chain. 1033 1033 + * 1034 1034 + * @param chain_id 1035 1035 + * 1036 1036 + * @return - Success : 0 1037 1037 + * Failure : -EINVAL 1038 1038 + */ 1039 1039 + int omap_free_dma_chain(int chain_id) 1040 1040 + { 1041 1041 + int *channels; 1042 1042 + u32 i; 1043 1043 + 1044 1044 + /* Check for input params */ 1045 1045 + if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1046 1046 + printk(KERN_ERR "Invalid chain id\n"); 1047 1047 + return -EINVAL; 1048 1048 + } 1049 1049 + 1050 1050 + /* Check if the chain exists */ 1051 1051 + if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { 1052 1052 + printk(KERN_ERR "Chain doesn't exists\n"); 1053 1053 + return -EINVAL; 1054 1054 + } 1055 1055 + 1056 1056 + channels = dma_linked_lch[chain_id].linked_dmach_q; 1057 1057 + for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) { 1058 1058 + dma_chan[channels[i]].next_linked_ch = -1; 1059 1059 + dma_chan[channels[i]].prev_linked_ch = -1; 1060 1060 + dma_chan[channels[i]].chain_id = -1; 1061 1061 + dma_chan[channels[i]].state = DMA_CH_NOTSTARTED; 1062 1062 + omap_free_dma(channels[i]); 1063 1063 + } 1064 1064 + 1065 1065 + kfree(channels); 1066 1066 + 1067 1067 + dma_linked_lch[chain_id].linked_dmach_q = NULL; 1068 1068 + dma_linked_lch[chain_id].chain_mode = -1; 1069 1069 + dma_linked_lch[chain_id].chain_state = -1; 1070 1070 + return (0); 1071 1071 + } 1072 1072 + EXPORT_SYMBOL(omap_free_dma_chain); 1073 1073 + 1074 1074 + /** 1075 1075 + * @brief omap_dma_chain_status - Check if the chain is in 1076 1076 + * active / inactive state. 1077 1077 + * @param chain_id 1078 1078 + * 1079 1079 + * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE 1080 1080 + * Failure : -EINVAL 1081 1081 + */ 1082 1082 + int omap_dma_chain_status(int chain_id) 1083 1083 + { 1084 1084 + /* Check for input params */ 1085 1085 + if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1086 1086 + printk(KERN_ERR "Invalid chain id\n"); 1087 1087 + return -EINVAL; 1088 1088 + } 1089 1089 + 1090 1090 + /* Check if the chain exists */ 1091 1091 + if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { 1092 1092 + printk(KERN_ERR "Chain doesn't exists\n"); 1093 1093 + return -EINVAL; 1094 1094 + } 1095 1095 + pr_debug("CHAINID=%d, qcnt=%d\n", chain_id, 1096 1096 + dma_linked_lch[chain_id].q_count); 1097 1097 + 1098 1098 + if (OMAP_DMA_CHAIN_QEMPTY(chain_id)) 1099 1099 + return OMAP_DMA_CHAIN_INACTIVE; 1100 1100 + return OMAP_DMA_CHAIN_ACTIVE; 1101 1101 + } 1102 1102 + EXPORT_SYMBOL(omap_dma_chain_status); 1103 1103 + 1104 1104 + /** 1105 1105 + * @brief omap_dma_chain_a_transfer - Get a free channel from a chain, 1106 1106 + * set the params and start the transfer. 1107 1107 + * 1108 1108 + * @param chain_id 1109 1109 + * @param src_start - buffer start address 1110 1110 + * @param dest_start - Dest address 1111 1111 + * @param elem_count 1112 1112 + * @param frame_count 1113 1113 + * @param callbk_data - channel callback parameter data. 1114 1114 + * 1115 1115 + * @return - Success : start_dma status 1116 1116 + * Failure: -EINVAL/-EBUSY 1117 1117 + */ 1118 1118 + int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start, 1119 1119 + int elem_count, int frame_count, void *callbk_data) 1120 1120 + { 1121 1121 + int *channels; 1122 1122 + u32 w, lch; 1123 1123 + int start_dma = 0; 1124 1124 + 1125 1125 + /* if buffer size is less than 1 then there is 1126 1126 + * no use of starting the chain */ 1127 1127 + if (elem_count < 1) { 1128 1128 + printk(KERN_ERR "Invalid buffer size\n"); 1129 1129 + return -EINVAL; 1130 1130 + } 1131 1131 + 1132 1132 + /* Check for input params */ 1133 1133 + if (unlikely((chain_id < 0 1134 1134 + || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1135 1135 + printk(KERN_ERR "Invalid chain id\n"); 1136 1136 + return -EINVAL; 1137 1137 + } 1138 1138 + 1139 1139 + /* Check if the chain exists */ 1140 1140 + if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { 1141 1141 + printk(KERN_ERR "Chain doesn't exist\n"); 1142 1142 + return -EINVAL; 1143 1143 + } 1144 1144 + 1145 1145 + /* Check if all the channels in chain are in use */ 1146 1146 + if (OMAP_DMA_CHAIN_QFULL(chain_id)) 1147 1147 + return -EBUSY; 1148 1148 + 1149 1149 + /* Frame count may be negative in case of indexed transfers */ 1150 1150 + channels = dma_linked_lch[chain_id].linked_dmach_q; 1151 1151 + 1152 1152 + /* Get a free channel */ 1153 1153 + lch = channels[dma_linked_lch[chain_id].q_tail]; 1154 1154 + 1155 1155 + /* Store the callback data */ 1156 1156 + dma_chan[lch].data = callbk_data; 1157 1157 + 1158 1158 + /* Increment the q_tail */ 1159 1159 + OMAP_DMA_CHAIN_INCQTAIL(chain_id); 1160 1160 + 1161 1161 + /* Set the params to the free channel */ 1162 1162 + if (src_start != 0) 1163 1163 + OMAP2_DMA_CSSA_REG(lch) = src_start; 1164 1164 + if (dest_start != 0) 1165 1165 + OMAP2_DMA_CDSA_REG(lch) = dest_start; 1166 1166 + 1167 1167 + /* Write the buffer size */ 1168 1168 + OMAP_DMA_CEN_REG(lch) = elem_count; 1169 1169 + OMAP_DMA_CFN_REG(lch) = frame_count; 1170 1170 + 1171 1171 + /* If the chain is dynamically linked, 1172 1172 + * then we may have to start the chain if its not active */ 1173 1173 + if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) { 1174 1174 + 1175 1175 + /* In Dynamic chain, if the chain is not started, 1176 1176 + * queue the channel */ 1177 1177 + if (dma_linked_lch[chain_id].chain_state == 1178 1178 + DMA_CHAIN_NOTSTARTED) { 1179 1179 + /* Enable the link in previous channel */ 1180 1180 + if (dma_chan[dma_chan[lch].prev_linked_ch].state == 1181 1181 + DMA_CH_QUEUED) 1182 1182 + enable_lnk(dma_chan[lch].prev_linked_ch); 1183 1183 + dma_chan[lch].state = DMA_CH_QUEUED; 1184 1184 + } 1185 1185 + 1186 1186 + /* Chain is already started, make sure its active, 1187 1187 + * if not then start the chain */ 1188 1188 + else { 1189 1189 + start_dma = 1; 1190 1190 + 1191 1191 + if (dma_chan[dma_chan[lch].prev_linked_ch].state == 1192 1192 + DMA_CH_STARTED) { 1193 1193 + enable_lnk(dma_chan[lch].prev_linked_ch); 1194 1194 + dma_chan[lch].state = DMA_CH_QUEUED; 1195 1195 + start_dma = 0; 1196 1196 + if (0 == ((1 << 7) & (OMAP_DMA_CCR_REG 1197 1197 + (dma_chan[lch].prev_linked_ch)))) { 1198 1198 + disable_lnk(dma_chan[lch]. 1199 1199 + prev_linked_ch); 1200 1200 + pr_debug("\n prev ch is stopped\n"); 1201 1201 + start_dma = 1; 1202 1202 + } 1203 1203 + } 1204 1204 + 1205 1205 + else if (dma_chan[dma_chan[lch].prev_linked_ch].state 1206 1206 + == DMA_CH_QUEUED) { 1207 1207 + enable_lnk(dma_chan[lch].prev_linked_ch); 1208 1208 + dma_chan[lch].state = DMA_CH_QUEUED; 1209 1209 + start_dma = 0; 1210 1210 + } 1211 1211 + omap_enable_channel_irq(lch); 1212 1212 + 1213 1213 + w = OMAP_DMA_CCR_REG(lch); 1214 1214 + 1215 1215 + if ((0 == (w & (1 << 24)))) 1216 1216 + w &= ~(1 << 25); 1217 1217 + else 1218 1218 + w |= (1 << 25); 1219 1219 + if (start_dma == 1) { 1220 1220 + if (0 == (w & (1 << 7))) { 1221 1221 + w |= (1 << 7); 1222 1222 + dma_chan[lch].state = DMA_CH_STARTED; 1223 1223 + pr_debug("starting %d\n", lch); 1224 1224 + OMAP_DMA_CCR_REG(lch) = w; 1225 1225 + } else 1226 1226 + start_dma = 0; 1227 1227 + } else { 1228 1228 + if (0 == (w & (1 << 7))) 1229 1229 + OMAP_DMA_CCR_REG(lch) = w; 1230 1230 + } 1231 1231 + dma_chan[lch].flags |= OMAP_DMA_ACTIVE; 1232 1232 + } 1233 1233 + } 1234 1234 + return start_dma; 1235 1235 + } 1236 1236 + EXPORT_SYMBOL(omap_dma_chain_a_transfer); 1237 1237 + 1238 1238 + /** 1239 1239 + * @brief omap_start_dma_chain_transfers - Start the chain 1240 1240 + * 1241 1241 + * @param chain_id 1242 1242 + * 1243 1243 + * @return - Success : 0 1244 1244 + * Failure : -EINVAL/-EBUSY 1245 1245 + */ 1246 1246 + int omap_start_dma_chain_transfers(int chain_id) 1247 1247 + { 1248 1248 + int *channels; 1249 1249 + u32 w, i; 1250 1250 + 1251 1251 + if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1252 1252 + printk(KERN_ERR "Invalid chain id\n"); 1253 1253 + return -EINVAL; 1254 1254 + } 1255 1255 + 1256 1256 + channels = dma_linked_lch[chain_id].linked_dmach_q; 1257 1257 + 1258 1258 + if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) { 1259 1259 + printk(KERN_ERR "Chain is already started\n"); 1260 1260 + return -EBUSY; 1261 1261 + } 1262 1262 + 1263 1263 + if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) { 1264 1264 + for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; 1265 1265 + i++) { 1266 1266 + enable_lnk(channels[i]); 1267 1267 + omap_enable_channel_irq(channels[i]); 1268 1268 + } 1269 1269 + } else { 1270 1270 + omap_enable_channel_irq(channels[0]); 1271 1271 + } 1272 1272 + 1273 1273 + w = OMAP_DMA_CCR_REG(channels[0]); 1274 1274 + w |= (1 << 7); 1275 1275 + dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED; 1276 1276 + dma_chan[channels[0]].state = DMA_CH_STARTED; 1277 1277 + 1278 1278 + if ((0 == (w & (1 << 24)))) 1279 1279 + w &= ~(1 << 25); 1280 1280 + else 1281 1281 + w |= (1 << 25); 1282 1282 + OMAP_DMA_CCR_REG(channels[0]) = w; 1283 1283 + 1284 1284 + dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE; 1285 1285 + return 0; 1286 1286 + } 1287 1287 + EXPORT_SYMBOL(omap_start_dma_chain_transfers); 1288 1288 + 1289 1289 + /** 1290 1290 + * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain. 1291 1291 + * 1292 1292 + * @param chain_id 1293 1293 + * 1294 1294 + * @return - Success : 0 1295 1295 + * Failure : EINVAL 1296 1296 + */ 1297 1297 + int omap_stop_dma_chain_transfers(int chain_id) 1298 1298 + { 1299 1299 + int *channels; 1300 1300 + u32 w, i; 1301 1301 + u32 sys_cf; 1302 1302 + 1303 1303 + /* Check for input params */ 1304 1304 + if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1305 1305 + printk(KERN_ERR "Invalid chain id\n"); 1306 1306 + return -EINVAL; 1307 1307 + } 1308 1308 + 1309 1309 + /* Check if the chain exists */ 1310 1310 + if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { 1311 1311 + printk(KERN_ERR "Chain doesn't exists\n"); 1312 1312 + return -EINVAL; 1313 1313 + } 1314 1314 + channels = dma_linked_lch[chain_id].linked_dmach_q; 1315 1315 + 1316 1316 + /* DMA Errata: 1317 1317 + * Special programming model needed to disable DMA before end of block 1318 1318 + */ 1319 1319 + sys_cf = omap_readl(OMAP_DMA4_OCP_SYSCONFIG); 1320 1320 + w = sys_cf; 1321 1321 + /* Middle mode reg set no Standby */ 1322 1322 + w &= ~((1 << 12)|(1 << 13)); 1323 1323 + omap_writel(w, OMAP_DMA4_OCP_SYSCONFIG); 1324 1324 + 1325 1325 + for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) { 1326 1326 + 1327 1327 + /* Stop the Channel transmission */ 1328 1328 + w = OMAP_DMA_CCR_REG(channels[i]); 1329 1329 + w &= ~(1 << 7); 1330 1330 + OMAP_DMA_CCR_REG(channels[i]) = w; 1331 1331 + 1332 1332 + /* Disable the link in all the channels */ 1333 1333 + disable_lnk(channels[i]); 1334 1334 + dma_chan[channels[i]].state = DMA_CH_NOTSTARTED; 1335 1335 + 1336 1336 + } 1337 1337 + dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED; 1338 1338 + 1339 1339 + /* Reset the Queue pointers */ 1340 1340 + OMAP_DMA_CHAIN_QINIT(chain_id); 1341 1341 + 1342 1342 + /* Errata - put in the old value */ 1343 1343 + omap_writel(sys_cf, OMAP_DMA4_OCP_SYSCONFIG); 1344 1344 + return 0; 1345 1345 + } 1346 1346 + EXPORT_SYMBOL(omap_stop_dma_chain_transfers); 1347 1347 + 1348 1348 + /* Get the index of the ongoing DMA in chain */ 1349 1349 + /** 1350 1350 + * @brief omap_get_dma_chain_index - Get the element and frame index 1351 1351 + * of the ongoing DMA in chain 1352 1352 + * 1353 1353 + * @param chain_id 1354 1354 + * @param ei - Element index 1355 1355 + * @param fi - Frame index 1356 1356 + * 1357 1357 + * @return - Success : 0 1358 1358 + * Failure : -EINVAL 1359 1359 + */ 1360 1360 + int omap_get_dma_chain_index(int chain_id, int *ei, int *fi) 1361 1361 + { 1362 1362 + int lch; 1363 1363 + int *channels; 1364 1364 + 1365 1365 + /* Check for input params */ 1366 1366 + if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1367 1367 + printk(KERN_ERR "Invalid chain id\n"); 1368 1368 + return -EINVAL; 1369 1369 + } 1370 1370 + 1371 1371 + /* Check if the chain exists */ 1372 1372 + if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { 1373 1373 + printk(KERN_ERR "Chain doesn't exists\n"); 1374 1374 + return -EINVAL; 1375 1375 + } 1376 1376 + if ((!ei) || (!fi)) 1377 1377 + return -EINVAL; 1378 1378 + 1379 1379 + channels = dma_linked_lch[chain_id].linked_dmach_q; 1380 1380 + 1381 1381 + /* Get the current channel */ 1382 1382 + lch = channels[dma_linked_lch[chain_id].q_head]; 1383 1383 + 1384 1384 + *ei = OMAP2_DMA_CCEN_REG(lch); 1385 1385 + *fi = OMAP2_DMA_CCFN_REG(lch); 1386 1386 + 1387 1387 + return 0; 1388 1388 + } 1389 1389 + EXPORT_SYMBOL(omap_get_dma_chain_index); 1390 1390 + 1391 1391 + /** 1392 1392 + * @brief omap_get_dma_chain_dst_pos - Get the destination position of the 1393 1393 + * ongoing DMA in chain 1394 1394 + * 1395 1395 + * @param chain_id 1396 1396 + * 1397 1397 + * @return - Success : Destination position 1398 1398 + * Failure : -EINVAL 1399 1399 + */ 1400 1400 + int omap_get_dma_chain_dst_pos(int chain_id) 1401 1401 + { 1402 1402 + int lch; 1403 1403 + int *channels; 1404 1404 + 1405 1405 + /* Check for input params */ 1406 1406 + if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1407 1407 + printk(KERN_ERR "Invalid chain id\n"); 1408 1408 + return -EINVAL; 1409 1409 + } 1410 1410 + 1411 1411 + /* Check if the chain exists */ 1412 1412 + if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { 1413 1413 + printk(KERN_ERR "Chain doesn't exists\n"); 1414 1414 + return -EINVAL; 1415 1415 + } 1416 1416 + 1417 1417 + channels = dma_linked_lch[chain_id].linked_dmach_q; 1418 1418 + 1419 1419 + /* Get the current channel */ 1420 1420 + lch = channels[dma_linked_lch[chain_id].q_head]; 1421 1421 + 1422 1422 + return (OMAP_DMA_CDAC_REG(lch)); 1423 1423 + } 1424 1424 + EXPORT_SYMBOL(omap_get_dma_chain_dst_pos); 1425 1425 + 1426 1426 + /** 1427 1427 + * @brief omap_get_dma_chain_src_pos - Get the source position 1428 1428 + * of the ongoing DMA in chain 1429 1429 + * @param chain_id 1430 1430 + * 1431 1431 + * @return - Success : Destination position 1432 1432 + * Failure : -EINVAL 1433 1433 + */ 1434 1434 + int omap_get_dma_chain_src_pos(int chain_id) 1435 1435 + { 1436 1436 + int lch; 1437 1437 + int *channels; 1438 1438 + 1439 1439 + /* Check for input params */ 1440 1440 + if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1441 1441 + printk(KERN_ERR "Invalid chain id\n"); 1442 1442 + return -EINVAL; 1443 1443 + } 1444 1444 + 1445 1445 + /* Check if the chain exists */ 1446 1446 + if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { 1447 1447 + printk(KERN_ERR "Chain doesn't exists\n"); 1448 1448 + return -EINVAL; 1449 1449 + } 1450 1450 + 1451 1451 + channels = dma_linked_lch[chain_id].linked_dmach_q; 1452 1452 + 1453 1453 + /* Get the current channel */ 1454 1454 + lch = channels[dma_linked_lch[chain_id].q_head]; 1455 1455 + 1456 1456 + return (OMAP_DMA_CSAC_REG(lch)); 1457 1457 + } 1458 1458 + EXPORT_SYMBOL(omap_get_dma_chain_src_pos); 1459 1459 + #endif 1460 1460 + 998 1461 /*----------------------------------------------------------------------------*/ 999 1462 1000 1463 #ifdef CONFIG_ARCH_OMAP1 ··· 1654 919 #define omap1_dma_irq_handler NULL 1655 920 #endif 1656 921 1657 1657 - #ifdef CONFIG_ARCH_OMAP2 922 922 + #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 1658 923 1659 924 static int omap2_dma_handle_ch(int ch) 1660 925 { ··· 1688 953 OMAP_DMA_CSR_REG(ch) = OMAP2_DMA_CSR_CLEAR_MASK; 1689 954 omap_writel(1 << ch, OMAP_DMA4_IRQSTATUS_L0); 1690 955 1691 1691 - if (likely(dma_chan[ch].callback != NULL)) 1692 1692 - dma_chan[ch].callback(ch, status, dma_chan[ch].data); 956 956 + /* If the ch is not chained then chain_id will be -1 */ 957 957 + if (dma_chan[ch].chain_id != -1) { 958 958 + int chain_id = dma_chan[ch].chain_id; 959 959 + dma_chan[ch].state = DMA_CH_NOTSTARTED; 960 960 + if (OMAP_DMA_CLNK_CTRL_REG(ch) & (1 << 15)) 961 961 + dma_chan[dma_chan[ch].next_linked_ch].state = 962 962 + DMA_CH_STARTED; 963 963 + if (dma_linked_lch[chain_id].chain_mode == 964 964 + OMAP_DMA_DYNAMIC_CHAIN) 965 965 + disable_lnk(ch); 966 966 + 967 967 + if (!OMAP_DMA_CHAIN_QEMPTY(chain_id)) 968 968 + OMAP_DMA_CHAIN_INCQHEAD(chain_id); 969 969 + 970 970 + status = OMAP_DMA_CSR_REG(ch); 971 971 + } 972 972 + 973 973 + if (likely(dma_chan[ch].callback != NULL)) { 974 974 + if (dma_chan[ch].chain_id != -1) 975 975 + dma_chan[ch].callback(dma_chan[ch].chain_id, status, 976 976 + dma_chan[ch].data); 977 977 + else 978 978 + dma_chan[ch].callback(ch, status, dma_chan[ch].data); 979 979 + 980 980 + } 981 981 + 982 982 + OMAP_DMA_CSR_REG(ch) = status; 1693 983 1694 984 return 0; 1695 985 } ··· 2145 1385 w &= ~(1 << 8); 2146 1386 omap_writew(w, OMAP1610_DMA_LCD_CTRL); 2147 1387 } 2148 2148 - } else if (cpu_is_omap24xx()) { 1388 1388 + } else if (cpu_class_is_omap2()) { 2149 1389 u8 revision = omap_readb(OMAP_DMA4_REVISION); 2150 1390 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", 2151 1391 revision >> 4, revision & 0xf); ··· 2188 1428 } 2189 1429 } 2190 1430 2191 2191 - if (cpu_is_omap24xx()) 1431 1431 + if (cpu_is_omap2430() || cpu_is_omap34xx()) 1432 1432 + omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE, 1433 1433 + DMA_DEFAULT_FIFO_DEPTH, 0); 1434 1434 + 1435 1435 + if (cpu_class_is_omap2()) 2192 1436 setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq); 2193 1437 2194 1438 /* FIXME: Update LCD DMA to work on 24xx */

+88 -28

arch/arm/plat-omap/dmtimer.c

reviewed

··· 48 48 #define OMAP_TIMER_COUNTER_REG 0x28 49 49 #define OMAP_TIMER_LOAD_REG 0x2c 50 50 #define OMAP_TIMER_TRIGGER_REG 0x30 51 51 - #define OMAP_TIMER_WRITE_PEND_REG 0x34 51 51 + #define OMAP_TIMER_WRITE_PEND_REG 0x34 52 52 #define OMAP_TIMER_MATCH_REG 0x38 53 53 #define OMAP_TIMER_CAPTURE_REG 0x3c 54 54 #define OMAP_TIMER_IF_CTRL_REG 0x40 ··· 70 70 struct omap_dm_timer { 71 71 unsigned long phys_base; 72 72 int irq; 73 73 - #ifdef CONFIG_ARCH_OMAP2 73 73 + #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 74 74 struct clk *iclk, *fclk; 75 75 #endif 76 76 void __iomem *io_base; ··· 82 82 83 83 #define omap_dm_clk_enable(x) 84 84 #define omap_dm_clk_disable(x) 85 85 + #define omap2_dm_timers NULL 86 86 + #define omap2_dm_source_names NULL 87 87 + #define omap2_dm_source_clocks NULL 88 88 + #define omap3_dm_timers NULL 89 89 + #define omap3_dm_source_names NULL 90 90 + #define omap3_dm_source_clocks NULL 85 91 86 86 - static struct omap_dm_timer dm_timers[] = { 92 92 + static struct omap_dm_timer omap1_dm_timers[] = { 87 93 { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 }, 88 94 { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 }, 89 95 { .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 }, ··· 100 94 { .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 }, 101 95 }; 102 96 97 97 + static const int dm_timer_count = ARRAY_SIZE(omap1_dm_timers); 98 98 + 103 99 #elif defined(CONFIG_ARCH_OMAP2) 104 100 105 105 - #define omap_dm_clk_enable(x) clk_enable(x) 106 106 - #define omap_dm_clk_disable(x) clk_disable(x) 101 101 + #define omap_dm_clk_enable(x) clk_enable(x) 102 102 + #define omap_dm_clk_disable(x) clk_disable(x) 103 103 + #define omap1_dm_timers NULL 104 104 + #define omap3_dm_timers NULL 105 105 + #define omap3_dm_source_names NULL 106 106 + #define omap3_dm_source_clocks NULL 107 107 108 108 - static struct omap_dm_timer dm_timers[] = { 108 108 + static struct omap_dm_timer omap2_dm_timers[] = { 109 109 { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 }, 110 110 { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 }, 111 111 { .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 }, ··· 126 114 { .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 }, 127 115 }; 128 116 129 129 - static const char *dm_source_names[] = { 117 117 + static const char *omap2_dm_source_names[] __initdata = { 130 118 "sys_ck", 131 119 "func_32k_ck", 132 132 - "alt_ck" 120 120 + "alt_ck", 121 121 + NULL 133 122 }; 134 123 135 135 - static struct clk *dm_source_clocks[3]; 124 124 + static struct clk **omap2_dm_source_clocks[3]; 125 125 + static const int dm_timer_count = ARRAY_SIZE(omap2_dm_timers); 126 126 + 127 127 + #elif defined(CONFIG_ARCH_OMAP3) 128 128 + 129 129 + #define omap_dm_clk_enable(x) clk_enable(x) 130 130 + #define omap_dm_clk_disable(x) clk_disable(x) 131 131 + #define omap1_dm_timers NULL 132 132 + #define omap2_dm_timers NULL 133 133 + #define omap2_dm_source_names NULL 134 134 + #define omap2_dm_source_clocks NULL 135 135 + 136 136 + static struct omap_dm_timer omap3_dm_timers[] = { 137 137 + { .phys_base = 0x48318000, .irq = INT_24XX_GPTIMER1 }, 138 138 + { .phys_base = 0x49032000, .irq = INT_24XX_GPTIMER2 }, 139 139 + { .phys_base = 0x49034000, .irq = INT_24XX_GPTIMER3 }, 140 140 + { .phys_base = 0x49036000, .irq = INT_24XX_GPTIMER4 }, 141 141 + { .phys_base = 0x49038000, .irq = INT_24XX_GPTIMER5 }, 142 142 + { .phys_base = 0x4903A000, .irq = INT_24XX_GPTIMER6 }, 143 143 + { .phys_base = 0x4903C000, .irq = INT_24XX_GPTIMER7 }, 144 144 + { .phys_base = 0x4903E000, .irq = INT_24XX_GPTIMER8 }, 145 145 + { .phys_base = 0x49040000, .irq = INT_24XX_GPTIMER9 }, 146 146 + { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 }, 147 147 + { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 }, 148 148 + { .phys_base = 0x48304000, .irq = INT_24XX_GPTIMER12 }, 149 149 + }; 150 150 + 151 151 + static const char *omap3_dm_source_names[] __initdata = { 152 152 + "sys_ck", 153 153 + "omap_32k_fck", 154 154 + NULL 155 155 + }; 156 156 + 157 157 + static struct clk **omap3_dm_source_clocks[2]; 158 158 + static const int dm_timer_count = ARRAY_SIZE(omap3_dm_timers); 136 159 137 160 #else 138 161 ··· 175 128 176 129 #endif 177 130 178 178 - static const int dm_timer_count = ARRAY_SIZE(dm_timers); 131 131 + static struct omap_dm_timer *dm_timers; 132 132 + static char **dm_source_names; 133 133 + static struct clk **dm_source_clocks; 134 134 + 179 135 static spinlock_t dm_timer_lock; 180 136 181 137 static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg) ··· 349 299 return inputmask; 350 300 } 351 301 352 352 - #elif defined(CONFIG_ARCH_OMAP2) 302 302 + #elif defined(CONFIG_ARCH_OMAP2) || defined (CONFIG_ARCH_OMAP3) 353 303 354 304 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) 355 305 { ··· 536 486 return 0; 537 487 } 538 488 539 539 - int omap_dm_timer_init(void) 489 489 + int __init omap_dm_timer_init(void) 540 490 { 541 491 struct omap_dm_timer *timer; 542 492 int i; 543 493 544 544 - if (!(cpu_is_omap16xx() || cpu_is_omap24xx())) 494 494 + if (!(cpu_is_omap16xx() || cpu_class_is_omap2())) 545 495 return -ENODEV; 546 496 547 497 spin_lock_init(&dm_timer_lock); 548 548 - #ifdef CONFIG_ARCH_OMAP2 549 549 - for (i = 0; i < ARRAY_SIZE(dm_source_names); i++) { 550 550 - dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]); 551 551 - BUG_ON(dm_source_clocks[i] == NULL); 498 498 + 499 499 + if (cpu_class_is_omap1()) 500 500 + dm_timers = omap1_dm_timers; 501 501 + else if (cpu_is_omap24xx()) { 502 502 + dm_timers = omap2_dm_timers; 503 503 + dm_source_names = (char **)omap2_dm_source_names; 504 504 + dm_source_clocks = (struct clk **)omap2_dm_source_clocks; 505 505 + } else if (cpu_is_omap34xx()) { 506 506 + dm_timers = omap3_dm_timers; 507 507 + dm_source_names = (char **)omap3_dm_source_names; 508 508 + dm_source_clocks = (struct clk **)omap3_dm_source_clocks; 552 509 } 553 553 - #endif 510 510 + 511 511 + if (cpu_class_is_omap2()) 512 512 + for (i = 0; dm_source_names[i] != NULL; i++) 513 513 + dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]); 514 514 + 554 515 if (cpu_is_omap243x()) 555 516 dm_timers[0].phys_base = 0x49018000; 556 517 557 518 for (i = 0; i < dm_timer_count; i++) { 558 558 - #ifdef CONFIG_ARCH_OMAP2 559 559 - char clk_name[16]; 560 560 - #endif 561 561 - 562 519 timer = &dm_timers[i]; 563 563 - timer->io_base = (void __iomem *) io_p2v(timer->phys_base); 564 564 - #ifdef CONFIG_ARCH_OMAP2 565 565 - sprintf(clk_name, "gpt%d_ick", i + 1); 566 566 - timer->iclk = clk_get(NULL, clk_name); 567 567 - sprintf(clk_name, "gpt%d_fck", i + 1); 568 568 - timer->fclk = clk_get(NULL, clk_name); 520 520 + timer->io_base = (void __iomem *)io_p2v(timer->phys_base); 521 521 + #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 522 522 + if (cpu_class_is_omap2()) { 523 523 + char clk_name[16]; 524 524 + sprintf(clk_name, "gpt%d_ick", i + 1); 525 525 + timer->iclk = clk_get(NULL, clk_name); 526 526 + sprintf(clk_name, "gpt%d_fck", i + 1); 527 527 + timer->fclk = clk_get(NULL, clk_name); 528 528 + } 569 529 #endif 570 530 } 571 531

+185 -73

arch/arm/plat-omap/gpio.c

reviewed

··· 110 110 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044 111 111 #define OMAP24XX_GPIO_RISINGDETECT 0x0048 112 112 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c 113 113 + #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050 114 114 + #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054 113 115 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060 114 116 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064 115 117 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080 ··· 119 117 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 120 118 #define OMAP24XX_GPIO_SETDATAOUT 0x0094 121 119 120 120 + /* 121 121 + * omap34xx specific GPIO registers 122 122 + */ 123 123 + 124 124 + #define OMAP34XX_GPIO1_BASE (void __iomem *)0x48310000 125 125 + #define OMAP34XX_GPIO2_BASE (void __iomem *)0x49050000 126 126 + #define OMAP34XX_GPIO3_BASE (void __iomem *)0x49052000 127 127 + #define OMAP34XX_GPIO4_BASE (void __iomem *)0x49054000 128 128 + #define OMAP34XX_GPIO5_BASE (void __iomem *)0x49056000 129 129 + #define OMAP34XX_GPIO6_BASE (void __iomem *)0x49058000 130 130 + 131 131 + 122 132 struct gpio_bank { 123 133 void __iomem *base; 124 134 u16 irq; 125 135 u16 virtual_irq_start; 126 136 int method; 127 137 u32 reserved_map; 128 128 - #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX) 138 138 + #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 129 139 u32 suspend_wakeup; 130 140 u32 saved_wakeup; 131 141 #endif 132 132 - #ifdef CONFIG_ARCH_OMAP24XX 142 142 + #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 133 143 u32 non_wakeup_gpios; 134 144 u32 enabled_non_wakeup_gpios; 135 145 ··· 206 192 207 193 #endif 208 194 195 195 + #ifdef CONFIG_ARCH_OMAP34XX 196 196 + static struct gpio_bank gpio_bank_34xx[6] = { 197 197 + { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, 198 198 + { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, 199 199 + { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, 200 200 + { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, 201 201 + { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX }, 202 202 + { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX }, 203 203 + }; 204 204 + 205 205 + #endif 206 206 + 209 207 static struct gpio_bank *gpio_bank; 210 208 static int gpio_bank_count; 211 209 212 210 static inline struct gpio_bank *get_gpio_bank(int gpio) 213 211 { 214 214 - #ifdef CONFIG_ARCH_OMAP15XX 215 212 if (cpu_is_omap15xx()) { 216 213 if (OMAP_GPIO_IS_MPUIO(gpio)) 217 214 return &gpio_bank[0]; 218 215 return &gpio_bank[1]; 219 216 } 220 220 - #endif 221 221 - #if defined(CONFIG_ARCH_OMAP16XX) 222 217 if (cpu_is_omap16xx()) { 223 218 if (OMAP_GPIO_IS_MPUIO(gpio)) 224 219 return &gpio_bank[0]; 225 220 return &gpio_bank[1 + (gpio >> 4)]; 226 221 } 227 227 - #endif 228 228 - #ifdef CONFIG_ARCH_OMAP730 229 222 if (cpu_is_omap730()) { 230 223 if (OMAP_GPIO_IS_MPUIO(gpio)) 231 224 return &gpio_bank[0]; 232 225 return &gpio_bank[1 + (gpio >> 5)]; 233 226 } 234 234 - #endif 235 235 - #ifdef CONFIG_ARCH_OMAP24XX 236 227 if (cpu_is_omap24xx()) 237 228 return &gpio_bank[gpio >> 5]; 238 238 - #endif 229 229 + if (cpu_is_omap34xx()) 230 230 + return &gpio_bank[gpio >> 5]; 239 231 } 240 232 241 233 static inline int get_gpio_index(int gpio) 242 234 { 243 243 - #ifdef CONFIG_ARCH_OMAP730 244 235 if (cpu_is_omap730()) 245 236 return gpio & 0x1f; 246 246 - #endif 247 247 - #ifdef CONFIG_ARCH_OMAP24XX 248 237 if (cpu_is_omap24xx()) 249 238 return gpio & 0x1f; 250 250 - #endif 239 239 + if (cpu_is_omap34xx()) 240 240 + return gpio & 0x1f; 251 241 return gpio & 0x0f; 252 242 } 253 243 ··· 259 241 { 260 242 if (gpio < 0) 261 243 return -1; 262 262 - #ifndef CONFIG_ARCH_OMAP24XX 263 263 - if (OMAP_GPIO_IS_MPUIO(gpio)) { 244 244 + if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) { 264 245 if (gpio >= OMAP_MAX_GPIO_LINES + 16) 265 246 return -1; 266 247 return 0; 267 248 } 268 268 - #endif 269 269 - #ifdef CONFIG_ARCH_OMAP15XX 270 249 if (cpu_is_omap15xx() && gpio < 16) 271 250 return 0; 272 272 - #endif 273 273 - #if defined(CONFIG_ARCH_OMAP16XX) 274 251 if ((cpu_is_omap16xx()) && gpio < 64) 275 252 return 0; 276 276 - #endif 277 277 - #ifdef CONFIG_ARCH_OMAP730 278 253 if (cpu_is_omap730() && gpio < 192) 279 254 return 0; 280 280 - #endif 281 281 - #ifdef CONFIG_ARCH_OMAP24XX 282 255 if (cpu_is_omap24xx() && gpio < 128) 283 256 return 0; 284 284 - #endif 257 257 + if (cpu_is_omap34xx() && gpio < 160) 258 258 + return 0; 285 259 return -1; 286 260 } 287 261 ··· 313 303 reg += OMAP730_GPIO_DIR_CONTROL; 314 304 break; 315 305 #endif 316 316 - #ifdef CONFIG_ARCH_OMAP24XX 306 306 + #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 317 307 case METHOD_GPIO_24XX: 318 308 reg += OMAP24XX_GPIO_OE; 319 309 break; ··· 387 377 l &= ~(1 << gpio); 388 378 break; 389 379 #endif 390 390 - #ifdef CONFIG_ARCH_OMAP24XX 380 380 + #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 391 381 case METHOD_GPIO_24XX: 392 382 if (enable) 393 383 reg += OMAP24XX_GPIO_SETDATAOUT; ··· 445 435 reg += OMAP730_GPIO_DATA_INPUT; 446 436 break; 447 437 #endif 448 448 - #ifdef CONFIG_ARCH_OMAP24XX 438 438 + #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 449 439 case METHOD_GPIO_24XX: 450 440 reg += OMAP24XX_GPIO_DATAIN; 451 441 break; ··· 465 455 __raw_writel(l, base + reg); \ 466 456 } while(0) 467 457 468 468 - #ifdef CONFIG_ARCH_OMAP24XX 469 469 - static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) 458 458 + void omap_set_gpio_debounce(int gpio, int enable) 459 459 + { 460 460 + struct gpio_bank *bank; 461 461 + void __iomem *reg; 462 462 + u32 val, l = 1 << get_gpio_index(gpio); 463 463 + 464 464 + if (cpu_class_is_omap1()) 465 465 + return; 466 466 + 467 467 + bank = get_gpio_bank(gpio); 468 468 + reg = bank->base; 469 469 + 470 470 + reg += OMAP24XX_GPIO_DEBOUNCE_EN; 471 471 + val = __raw_readl(reg); 472 472 + 473 473 + if (enable) 474 474 + val |= l; 475 475 + else 476 476 + val &= ~l; 477 477 + 478 478 + __raw_writel(val, reg); 479 479 + } 480 480 + EXPORT_SYMBOL(omap_set_gpio_debounce); 481 481 + 482 482 + void omap_set_gpio_debounce_time(int gpio, int enc_time) 483 483 + { 484 484 + struct gpio_bank *bank; 485 485 + void __iomem *reg; 486 486 + 487 487 + if (cpu_class_is_omap1()) 488 488 + return; 489 489 + 490 490 + bank = get_gpio_bank(gpio); 491 491 + reg = bank->base; 492 492 + 493 493 + enc_time &= 0xff; 494 494 + reg += OMAP24XX_GPIO_DEBOUNCE_VAL; 495 495 + __raw_writel(enc_time, reg); 496 496 + } 497 497 + EXPORT_SYMBOL(omap_set_gpio_debounce_time); 498 498 + 499 499 + #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 500 500 + static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, 501 501 + int trigger) 470 502 { 471 503 void __iomem *base = bank->base; 472 504 u32 gpio_bit = 1 << gpio; ··· 521 469 trigger & __IRQT_RISEDGE); 522 470 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, 523 471 trigger & __IRQT_FALEDGE); 472 472 + 524 473 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { 525 474 if (trigger != 0) 526 526 - __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_SETWKUENA); 475 475 + __raw_writel(1 << gpio, bank->base 476 476 + + OMAP24XX_GPIO_SETWKUENA); 527 477 else 528 528 - __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_CLEARWKUENA); 478 478 + __raw_writel(1 << gpio, bank->base 479 479 + + OMAP24XX_GPIO_CLEARWKUENA); 529 480 } else { 530 481 if (trigger != 0) 531 482 bank->enabled_non_wakeup_gpios |= gpio_bit; 532 483 else 533 484 bank->enabled_non_wakeup_gpios &= ~gpio_bit; 534 485 } 535 535 - /* FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only level 536 536 - * triggering requested. */ 486 486 + 487 487 + /* 488 488 + * FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only 489 489 + * level triggering requested. 490 490 + */ 537 491 } 538 492 #endif 539 493 ··· 605 547 goto bad; 606 548 break; 607 549 #endif 608 608 - #ifdef CONFIG_ARCH_OMAP24XX 550 550 + #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 609 551 case METHOD_GPIO_24XX: 610 552 set_24xx_gpio_triggering(bank, gpio, trigger); 611 553 break; ··· 625 567 unsigned gpio; 626 568 int retval; 627 569 628 628 - if (!cpu_is_omap24xx() && irq > IH_MPUIO_BASE) 570 570 + if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE) 629 571 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); 630 572 else 631 573 gpio = irq - IH_GPIO_BASE; ··· 637 579 return -EINVAL; 638 580 639 581 /* OMAP1 allows only only edge triggering */ 640 640 - if (!cpu_is_omap24xx() 582 582 + if (!cpu_class_is_omap2() 641 583 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) 642 584 return -EINVAL; 643 585 ··· 678 620 reg += OMAP730_GPIO_INT_STATUS; 679 621 break; 680 622 #endif 681 681 - #ifdef CONFIG_ARCH_OMAP24XX 623 623 + #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 682 624 case METHOD_GPIO_24XX: 683 625 reg += OMAP24XX_GPIO_IRQSTATUS1; 684 626 break; ··· 690 632 __raw_writel(gpio_mask, reg); 691 633 692 634 /* Workaround for clearing DSP GPIO interrupts to allow retention */ 693 693 - if (cpu_is_omap2420()) 635 635 + #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 636 636 + if (cpu_is_omap24xx() || cpu_is_omap34xx()) 694 637 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2); 638 638 + #endif 695 639 } 696 640 697 641 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) ··· 736 676 inv = 1; 737 677 break; 738 678 #endif 739 739 - #ifdef CONFIG_ARCH_OMAP24XX 679 679 + #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 740 680 case METHOD_GPIO_24XX: 741 681 reg += OMAP24XX_GPIO_IRQENABLE1; 742 682 mask = 0xffffffff; ··· 799 739 l |= gpio_mask; 800 740 break; 801 741 #endif 802 802 - #ifdef CONFIG_ARCH_OMAP24XX 742 742 + #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 803 743 case METHOD_GPIO_24XX: 804 744 if (enable) 805 745 reg += OMAP24XX_GPIO_SETIRQENABLE1; ··· 845 785 spin_unlock(&bank->lock); 846 786 return 0; 847 787 #endif 848 848 - #ifdef CONFIG_ARCH_OMAP24XX 788 788 + #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 849 789 case METHOD_GPIO_24XX: 850 790 if (bank->non_wakeup_gpios & (1 << gpio)) { 851 791 printk(KERN_ERR "Unable to modify wakeup on " ··· 951 891 __raw_writel(1 << get_gpio_index(gpio), reg); 952 892 } 953 893 #endif 954 954 - #ifdef CONFIG_ARCH_OMAP24XX 894 894 + #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 955 895 if (bank->method == METHOD_GPIO_24XX) { 956 896 /* Disable wake-up during idle for dynamic tick */ 957 897 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; ··· 1000 940 if (bank->method == METHOD_GPIO_730) 1001 941 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS; 1002 942 #endif 1003 1003 - #ifdef CONFIG_ARCH_OMAP24XX 943 943 + #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 1004 944 if (bank->method == METHOD_GPIO_24XX) 1005 945 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; 1006 946 #endif ··· 1014 954 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) 1015 955 isr &= 0x0000ffff; 1016 956 1017 1017 - if (cpu_is_omap24xx()) { 957 957 + if (cpu_class_is_omap2()) { 1018 958 level_mask = 1019 959 __raw_readl(bank->base + 1020 960 OMAP24XX_GPIO_LEVELDETECT0) | ··· 1083 1023 } 1084 1024 } 1085 1025 1086 1086 - if (cpu_is_omap24xx()) { 1026 1026 + if (cpu_class_is_omap2()) { 1087 1027 /* clear level sensitive interrupts after handler(s) */ 1088 1028 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0); 1089 1029 _clear_gpio_irqbank(bank, isr_saved & level_mask); ··· 1259 1199 /*---------------------------------------------------------------------*/ 1260 1200 1261 1201 static int initialized; 1202 1202 + #if !defined(CONFIG_ARCH_OMAP3) 1262 1203 static struct clk * gpio_ick; 1263 1263 - static struct clk * gpio_fck; 1204 1204 + #endif 1264 1205 1265 1265 - #ifdef CONFIG_ARCH_OMAP2430 1206 1206 + #if defined(CONFIG_ARCH_OMAP2) 1207 1207 + static struct clk * gpio_fck; 1208 1208 + #endif 1209 1209 + 1210 1210 + #if defined(CONFIG_ARCH_OMAP2430) 1266 1211 static struct clk * gpio5_ick; 1267 1212 static struct clk * gpio5_fck; 1213 1213 + #endif 1214 1214 + 1215 1215 + #if defined(CONFIG_ARCH_OMAP3) 1216 1216 + static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS]; 1217 1217 + static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS]; 1268 1218 #endif 1269 1219 1270 1220 static int __init _omap_gpio_init(void) 1271 1221 { 1272 1222 int i; 1273 1223 struct gpio_bank *bank; 1224 1224 + #if defined(CONFIG_ARCH_OMAP3) 1225 1225 + char clk_name[11]; 1226 1226 + #endif 1274 1227 1275 1228 initialized = 1; 1276 1229 1230 1230 + #if defined(CONFIG_ARCH_OMAP1) 1277 1231 if (cpu_is_omap15xx()) { 1278 1232 gpio_ick = clk_get(NULL, "arm_gpio_ck"); 1279 1233 if (IS_ERR(gpio_ick)) ··· 1295 1221 else 1296 1222 clk_enable(gpio_ick); 1297 1223 } 1298 1298 - if (cpu_is_omap24xx()) { 1224 1224 + #endif 1225 1225 + #if defined(CONFIG_ARCH_OMAP2) 1226 1226 + if (cpu_class_is_omap2()) { 1299 1227 gpio_ick = clk_get(NULL, "gpios_ick"); 1300 1228 if (IS_ERR(gpio_ick)) 1301 1229 printk("Could not get gpios_ick\n"); ··· 1310 1234 clk_enable(gpio_fck); 1311 1235 1312 1236 /* 1313 1313 - * On 2430 GPIO 5 uses CORE L4 ICLK 1237 1237 + * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK 1314 1238 */ 1315 1315 - #ifdef CONFIG_ARCH_OMAP2430 1239 1239 + #if defined(CONFIG_ARCH_OMAP2430) 1316 1240 if (cpu_is_omap2430()) { 1317 1241 gpio5_ick = clk_get(NULL, "gpio5_ick"); 1318 1242 if (IS_ERR(gpio5_ick)) ··· 1326 1250 clk_enable(gpio5_fck); 1327 1251 } 1328 1252 #endif 1329 1329 - } 1253 1253 + } 1254 1254 + #endif 1255 1255 + 1256 1256 + #if defined(CONFIG_ARCH_OMAP3) 1257 1257 + if (cpu_is_omap34xx()) { 1258 1258 + for (i = 0; i < OMAP34XX_NR_GPIOS; i++) { 1259 1259 + sprintf(clk_name, "gpio%d_ick", i + 1); 1260 1260 + gpio_iclks[i] = clk_get(NULL, clk_name); 1261 1261 + if (IS_ERR(gpio_iclks[i])) 1262 1262 + printk(KERN_ERR "Could not get %s\n", clk_name); 1263 1263 + else 1264 1264 + clk_enable(gpio_iclks[i]); 1265 1265 + sprintf(clk_name, "gpio%d_fck", i + 1); 1266 1266 + gpio_fclks[i] = clk_get(NULL, clk_name); 1267 1267 + if (IS_ERR(gpio_fclks[i])) 1268 1268 + printk(KERN_ERR "Could not get %s\n", clk_name); 1269 1269 + else 1270 1270 + clk_enable(gpio_fclks[i]); 1271 1271 + } 1272 1272 + } 1273 1273 + #endif 1274 1274 + 1330 1275 1331 1276 #ifdef CONFIG_ARCH_OMAP15XX 1332 1277 if (cpu_is_omap15xx()) { ··· 1395 1298 (rev >> 4) & 0x0f, rev & 0x0f); 1396 1299 } 1397 1300 #endif 1301 1301 + #ifdef CONFIG_ARCH_OMAP34XX 1302 1302 + if (cpu_is_omap34xx()) { 1303 1303 + int rev; 1304 1304 + 1305 1305 + gpio_bank_count = OMAP34XX_NR_GPIOS; 1306 1306 + gpio_bank = gpio_bank_34xx; 1307 1307 + rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); 1308 1308 + printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n", 1309 1309 + (rev >> 4) & 0x0f, rev & 0x0f); 1310 1310 + } 1311 1311 + #endif 1398 1312 for (i = 0; i < gpio_bank_count; i++) { 1399 1313 int j, gpio_count = 16; 1400 1314 ··· 1415 1307 spin_lock_init(&bank->lock); 1416 1308 if (bank_is_mpuio(bank)) 1417 1309 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT); 1418 1418 - #ifdef CONFIG_ARCH_OMAP15XX 1419 1419 - if (bank->method == METHOD_GPIO_1510) { 1310 1310 + if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { 1420 1311 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK); 1421 1312 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS); 1422 1313 } 1423 1423 - #endif 1424 1424 - #if defined(CONFIG_ARCH_OMAP16XX) 1425 1425 - if (bank->method == METHOD_GPIO_1610) { 1314 1314 + if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) { 1426 1315 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1); 1427 1316 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); 1428 1317 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); 1429 1318 } 1430 1430 - #endif 1431 1431 - #ifdef CONFIG_ARCH_OMAP730 1432 1432 - if (bank->method == METHOD_GPIO_730) { 1319 1319 + if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) { 1433 1320 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK); 1434 1321 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS); 1435 1322 1436 1323 gpio_count = 32; /* 730 has 32-bit GPIOs */ 1437 1324 } 1438 1438 - #endif 1439 1439 - #ifdef CONFIG_ARCH_OMAP24XX 1325 1325 + 1326 1326 + #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 1440 1327 if (bank->method == METHOD_GPIO_24XX) { 1441 1328 static const u32 non_wakeup_gpios[] = { 1442 1329 0xe203ffc0, 0x08700040 ··· 1467 1364 if (cpu_is_omap16xx()) 1468 1365 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL); 1469 1366 1470 1470 - #ifdef CONFIG_ARCH_OMAP24XX 1471 1367 /* Enable autoidle for the OCP interface */ 1472 1368 if (cpu_is_omap24xx()) 1473 1369 omap_writel(1 << 0, 0x48019010); 1474 1474 - #endif 1370 1370 + if (cpu_is_omap34xx()) 1371 1371 + omap_writel(1 << 0, 0x48306814); 1475 1372 1476 1373 return 0; 1477 1374 } 1478 1375 1479 1479 - #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX) 1376 1376 + #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 1480 1377 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) 1481 1378 { 1482 1379 int i; 1483 1380 1484 1484 - if (!cpu_is_omap24xx() && !cpu_is_omap16xx()) 1381 1381 + if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) 1485 1382 return 0; 1486 1383 1487 1384 for (i = 0; i < gpio_bank_count; i++) { ··· 1498 1395 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; 1499 1396 break; 1500 1397 #endif 1501 1501 - #ifdef CONFIG_ARCH_OMAP24XX 1398 1398 + #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 1502 1399 case METHOD_GPIO_24XX: 1503 1400 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA; 1504 1401 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; ··· 1538 1435 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; 1539 1436 break; 1540 1437 #endif 1541 1541 - #ifdef CONFIG_ARCH_OMAP24XX 1438 1438 + #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 1542 1439 case METHOD_GPIO_24XX: 1543 1440 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 1544 1441 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; ··· 1570 1467 1571 1468 #endif 1572 1469 1573 1573 - #ifdef CONFIG_ARCH_OMAP24XX 1470 1470 + #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 1574 1471 1575 1472 static int workaround_enabled; 1576 1473 ··· 1586 1483 1587 1484 if (!(bank->enabled_non_wakeup_gpios)) 1588 1485 continue; 1486 1486 + #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 1589 1487 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); 1590 1488 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); 1591 1489 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); 1490 1490 + #endif 1592 1491 bank->saved_fallingdetect = l1; 1593 1492 bank->saved_risingdetect = l2; 1594 1493 l1 &= ~bank->enabled_non_wakeup_gpios; 1595 1494 l2 &= ~bank->enabled_non_wakeup_gpios; 1495 1495 + #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 1596 1496 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT); 1597 1497 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT); 1498 1498 + #endif 1598 1499 c++; 1599 1500 } 1600 1501 if (!c) { ··· 1620 1513 1621 1514 if (!(bank->enabled_non_wakeup_gpios)) 1622 1515 continue; 1516 1516 + #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 1623 1517 __raw_writel(bank->saved_fallingdetect, 1624 1518 bank->base + OMAP24XX_GPIO_FALLINGDETECT); 1625 1519 __raw_writel(bank->saved_risingdetect, 1626 1520 bank->base + OMAP24XX_GPIO_RISINGDETECT); 1521 1521 + #endif 1627 1522 /* Check if any of the non-wakeup interrupt GPIOs have changed 1628 1523 * state. If so, generate an IRQ by software. This is 1629 1524 * horribly racy, but it's the best we can do to work around 1630 1525 * this silicon bug. */ 1526 1526 + #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 1631 1527 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); 1528 1528 + #endif 1632 1529 l ^= bank->saved_datain; 1633 1530 l &= bank->non_wakeup_gpios; 1634 1531 if (l) { 1635 1532 u32 old0, old1; 1636 1636 - 1533 1533 + #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 1637 1534 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); 1638 1535 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); 1639 1536 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0); 1640 1537 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1); 1641 1538 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0); 1642 1539 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1); 1540 1540 + #endif 1643 1541 } 1644 1542 } 1645 1543 ··· 1673 1561 1674 1562 mpuio_init(); 1675 1563 1676 1676 - #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) 1677 1677 - if (cpu_is_omap16xx() || cpu_is_omap24xx()) { 1564 1564 + #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 1565 1565 + if (cpu_is_omap16xx() || cpu_class_is_omap2()) { 1678 1566 if (ret == 0) { 1679 1567 ret = sysdev_class_register(&omap_gpio_sysclass); 1680 1568 if (ret == 0) ··· 1736 1624 1737 1625 if (bank_is_mpuio(bank)) 1738 1626 gpio = OMAP_MPUIO(0); 1739 1739 - else if (cpu_is_omap24xx() || cpu_is_omap730()) 1627 1627 + else if (cpu_class_is_omap2() || cpu_is_omap730()) 1740 1628 bankwidth = 32; 1741 1629 1742 1630 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {

+148

arch/arm/plat-omap/i2c.c

reviewed

··· 1 1 + /* 2 2 + * linux/arch/arm/plat-omap/i2c.c 3 3 + * 4 4 + * Helper module for board specific I2C bus registration 5 5 + * 6 6 + * Copyright (C) 2007 Nokia Corporation. 7 7 + * 8 8 + * Contact: Jarkko Nikula <jarkko.nikula@nokia.com> 9 9 + * 10 10 + * This program is free software; you can redistribute it and/or 11 11 + * modify it under the terms of the GNU General Public License 12 12 + * version 2 as published by the Free Software Foundation. 13 13 + * 14 14 + * This program is distributed in the hope that it will be useful, but 15 15 + * WITHOUT ANY WARRANTY; without even the implied warranty of 16 16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 17 + * General Public License for more details. 18 18 + * 19 19 + * You should have received a copy of the GNU General Public License 20 20 + * along with this program; if not, write to the Free Software 21 21 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 22 22 + * 02110-1301 USA 23 23 + * 24 24 + */ 25 25 + 26 26 + #include <linux/kernel.h> 27 27 + #include <linux/platform_device.h> 28 28 + #include <linux/i2c.h> 29 29 + #include <asm/mach-types.h> 30 30 + #include <asm/arch/mux.h> 31 31 + 32 32 + #define OMAP_I2C_SIZE 0x3f 33 33 + #define OMAP1_I2C_BASE 0xfffb3800 34 34 + #define OMAP2_I2C_BASE1 0x48070000 35 35 + #define OMAP2_I2C_BASE2 0x48072000 36 36 + #define OMAP2_I2C_BASE3 0x48060000 37 37 + 38 38 + static const char name[] = "i2c_omap"; 39 39 + 40 40 + #define I2C_RESOURCE_BUILDER(base, irq) \ 41 41 + { \ 42 42 + .start = (base), \ 43 43 + .end = (base) + OMAP_I2C_SIZE, \ 44 44 + .flags = IORESOURCE_MEM, \ 45 45 + }, \ 46 46 + { \ 47 47 + .start = (irq), \ 48 48 + .flags = IORESOURCE_IRQ, \ 49 49 + }, 50 50 + 51 51 + static struct resource i2c_resources[][2] = { 52 52 + { I2C_RESOURCE_BUILDER(0, 0) }, 53 53 + #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 54 54 + { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE2, INT_24XX_I2C2_IRQ) }, 55 55 + #endif 56 56 + #if defined(CONFIG_ARCH_OMAP34XX) 57 57 + { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE3, INT_34XX_I2C3_IRQ) }, 58 58 + #endif 59 59 + }; 60 60 + 61 61 + #define I2C_DEV_BUILDER(bus_id, res, data) \ 62 62 + { \ 63 63 + .id = (bus_id), \ 64 64 + .name = name, \ 65 65 + .num_resources = ARRAY_SIZE(res), \ 66 66 + .resource = (res), \ 67 67 + .dev = { \ 68 68 + .platform_data = (data), \ 69 69 + }, \ 70 70 + } 71 71 + 72 72 + static u32 i2c_rate[ARRAY_SIZE(i2c_resources)]; 73 73 + static struct platform_device omap_i2c_devices[] = { 74 74 + I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_rate[0]), 75 75 + #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 76 76 + I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_rate[1]), 77 77 + #endif 78 78 + #if defined(CONFIG_ARCH_OMAP34XX) 79 79 + I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_rate[2]), 80 80 + #endif 81 81 + }; 82 82 + 83 83 + static void __init omap_i2c_mux_pins(int bus_id) 84 84 + { 85 85 + /* TODO: Muxing for OMAP3 */ 86 86 + switch (bus_id) { 87 87 + case 1: 88 88 + if (cpu_class_is_omap1()) { 89 89 + omap_cfg_reg(I2C_SCL); 90 90 + omap_cfg_reg(I2C_SDA); 91 91 + } else if (cpu_is_omap24xx()) { 92 92 + omap_cfg_reg(M19_24XX_I2C1_SCL); 93 93 + omap_cfg_reg(L15_24XX_I2C1_SDA); 94 94 + } 95 95 + break; 96 96 + case 2: 97 97 + if (cpu_is_omap24xx()) { 98 98 + omap_cfg_reg(J15_24XX_I2C2_SCL); 99 99 + omap_cfg_reg(H19_24XX_I2C2_SDA); 100 100 + } 101 101 + break; 102 102 + } 103 103 + } 104 104 + 105 105 + int __init omap_register_i2c_bus(int bus_id, u32 clkrate, 106 106 + struct i2c_board_info const *info, 107 107 + unsigned len) 108 108 + { 109 109 + int ports, err; 110 110 + struct platform_device *pdev; 111 111 + struct resource *res; 112 112 + resource_size_t base, irq; 113 113 + 114 114 + if (cpu_class_is_omap1()) 115 115 + ports = 1; 116 116 + else if (cpu_is_omap24xx()) 117 117 + ports = 2; 118 118 + else if (cpu_is_omap34xx()) 119 119 + ports = 3; 120 120 + 121 121 + BUG_ON(bus_id < 1 || bus_id > ports); 122 122 + 123 123 + if (info) { 124 124 + err = i2c_register_board_info(bus_id, info, len); 125 125 + if (err) 126 126 + return err; 127 127 + } 128 128 + 129 129 + pdev = &omap_i2c_devices[bus_id - 1]; 130 130 + *(u32 *)pdev->dev.platform_data = clkrate; 131 131 + 132 132 + if (bus_id == 1) { 133 133 + res = pdev->resource; 134 134 + if (cpu_class_is_omap1()) { 135 135 + base = OMAP1_I2C_BASE; 136 136 + irq = INT_I2C; 137 137 + } else { 138 138 + base = OMAP2_I2C_BASE1; 139 139 + irq = INT_24XX_I2C1_IRQ; 140 140 + } 141 141 + res[0].start = base; 142 142 + res[0].end = base + OMAP_I2C_SIZE; 143 143 + res[1].start = irq; 144 144 + } 145 145 + 146 146 + omap_i2c_mux_pins(bus_id); 147 147 + return platform_device_register(pdev); 148 148 + }

+11

arch/arm/plat-omap/mcbsp.c

reviewed

··· 201 201 static void omap_mcbsp_dsp_request(void) 202 202 { 203 203 if (cpu_is_omap15xx() || cpu_is_omap16xx()) { 204 204 + int ret; 205 205 + 206 206 + ret = omap_dsp_request_mem(); 207 207 + if (ret < 0) { 208 208 + printk(KERN_ERR "Could not get dsp memory: %i\n", ret); 209 209 + return; 210 210 + } 211 211 + 204 212 clk_enable(mcbsp_dsp_ck); 205 213 clk_enable(mcbsp_api_ck); 206 214 ··· 227 219 static void omap_mcbsp_dsp_free(void) 228 220 { 229 221 if (cpu_is_omap15xx() || cpu_is_omap16xx()) { 222 222 + omap_dsp_release_mem(); 230 223 clk_disable(mcbsp_dspxor_ck); 231 224 clk_disable(mcbsp_dsp_ck); 232 225 clk_disable(mcbsp_api_ck); ··· 1033 1024 EXPORT_SYMBOL(omap_mcbsp_free); 1034 1025 EXPORT_SYMBOL(omap_mcbsp_start); 1035 1026 EXPORT_SYMBOL(omap_mcbsp_stop); 1027 1027 + EXPORT_SYMBOL(omap_mcbsp_pollread); 1028 1028 + EXPORT_SYMBOL(omap_mcbsp_pollwrite); 1036 1029 EXPORT_SYMBOL(omap_mcbsp_xmit_word); 1037 1030 EXPORT_SYMBOL(omap_mcbsp_recv_word); 1038 1031 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);

+2

include/asm-arm/arch-omap/board-apollon.h

reviewed

··· 29 29 #ifndef __ASM_ARCH_OMAP_APOLLON_H 30 30 #define __ASM_ARCH_OMAP_APOLLON_H 31 31 32 32 + extern void apollon_mmc_init(void); 33 33 + 32 34 /* Placeholder for APOLLON specific defines */ 33 35 #define APOLLON_ETHR_GPIO_IRQ 74 34 36

+3

include/asm-arm/arch-omap/board-h2.h

reviewed

··· 34 34 /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ 35 35 #define OMAP1610_ETHR_START 0x04000300 36 36 37 37 + extern void h2_mmc_init(void); 38 38 + extern void h2_mmc_slot_cover_handler(void *arg, int state); 39 39 + 37 40 #endif /* __ASM_ARCH_OMAP_H2_H */ 38 41

+2

include/asm-arm/arch-omap/board-h3.h

reviewed

··· 36 36 37 37 #define NR_IRQS (MAXIRQNUM + 1) 38 38 39 39 + extern void __init h3_mmc_init(void); 40 40 + extern void h3_mmc_slot_cover_handler(void *arg, int state); 39 41 40 42 #endif /* __ASM_ARCH_OMAP_H3_H */

+7 -1

include/asm-arm/arch-omap/board-sx1.h

reviewed

··· 41 41 42 42 int sx1_setmmipower(u8 onoff); 43 43 int sx1_setusbpower(u8 onoff); 44 44 - int sx1_setmmcpower(u8 onoff); 44 44 + int sx1_i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value); 45 45 + int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value); 46 46 + 47 47 + /* MMC prototypes */ 48 48 + 49 49 + extern void sx1_mmc_init(void); 50 50 + extern void sx1_mmc_slot_cover_handler(void *arg, int state); 45 51 46 52 #endif /* __ASM_ARCH_SX1_I2C_CHIPS_H */

+11

include/asm-arm/arch-omap/common.h

reviewed

··· 27 27 #ifndef __ARCH_ARM_MACH_OMAP_COMMON_H 28 28 #define __ARCH_ARM_MACH_OMAP_COMMON_H 29 29 30 30 + #ifdef CONFIG_I2C_OMAP 31 31 + #include <linux/i2c.h> 32 32 + #endif 33 33 + 30 34 struct sys_timer; 31 35 32 36 extern void omap_map_common_io(void); 33 37 extern struct sys_timer omap_timer; 34 38 extern void omap_serial_init(void); 39 39 + #ifdef CONFIG_I2C_OMAP 40 40 + extern int omap_register_i2c_bus(int bus_id, u32 clkrate, 41 41 + struct i2c_board_info const *info, 42 42 + unsigned len); 43 43 + #else 44 44 + #define omap_register_i2c_bus(a, b, c, d) 0 45 45 + #endif 35 46 36 47 #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */

+122 -7

include/asm-arm/arch-omap/cpu.h

reviewed

··· 28 28 29 29 extern unsigned int system_rev; 30 30 31 31 - #define omap2_cpu_rev() ((system_rev >> 8) & 0x0f) 31 31 + #define omap2_cpu_rev() ((system_rev >> 12) & 0x0f) 32 32 33 33 /* 34 34 * Test if multicore OMAP support is needed ··· 61 61 # define OMAP_NAME omap16xx 62 62 # endif 63 63 #endif 64 64 - #ifdef CONFIG_ARCH_OMAP24XX 64 64 + #if (defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)) 65 65 # if (defined(OMAP_NAME) || defined(MULTI_OMAP1)) 66 66 # error "OMAP1 and OMAP2 can't be selected at the same time" 67 67 - # else 67 67 + # endif 68 68 + #endif 69 69 + #ifdef CONFIG_ARCH_OMAP2420 70 70 + # ifdef OMAP_NAME 68 71 # undef MULTI_OMAP2 69 69 - # define OMAP_NAME omap24xx 72 72 + # define MULTI_OMAP2 73 73 + # else 74 74 + # define OMAP_NAME omap2420 75 75 + # endif 76 76 + #endif 77 77 + #ifdef CONFIG_ARCH_OMAP2430 78 78 + # ifdef OMAP_NAME 79 79 + # undef MULTI_OMAP2 80 80 + # define MULTI_OMAP2 81 81 + # else 82 82 + # define OMAP_NAME omap2430 83 83 + # endif 84 84 + #endif 85 85 + #ifdef CONFIG_ARCH_OMAP3430 86 86 + # ifdef OMAP_NAME 87 87 + # undef MULTI_OMAP2 88 88 + # define MULTI_OMAP2 89 89 + # else 90 90 + # define OMAP_NAME omap3430 70 91 # endif 71 92 #endif 72 93 ··· 100 79 * cpu_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430 101 80 * cpu_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423 102 81 * cpu_is_omap243x(): True for OMAP2430 82 82 + * cpu_is_omap343x(): True for OMAP3430 103 83 */ 104 104 - #define GET_OMAP_CLASS (system_rev & 0xff) 84 84 + #define GET_OMAP_CLASS ((system_rev >> 24) & 0xff) 105 85 106 86 #define IS_OMAP_CLASS(class, id) \ 107 87 static inline int is_omap ##class (void) \ ··· 122 100 IS_OMAP_CLASS(15xx, 0x15) 123 101 IS_OMAP_CLASS(16xx, 0x16) 124 102 IS_OMAP_CLASS(24xx, 0x24) 103 103 + IS_OMAP_CLASS(34xx, 0x34) 125 104 126 105 IS_OMAP_SUBCLASS(242x, 0x242) 127 106 IS_OMAP_SUBCLASS(243x, 0x243) 107 107 + IS_OMAP_SUBCLASS(343x, 0x343) 128 108 129 109 #define cpu_is_omap7xx() 0 130 110 #define cpu_is_omap15xx() 0 ··· 134 110 #define cpu_is_omap24xx() 0 135 111 #define cpu_is_omap242x() 0 136 112 #define cpu_is_omap243x() 0 113 113 + #define cpu_is_omap34xx() 0 114 114 + #define cpu_is_omap343x() 0 137 115 138 116 #if defined(MULTI_OMAP1) 139 117 # if defined(CONFIG_ARCH_OMAP730) ··· 163 137 # undef cpu_is_omap16xx 164 138 # define cpu_is_omap16xx() 1 165 139 # endif 140 140 + #endif 141 141 + 142 142 + #if defined(MULTI_OMAP2) 166 143 # if defined(CONFIG_ARCH_OMAP24XX) 167 144 # undef cpu_is_omap24xx 168 145 # undef cpu_is_omap242x 169 146 # undef cpu_is_omap243x 170 170 - # define cpu_is_omap24xx() 1 147 147 + # define cpu_is_omap24xx() is_omap24xx() 171 148 # define cpu_is_omap242x() is_omap242x() 172 149 # define cpu_is_omap243x() is_omap243x() 150 150 + # endif 151 151 + # if defined(CONFIG_ARCH_OMAP34XX) 152 152 + # undef cpu_is_omap34xx 153 153 + # undef cpu_is_omap343x 154 154 + # define cpu_is_omap34xx() is_omap34xx() 155 155 + # define cpu_is_omap343x() is_omap343x() 156 156 + # endif 157 157 + #else 158 158 + # if defined(CONFIG_ARCH_OMAP24XX) 159 159 + # undef cpu_is_omap24xx 160 160 + # define cpu_is_omap24xx() 1 161 161 + # endif 162 162 + # if defined(CONFIG_ARCH_OMAP2420) 163 163 + # undef cpu_is_omap242x 164 164 + # define cpu_is_omap242x() 1 165 165 + # endif 166 166 + # if defined(CONFIG_ARCH_OMAP2430) 167 167 + # undef cpu_is_omap243x 168 168 + # define cpu_is_omap243x() 1 169 169 + # endif 170 170 + # if defined(CONFIG_ARCH_OMAP34XX) 171 171 + # undef cpu_is_omap34xx 172 172 + # define cpu_is_omap34xx() 1 173 173 + # endif 174 174 + # if defined(CONFIG_ARCH_OMAP3430) 175 175 + # undef cpu_is_omap343x 176 176 + # define cpu_is_omap343x() 1 173 177 # endif 174 178 #endif 175 179 ··· 218 162 * cpu_is_omap2422(): True for OMAP2422 219 163 * cpu_is_omap2423(): True for OMAP2423 220 164 * cpu_is_omap2430(): True for OMAP2430 165 165 + * cpu_is_omap3430(): True for OMAP3430 221 166 */ 222 167 #define GET_OMAP_TYPE ((system_rev >> 16) & 0xffff) 223 168 ··· 240 183 IS_OMAP_TYPE(2422, 0x2422) 241 184 IS_OMAP_TYPE(2423, 0x2423) 242 185 IS_OMAP_TYPE(2430, 0x2430) 186 186 + IS_OMAP_TYPE(3430, 0x3430) 243 187 244 188 #define cpu_is_omap310() 0 245 189 #define cpu_is_omap730() 0 ··· 254 196 #define cpu_is_omap2422() 0 255 197 #define cpu_is_omap2423() 0 256 198 #define cpu_is_omap2430() 0 199 199 + #define cpu_is_omap3430() 0 257 200 258 201 #if defined(MULTI_OMAP1) 259 202 # if defined(CONFIG_ARCH_OMAP730) ··· 303 244 # define cpu_is_omap2430() is_omap2430() 304 245 #endif 305 246 247 247 + #if defined(CONFIG_ARCH_OMAP34XX) 248 248 + # undef cpu_is_omap3430 249 249 + # define cpu_is_omap3430() is_omap3430() 250 250 + #endif 251 251 + 306 252 /* Macros to detect if we have OMAP1 or OMAP2 */ 307 253 #define cpu_class_is_omap1() (cpu_is_omap730() || cpu_is_omap15xx() || \ 308 254 cpu_is_omap16xx()) 309 309 - #define cpu_class_is_omap2() cpu_is_omap24xx() 255 255 + #define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx()) 256 256 + 257 257 + #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 258 258 + /* 259 259 + * Macros to detect silicon revision of OMAP2/3 processors. 260 260 + * is_sil_rev_greater_than: true if passed cpu type & its rev is greater. 261 261 + * is_sil_rev_lesser_than: true if passed cpu type & its rev is lesser. 262 262 + * is_sil_rev_equal_to: true if passed cpu type & its rev is equal. 263 263 + * get_sil_rev: return the silicon rev value. 264 264 + */ 265 265 + #define get_sil_omap_type(rev) ((rev & 0xffff0000) >> 16) 266 266 + #define get_sil_revision(rev) ((rev & 0x0000f000) >> 12) 267 267 + 268 268 + #define is_sil_rev_greater_than(rev) \ 269 269 + ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \ 270 270 + (get_sil_revision(system_rev) > get_sil_revision(rev))) 271 271 + 272 272 + #define is_sil_rev_less_than(rev) \ 273 273 + ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \ 274 274 + (get_sil_revision(system_rev) < get_sil_revision(rev))) 275 275 + 276 276 + #define is_sil_rev_equal_to(rev) \ 277 277 + ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \ 278 278 + (get_sil_revision(system_rev) == get_sil_revision(rev))) 279 279 + 280 280 + #define get_sil_rev() \ 281 281 + get_sil_revision(system_rev) 282 282 + 283 283 + /* Various silicon macros defined here */ 284 284 + #define OMAP2420_REV_ES1_0 0x24200000 285 285 + #define OMAP2420_REV_ES2_0 0x24201000 286 286 + #define OMAP2430_REV_ES1_0 0x24300000 287 287 + #define OMAP3430_REV_ES1_0 0x34300000 288 288 + #define OMAP3430_REV_ES2_0 0x34301000 289 289 + 290 290 + /* 291 291 + * Macro to detect device type i.e. EMU/HS/TST/GP/BAD 292 292 + */ 293 293 + #define DEVICE_TYPE_TEST 0 294 294 + #define DEVICE_TYPE_EMU 1 295 295 + #define DEVICE_TYPE_SEC 2 296 296 + #define DEVICE_TYPE_GP 3 297 297 + #define DEVICE_TYPE_BAD 4 298 298 + 299 299 + #define get_device_type() ((system_rev & 0x700) >> 8) 300 300 + #define is_device_type_test() (get_device_type() == DEVICE_TYPE_TEST) 301 301 + #define is_device_type_emu() (get_device_type() == DEVICE_TYPE_EMU) 302 302 + #define is_device_type_sec() (get_device_type() == DEVICE_TYPE_SEC) 303 303 + #define is_device_type_gp() (get_device_type() == DEVICE_TYPE_GP) 304 304 + #define is_device_type_bad() (get_device_type() == DEVICE_TYPE_BAD) 305 305 + 306 306 + #endif 310 307 311 308 #endif

+101 -34

include/asm-arm/arch-omap/dma.h

reviewed

··· 45 45 #define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0) 46 46 47 47 /* Hardware registers for omap2 */ 48 48 - #define OMAP24XX_DMA_BASE (L4_24XX_BASE + 0x56000) 49 49 - #define OMAP_DMA4_REVISION (OMAP24XX_DMA_BASE + 0x00) 50 50 - #define OMAP_DMA4_GCR_REG (OMAP24XX_DMA_BASE + 0x78) 51 51 - #define OMAP_DMA4_IRQSTATUS_L0 (OMAP24XX_DMA_BASE + 0x08) 52 52 - #define OMAP_DMA4_IRQSTATUS_L1 (OMAP24XX_DMA_BASE + 0x0c) 53 53 - #define OMAP_DMA4_IRQSTATUS_L2 (OMAP24XX_DMA_BASE + 0x10) 54 54 - #define OMAP_DMA4_IRQSTATUS_L3 (OMAP24XX_DMA_BASE + 0x14) 55 55 - #define OMAP_DMA4_IRQENABLE_L0 (OMAP24XX_DMA_BASE + 0x18) 56 56 - #define OMAP_DMA4_IRQENABLE_L1 (OMAP24XX_DMA_BASE + 0x1c) 57 57 - #define OMAP_DMA4_IRQENABLE_L2 (OMAP24XX_DMA_BASE + 0x20) 58 58 - #define OMAP_DMA4_IRQENABLE_L3 (OMAP24XX_DMA_BASE + 0x24) 59 59 - #define OMAP_DMA4_SYSSTATUS (OMAP24XX_DMA_BASE + 0x28) 60 60 - #define OMAP_DMA4_CAPS_0 (OMAP24XX_DMA_BASE + 0x64) 61 61 - #define OMAP_DMA4_CAPS_2 (OMAP24XX_DMA_BASE + 0x6c) 62 62 - #define OMAP_DMA4_CAPS_3 (OMAP24XX_DMA_BASE + 0x70) 63 63 - #define OMAP_DMA4_CAPS_4 (OMAP24XX_DMA_BASE + 0x74) 48 48 + #if defined(CONFIG_ARCH_OMAP3) 49 49 + #define OMAP_DMA4_BASE (L4_34XX_BASE + 0x56000) 50 50 + #else /* CONFIG_ARCH_OMAP2 */ 51 51 + #define OMAP_DMA4_BASE (L4_24XX_BASE + 0x56000) 52 52 + #endif 53 53 + 54 54 + #define OMAP_DMA4_REVISION (OMAP_DMA4_BASE + 0x00) 55 55 + #define OMAP_DMA4_GCR_REG (OMAP_DMA4_BASE + 0x78) 56 56 + #define OMAP_DMA4_IRQSTATUS_L0 (OMAP_DMA4_BASE + 0x08) 57 57 + #define OMAP_DMA4_IRQSTATUS_L1 (OMAP_DMA4_BASE + 0x0c) 58 58 + #define OMAP_DMA4_IRQSTATUS_L2 (OMAP_DMA4_BASE + 0x10) 59 59 + #define OMAP_DMA4_IRQSTATUS_L3 (OMAP_DMA4_BASE + 0x14) 60 60 + #define OMAP_DMA4_IRQENABLE_L0 (OMAP_DMA4_BASE + 0x18) 61 61 + #define OMAP_DMA4_IRQENABLE_L1 (OMAP_DMA4_BASE + 0x1c) 62 62 + #define OMAP_DMA4_IRQENABLE_L2 (OMAP_DMA4_BASE + 0x20) 63 63 + #define OMAP_DMA4_IRQENABLE_L3 (OMAP_DMA4_BASE + 0x24) 64 64 + #define OMAP_DMA4_SYSSTATUS (OMAP_DMA4_BASE + 0x28) 65 65 + #define OMAP_DMA4_OCP_SYSCONFIG (OMAP_DMA4_BASE + 0x2c) 66 66 + #define OMAP_DMA4_CAPS_0 (OMAP_DMA4_BASE + 0x64) 67 67 + #define OMAP_DMA4_CAPS_2 (OMAP_DMA4_BASE + 0x6c) 68 68 + #define OMAP_DMA4_CAPS_3 (OMAP_DMA4_BASE + 0x70) 69 69 + #define OMAP_DMA4_CAPS_4 (OMAP_DMA4_BASE + 0x74) 64 70 65 71 #ifdef CONFIG_ARCH_OMAP1 66 72 ··· 92 86 #define OMAP_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */ 93 87 94 88 /* Common channel specific registers for omap2 */ 95 95 - #define OMAP_DMA_CCR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x80) 96 96 - #define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x84) 97 97 - #define OMAP_DMA_CICR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x88) 98 98 - #define OMAP_DMA_CSR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x8c) 99 99 - #define OMAP_DMA_CSDP_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x90) 100 100 - #define OMAP_DMA_CEN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x94) 101 101 - #define OMAP_DMA_CFN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x98) 102 102 - #define OMAP_DMA_CSEI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa4) 103 103 - #define OMAP_DMA_CSFI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa8) 104 104 - #define OMAP_DMA_CDEI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xac) 105 105 - #define OMAP_DMA_CDFI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb0) 106 106 - #define OMAP_DMA_CSAC_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb4) 107 107 - #define OMAP_DMA_CDAC_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb8) 89 89 + #define OMAP_DMA_CCR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x80) 90 90 + #define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x84) 91 91 + #define OMAP_DMA_CICR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x88) 92 92 + #define OMAP_DMA_CSR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x8c) 93 93 + #define OMAP_DMA_CSDP_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x90) 94 94 + #define OMAP_DMA_CEN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x94) 95 95 + #define OMAP_DMA_CFN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x98) 96 96 + #define OMAP_DMA_CSEI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa4) 97 97 + #define OMAP_DMA_CSFI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa8) 98 98 + #define OMAP_DMA_CDEI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xac) 99 99 + #define OMAP_DMA_CDFI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb0) 100 100 + #define OMAP_DMA_CSAC_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb4) 101 101 + #define OMAP_DMA_CDAC_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb8) 108 102 109 103 #endif 110 104 ··· 119 113 #define OMAP1_DMA_LCH_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a) 120 114 121 115 /* Channel specific registers only on omap2 */ 122 122 - #define OMAP2_DMA_CSSA_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x9c) 123 123 - #define OMAP2_DMA_CDSA_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa0) 124 124 - #define OMAP2_DMA_CCEN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xbc) 125 125 - #define OMAP2_DMA_CCFN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc0) 126 126 - #define OMAP2_DMA_COLOR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc4) 116 116 + #define OMAP2_DMA_CSSA_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x9c) 117 117 + #define OMAP2_DMA_CDSA_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa0) 118 118 + #define OMAP2_DMA_CCEN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xbc) 119 119 + #define OMAP2_DMA_CCFN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc0) 120 120 + #define OMAP2_DMA_COLOR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc4) 127 121 128 122 /*----------------------------------------------------------------------------*/ 129 123 ··· 303 297 #define OMAP_DMA_SYNC_ELEMENT 0x00 304 298 #define OMAP_DMA_SYNC_FRAME 0x01 305 299 #define OMAP_DMA_SYNC_BLOCK 0x02 300 300 + #define OMAP_DMA_SYNC_PACKET 0x03 301 301 + 302 302 + #define OMAP_DMA_SRC_SYNC 0x01 303 303 + #define OMAP_DMA_DST_SYNC 0x00 306 304 307 305 #define OMAP_DMA_PORT_EMIFF 0x00 308 306 #define OMAP_DMA_PORT_EMIFS 0x01 ··· 319 309 #define OMAP_DMA_AMODE_POST_INC 0x01 320 310 #define OMAP_DMA_AMODE_SINGLE_IDX 0x02 321 311 #define OMAP_DMA_AMODE_DOUBLE_IDX 0x03 312 312 + 313 313 + #define DMA_DEFAULT_FIFO_DEPTH 0x10 314 314 + #define DMA_DEFAULT_ARB_RATE 0x01 315 315 + /* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */ 316 316 + #define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */ 317 317 + #define DMA_THREAD_RESERVE_ONET (0x01 << 12) 318 318 + #define DMA_THREAD_RESERVE_TWOT (0x02 << 12) 319 319 + #define DMA_THREAD_RESERVE_THREET (0x03 << 12) 320 320 + #define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */ 321 321 + #define DMA_THREAD_FIFO_75 (0x01 << 14) 322 322 + #define DMA_THREAD_FIFO_25 (0x02 << 14) 323 323 + #define DMA_THREAD_FIFO_50 (0x03 << 14) 324 324 + 325 325 + /* Chaining modes*/ 326 326 + #ifndef CONFIG_ARCH_OMAP1 327 327 + #define OMAP_DMA_STATIC_CHAIN 0x1 328 328 + #define OMAP_DMA_DYNAMIC_CHAIN 0x2 329 329 + #define OMAP_DMA_CHAIN_ACTIVE 0x1 330 330 + #define OMAP_DMA_CHAIN_INACTIVE 0x0 331 331 + #endif 332 332 + 333 333 + #define DMA_CH_PRIO_HIGH 0x1 334 334 + #define DMA_CH_PRIO_LOW 0x0 /* Def */ 322 335 323 336 /* LCD DMA block numbers */ 324 337 enum { ··· 392 359 int src_or_dst_synch; /* source synch(1) or destination synch(0) */ 393 360 394 361 int ie; /* interrupt enabled */ 362 362 + 363 363 + unsigned char read_prio;/* read priority */ 364 364 + unsigned char write_prio;/* write priority */ 365 365 + 366 366 + #ifndef CONFIG_ARCH_OMAP1 367 367 + enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */ 368 368 + #endif 395 369 }; 396 370 397 371 ··· 449 409 extern int omap_get_dma_src_addr_counter(int lch); 450 410 extern void omap_clear_dma(int lch); 451 411 extern int omap_dma_running(void); 412 412 + extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth, 413 413 + int tparams); 414 414 + extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio, 415 415 + unsigned char write_prio); 416 416 + 417 417 + /* Chaining APIs */ 418 418 + #ifndef CONFIG_ARCH_OMAP1 419 419 + extern int omap_request_dma_chain(int dev_id, const char *dev_name, 420 420 + void (*callback) (int chain_id, u16 ch_status, 421 421 + void *data), 422 422 + int *chain_id, int no_of_chans, 423 423 + int chain_mode, 424 424 + struct omap_dma_channel_params params); 425 425 + extern int omap_free_dma_chain(int chain_id); 426 426 + extern int omap_dma_chain_a_transfer(int chain_id, int src_start, 427 427 + int dest_start, int elem_count, 428 428 + int frame_count, void *callbk_data); 429 429 + extern int omap_start_dma_chain_transfers(int chain_id); 430 430 + extern int omap_stop_dma_chain_transfers(int chain_id); 431 431 + extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi); 432 432 + extern int omap_get_dma_chain_dst_pos(int chain_id); 433 433 + extern int omap_get_dma_chain_src_pos(int chain_id); 434 434 + 435 435 + extern int omap_modify_dma_chain_params(int chain_id, 436 436 + struct omap_dma_channel_params params); 437 437 + extern int omap_dma_chain_status(int chain_id); 438 438 + #endif 452 439 453 440 /* LCD DMA functions */ 454 441 extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data),

+4

include/asm-arm/arch-omap/gpio.h

reviewed

··· 62 62 #define OMAP_MPUIO_LATCH 0x34 63 63 #endif 64 64 65 65 + #define OMAP34XX_NR_GPIOS 6 66 66 + 65 67 #define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr)) 66 68 #define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES) 67 69 ··· 77 75 extern void omap_set_gpio_direction(int gpio, int is_input); 78 76 extern void omap_set_gpio_dataout(int gpio, int enable); 79 77 extern int omap_get_gpio_datain(int gpio); 78 78 + extern void omap_set_gpio_debounce(int gpio, int enable); 79 79 + extern void omap_set_gpio_debounce_time(int gpio, int enable); 80 80 81 81 /*-------------------------------------------------------------------------*/ 82 82

+2

include/asm-arm/arch-omap/irqs.h

reviewed

··· 263 263 #define INT_24XX_GPTIMER10 46 264 264 #define INT_24XX_GPTIMER11 47 265 265 #define INT_24XX_GPTIMER12 48 266 266 + #define INT_24XX_I2C1_IRQ 56 267 267 + #define INT_24XX_I2C2_IRQ 57 266 268 #define INT_24XX_MCBSP1_IRQ_TX 59 267 269 #define INT_24XX_MCBSP1_IRQ_RX 60 268 270 #define INT_24XX_MCBSP2_IRQ_TX 62

+24

include/asm-arm/arch-omap/nand.h

reviewed

··· 1 1 + /* 2 2 + * include/asm-arm/arch-omap/nand.h 3 3 + * 4 4 + * Copyright (C) 2006 Micron Technology Inc. 5 5 + * 6 6 + * This program is free software; you can redistribute it and/or modify 7 7 + * it under the terms of the GNU General Public License version 2 as 8 8 + * published by the Free Software Foundation. 9 9 + */ 10 10 + 11 11 + #include <linux/mtd/partitions.h> 12 12 + 13 13 + struct omap_nand_platform_data { 14 14 + unsigned int options; 15 15 + int cs; 16 16 + int gpio_irq; 17 17 + struct mtd_partition *parts; 18 18 + int nr_parts; 19 19 + int (*nand_setup)(void __iomem *); 20 20 + int (*dev_ready)(struct omap_nand_platform_data *); 21 21 + int dma_channel; 22 22 + void __iomem *gpmc_cs_baseaddr; 23 23 + void __iomem *gpmc_baseaddr; 24 24 + };

+7 -2

include/asm-arm/arch-orion/debug-macro.S

reviewed

··· 8 8 * published by the Free Software Foundation. 9 9 */ 10 10 11 11 + #include <asm/arch/orion.h> 12 12 + 11 13 .macro addruart,rx 12 12 - mov \rx, #0xf1000000 13 13 - orr \rx, \rx, #0x00012000 14 14 + mrc p15, 0, \rx, c1, c0 15 15 + tst \rx, #1 @ MMU enabled? 16 16 + ldreq \rx, =ORION_REGS_PHYS_BASE 17 17 + ldrne \rx, =ORION_REGS_VIRT_BASE 18 18 + orr \rx, \rx, #0x00012000 14 19 .endm 15 20 16 21 #define UART_SHIFT 2

+2 -2

include/asm-arm/arch-orion/entry-macro.S

reviewed

··· 3 3 * 4 4 * Low-level IRQ helper macros for Orion platforms 5 5 * 6 6 - * This file is licensed under the terms of the GNU General Public 7 7 - * License version 2. This program is licensed "as is" without any 6 6 + * This file is licensed under the terms of the GNU General Public 7 7 + * License version 2. This program is licensed "as is" without any 8 8 * warranty of any kind, whether express or implied. 9 9 */ 10 10

+5 -8

include/asm-arm/arch-orion/hardware.h

reviewed

··· 4 4 * This program is free software; you can redistribute it and/or modify 5 5 * it under the terms of the GNU General Public License version 2 as 6 6 * published by the Free Software Foundation. 7 7 - * 8 7 */ 9 8 10 9 #ifndef __ASM_ARCH_HARDWARE_H__ ··· 11 12 12 13 #include "orion.h" 13 14 14 14 - #define PCI_MEMORY_VADDR ORION_PCI_SYS_MEM_BASE 15 15 - #define PCI_IO_VADDR ORION_PCI_SYS_IO_BASE 15 15 + #define pcibios_assign_all_busses() 1 16 16 17 17 - #define pcibios_assign_all_busses() 1 17 17 + #define PCIBIOS_MIN_IO 0x00001000 18 18 + #define PCIBIOS_MIN_MEM 0x01000000 19 19 + #define PCIMEM_BASE ORION_PCIE_MEM_PHYS_BASE 18 20 19 19 - #define PCIBIOS_MIN_IO 0x1000 20 20 - #define PCIBIOS_MIN_MEM 0x01000000 21 21 - #define PCIMEM_BASE PCI_MEMORY_VADDR /* mem base for VGA */ 22 21 23 23 - #endif /* _ASM_ARCH_HARDWARE_H */ 22 22 + #endif

+61 -39

include/asm-arm/arch-orion/orion.h

reviewed

··· 14 14 #ifndef __ASM_ARCH_ORION_H__ 15 15 #define __ASM_ARCH_ORION_H__ 16 16 17 17 - /******************************************************************************* 17 17 + /***************************************************************************** 18 18 * Orion Address Map 19 19 - * Use the same mapping (1:1 virtual:physical) of internal registers and 20 20 - * PCI system (PCI+PCIE) for all machines. 21 21 - * Each machine defines the rest of its mapping (e.g. device bus flashes) 22 22 - ******************************************************************************/ 23 23 - #define ORION_REGS_BASE 0xf1000000 19 19 + * 20 20 + * virt phys size 21 21 + * fdd00000 f1000000 1M on-chip peripheral registers 22 22 + * fde00000 f2000000 1M PCIe I/O space 23 23 + * fdf00000 f2100000 1M PCI I/O space 24 24 + * fe000000 f0000000 16M PCIe WA space (Orion-NAS only) 25 25 + ****************************************************************************/ 26 26 + #define ORION_REGS_PHYS_BASE 0xf1000000 27 27 + #define ORION_REGS_VIRT_BASE 0xfdd00000 24 28 #define ORION_REGS_SIZE SZ_1M 25 29 26 26 - #define ORION_PCI_SYS_MEM_BASE 0xe0000000 27 27 - #define ORION_PCIE_MEM_BASE ORION_PCI_SYS_MEM_BASE 28 28 - #define ORION_PCIE_MEM_SIZE SZ_128M 29 29 - #define ORION_PCI_MEM_BASE (ORION_PCIE_MEM_BASE + ORION_PCIE_MEM_SIZE) 30 30 - #define ORION_PCI_MEM_SIZE SZ_128M 31 31 - 32 32 - #define ORION_PCI_SYS_IO_BASE 0xf2000000 33 33 - #define ORION_PCIE_IO_BASE ORION_PCI_SYS_IO_BASE 30 30 + #define ORION_PCIE_IO_PHYS_BASE 0xf2000000 31 31 + #define ORION_PCIE_IO_VIRT_BASE 0xfde00000 32 32 + #define ORION_PCIE_IO_BUS_BASE 0x00000000 34 33 #define ORION_PCIE_IO_SIZE SZ_1M 35 35 - #define ORION_PCIE_IO_REMAP (ORION_PCIE_IO_BASE - ORION_PCI_SYS_IO_BASE) 36 36 - #define ORION_PCI_IO_BASE (ORION_PCIE_IO_BASE + ORION_PCIE_IO_SIZE) 34 34 + 35 35 + #define ORION_PCI_IO_PHYS_BASE 0xf2100000 36 36 + #define ORION_PCI_IO_VIRT_BASE 0xfdf00000 37 37 + #define ORION_PCI_IO_BUS_BASE 0x00100000 37 38 #define ORION_PCI_IO_SIZE SZ_1M 38 38 - #define ORION_PCI_IO_REMAP (ORION_PCI_IO_BASE - ORION_PCI_SYS_IO_BASE) 39 39 + 39 40 /* Relevant only for Orion-NAS */ 40 40 - #define ORION_PCIE_WA_BASE 0xf0000000 41 41 + #define ORION_PCIE_WA_PHYS_BASE 0xf0000000 42 42 + #define ORION_PCIE_WA_VIRT_BASE 0xfe000000 41 43 #define ORION_PCIE_WA_SIZE SZ_16M 44 44 + 45 45 + #define ORION_PCIE_MEM_PHYS_BASE 0xe0000000 46 46 + #define ORION_PCIE_MEM_SIZE SZ_128M 47 47 + 48 48 + #define ORION_PCI_MEM_PHYS_BASE 0xe8000000 49 49 + #define ORION_PCI_MEM_SIZE SZ_128M 42 50 43 51 /******************************************************************************* 44 52 * Supported Devices & Revisions ··· 65 57 /******************************************************************************* 66 58 * Orion Registers Map 67 59 ******************************************************************************/ 68 68 - #define ORION_DDR_REG_BASE (ORION_REGS_BASE | 0x00000) 69 69 - #define ORION_DEV_BUS_REG_BASE (ORION_REGS_BASE | 0x10000) 70 70 - #define ORION_BRIDGE_REG_BASE (ORION_REGS_BASE | 0x20000) 71 71 - #define ORION_PCI_REG_BASE (ORION_REGS_BASE | 0x30000) 72 72 - #define ORION_PCIE_REG_BASE (ORION_REGS_BASE | 0x40000) 73 73 - #define ORION_USB0_REG_BASE (ORION_REGS_BASE | 0x50000) 74 74 - #define ORION_ETH_REG_BASE (ORION_REGS_BASE | 0x70000) 75 75 - #define ORION_SATA_REG_BASE (ORION_REGS_BASE | 0x80000) 76 76 - #define ORION_USB1_REG_BASE (ORION_REGS_BASE | 0xa0000) 60 60 + #define ORION_DDR_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x00000) 61 61 + #define ORION_DDR_REG(x) (ORION_DDR_VIRT_BASE | (x)) 77 62 78 78 - #define ORION_DDR_REG(x) (ORION_DDR_REG_BASE | (x)) 79 79 - #define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_REG_BASE | (x)) 80 80 - #define ORION_BRIDGE_REG(x) (ORION_BRIDGE_REG_BASE | (x)) 81 81 - #define ORION_PCI_REG(x) (ORION_PCI_REG_BASE | (x)) 82 82 - #define ORION_PCIE_REG(x) (ORION_PCIE_REG_BASE | (x)) 83 83 - #define ORION_USB0_REG(x) (ORION_USB0_REG_BASE | (x)) 84 84 - #define ORION_USB1_REG(x) (ORION_USB1_REG_BASE | (x)) 85 85 - #define ORION_ETH_REG(x) (ORION_ETH_REG_BASE | (x)) 86 86 - #define ORION_SATA_REG(x) (ORION_SATA_REG_BASE | (x)) 63 63 + #define ORION_DEV_BUS_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x10000) 64 64 + #define ORION_DEV_BUS_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x10000) 65 65 + #define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_VIRT_BASE | (x)) 66 66 + #define I2C_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x1000) 67 67 + #define UART0_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2000) 68 68 + #define UART0_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2000) 69 69 + #define UART1_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2100) 70 70 + #define UART1_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2100) 71 71 + 72 72 + #define ORION_BRIDGE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x20000) 73 73 + #define ORION_BRIDGE_REG(x) (ORION_BRIDGE_VIRT_BASE | (x)) 74 74 + 75 75 + #define ORION_PCI_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x30000) 76 76 + #define ORION_PCI_REG(x) (ORION_PCI_VIRT_BASE | (x)) 77 77 + 78 78 + #define ORION_PCIE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x40000) 79 79 + #define ORION_PCIE_REG(x) (ORION_PCIE_VIRT_BASE | (x)) 80 80 + 81 81 + #define ORION_USB0_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x50000) 82 82 + #define ORION_USB0_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x50000) 83 83 + #define ORION_USB0_REG(x) (ORION_USB0_VIRT_BASE | (x)) 84 84 + 85 85 + #define ORION_ETH_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x70000) 86 86 + #define ORION_ETH_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x70000) 87 87 + #define ORION_ETH_REG(x) (ORION_ETH_VIRT_BASE | (x)) 88 88 + 89 89 + #define ORION_SATA_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x80000) 90 90 + #define ORION_SATA_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x80000) 91 91 + #define ORION_SATA_REG(x) (ORION_SATA_VIRT_BASE | (x)) 92 92 + 93 93 + #define ORION_USB1_PHYS_BASE (ORION_REGS_PHYS_BASE | 0xa0000) 94 94 + #define ORION_USB1_VIRT_BASE (ORION_REGS_VIRT_BASE | 0xa0000) 95 95 + #define ORION_USB1_REG(x) (ORION_USB1_VIRT_BASE | (x)) 87 96 88 97 /******************************************************************************* 89 98 * Device Bus Registers ··· 125 100 #define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0) 126 101 #define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0) 127 102 #define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4) 128 128 - #define I2C_BASE ORION_DEV_BUS_REG(0x1000) 129 129 - #define UART0_BASE ORION_DEV_BUS_REG(0x2000) 130 130 - #define UART1_BASE ORION_DEV_BUS_REG(0x2100) 131 103 #define GPIO_MAX 32 132 104 133 105 /***************************************************************************

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include/asm-arm/arch-orion/uncompress.h

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··· 10 10 11 11 #include <asm/arch/orion.h> 12 12 13 13 - #define MV_UART_LSR ((volatile unsigned char *)(UART0_BASE + 0x14)) 14 14 - #define MV_UART_THR ((volatile unsigned char *)(UART0_BASE + 0x0)) 13 13 + #define MV_UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0)) 14 14 + #define MV_UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14)) 15 15 16 16 #define LSR_THRE 0x20 17 17 ··· 25 25 26 26 static void flush(void) 27 27 { 28 28 - } 29 29 - 30 30 - static void orion_early_putstr(const char *ptr) 31 31 - { 32 32 - char c; 33 33 - while ((c = *ptr++) != '\0') { 34 34 - if (c == '\n') 35 35 - putc('\r'); 36 36 - putc(c); 37 37 - } 38 28 } 39 29 40 30 /*

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include/asm-arm/arch-orion/vmalloc.h

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··· 2 2 * include/asm-arm/arch-orion/vmalloc.h 3 3 */ 4 4 5 5 - #define VMALLOC_END 0xf0000000 5 5 + #define VMALLOC_END 0xfd800000