Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/ast: Move Gen4+ POST code to separate source file
Move POST code for Gen4+ to separate source file and hide it in
ast_2300_post(). With P2A configuration, it performs a full board
POST and enables the transmitter chip; otherwise it only enables the
transmitter chip.
Also fix coding style in several places. No changes to the overall
logic.
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com>
Link: https://lore.kernel.org/r/20250706162816.211552-5-tzimmermann@suse.de
+1302
-1262
+1
drivers/gpu/drm/ast/Makefile
+1
drivers/gpu/drm/ast/Makefile
+1295
drivers/gpu/drm/ast/ast_2300.c
+1295
drivers/gpu/drm/ast/ast_2300.c
···
1
+
// SPDX-License-Identifier: MIT
2
+
/*
3
+
* Copyright 2012 Red Hat Inc.
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+
*
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* Permission is hereby granted, free of charge, to any person obtaining a
6
+
* copy of this software and associated documentation files (the
7
+
* "Software"), to deal in the Software without restriction, including
8
+
* without limitation the rights to use, copy, modify, merge, publish,
9
+
* distribute, sub license, and/or sell copies of the Software, and to
10
+
* permit persons to whom the Software is furnished to do so, subject to
11
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* the following conditions:
12
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*
13
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15
+
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17
+
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18
+
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19
+
* USE OR OTHER DEALINGS IN THE SOFTWARE.
20
+
*
21
+
* The above copyright notice and this permission notice (including the
22
+
* next paragraph) shall be included in all copies or substantial portions
23
+
* of the Software.
24
+
*/
25
+
/*
26
+
* Authors: Dave Airlie <airlied@redhat.com>
27
+
*/
28
+
29
+
#include <linux/delay.h>
30
+
31
+
#include "ast_drv.h"
32
+
#include "ast_post.h"
33
+
34
+
/*
35
+
* POST
36
+
*/
37
+
38
+
/* AST 2300 DRAM settings */
39
+
#define AST_DDR3 0
40
+
#define AST_DDR2 1
41
+
42
+
struct ast2300_dram_param {
43
+
u32 dram_type;
44
+
u32 dram_chipid;
45
+
u32 dram_freq;
46
+
u32 vram_size;
47
+
u32 odt;
48
+
u32 wodt;
49
+
u32 rodt;
50
+
u32 dram_config;
51
+
u32 reg_PERIOD;
52
+
u32 reg_MADJ;
53
+
u32 reg_SADJ;
54
+
u32 reg_MRS;
55
+
u32 reg_EMRS;
56
+
u32 reg_AC1;
57
+
u32 reg_AC2;
58
+
u32 reg_DQSIC;
59
+
u32 reg_DRV;
60
+
u32 reg_IOZ;
61
+
u32 reg_DQIDLY;
62
+
u32 reg_FREQ;
63
+
u32 madj_max;
64
+
u32 dll2_finetune_step;
65
+
};
66
+
67
+
/*
68
+
* DQSI DLL CBR Setting
69
+
*/
70
+
#define CBR_SIZE0 ((1 << 10) - 1)
71
+
#define CBR_SIZE1 ((4 << 10) - 1)
72
+
#define CBR_SIZE2 ((64 << 10) - 1)
73
+
#define CBR_PASSNUM 5
74
+
#define CBR_PASSNUM2 5
75
+
#define CBR_THRESHOLD 10
76
+
#define CBR_THRESHOLD2 10
77
+
#define TIMEOUT 5000000
78
+
#define CBR_PATNUM 8
79
+
80
+
static const u32 pattern[8] = {
81
+
0xFF00FF00,
82
+
0xCC33CC33,
83
+
0xAA55AA55,
84
+
0x88778877,
85
+
0x92CC4D6E,
86
+
0x543D3CDE,
87
+
0xF1E843C7,
88
+
0x7C61D253
89
+
};
90
+
91
+
static u32 mmc_test2(struct ast_device *ast, u32 datagen, u8 test_ctl)
92
+
{
93
+
u32 data, timeout;
94
+
95
+
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
96
+
ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
97
+
timeout = 0;
98
+
do {
99
+
data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
100
+
if (++timeout > TIMEOUT) {
101
+
ast_moutdwm(ast, 0x1e6e0070, 0x0);
102
+
return 0xffffffff;
103
+
}
104
+
} while (!data);
105
+
data = ast_mindwm(ast, 0x1e6e0078);
106
+
data = (data | (data >> 16)) & 0xffff;
107
+
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
108
+
return data;
109
+
}
110
+
111
+
static u32 mmc_test_burst2(struct ast_device *ast, u32 datagen)
112
+
{
113
+
return mmc_test2(ast, datagen, 0x41);
114
+
}
115
+
116
+
static bool mmc_test_single(struct ast_device *ast, u32 datagen)
117
+
{
118
+
return mmc_test(ast, datagen, 0xc5);
119
+
}
120
+
121
+
static u32 mmc_test_single2(struct ast_device *ast, u32 datagen)
122
+
{
123
+
return mmc_test2(ast, datagen, 0x05);
124
+
}
125
+
126
+
static int cbr_test(struct ast_device *ast)
127
+
{
128
+
u32 data;
129
+
int i;
130
+
131
+
data = mmc_test_single2(ast, 0);
132
+
if ((data & 0xff) && (data & 0xff00))
133
+
return 0;
134
+
for (i = 0; i < 8; i++) {
135
+
data = mmc_test_burst2(ast, i);
136
+
if ((data & 0xff) && (data & 0xff00))
137
+
return 0;
138
+
}
139
+
if (!data)
140
+
return 3;
141
+
else if (data & 0xff)
142
+
return 2;
143
+
return 1;
144
+
}
145
+
146
+
static int cbr_scan(struct ast_device *ast)
147
+
{
148
+
u32 data, data2, patcnt, loop;
149
+
150
+
data2 = 3;
151
+
for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
152
+
ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
153
+
for (loop = 0; loop < CBR_PASSNUM2; loop++) {
154
+
data = cbr_test(ast);
155
+
if (data != 0) {
156
+
data2 &= data;
157
+
if (!data2)
158
+
return 0;
159
+
break;
160
+
}
161
+
}
162
+
if (loop == CBR_PASSNUM2)
163
+
return 0;
164
+
}
165
+
return data2;
166
+
}
167
+
168
+
static u32 cbr_test2(struct ast_device *ast)
169
+
{
170
+
u32 data;
171
+
172
+
data = mmc_test_burst2(ast, 0);
173
+
if (data == 0xffff)
174
+
return 0;
175
+
data |= mmc_test_single2(ast, 0);
176
+
if (data == 0xffff)
177
+
return 0;
178
+
179
+
return ~data & 0xffff;
180
+
}
181
+
182
+
static u32 cbr_scan2(struct ast_device *ast)
183
+
{
184
+
u32 data, data2, patcnt, loop;
185
+
186
+
data2 = 0xffff;
187
+
for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
188
+
ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
189
+
for (loop = 0; loop < CBR_PASSNUM2; loop++) {
190
+
data = cbr_test2(ast);
191
+
if (data != 0) {
192
+
data2 &= data;
193
+
if (!data2)
194
+
return 0;
195
+
break;
196
+
}
197
+
}
198
+
if (loop == CBR_PASSNUM2)
199
+
return 0;
200
+
}
201
+
return data2;
202
+
}
203
+
204
+
static bool cbr_test3(struct ast_device *ast)
205
+
{
206
+
if (!mmc_test_burst(ast, 0))
207
+
return false;
208
+
if (!mmc_test_single(ast, 0))
209
+
return false;
210
+
return true;
211
+
}
212
+
213
+
static bool cbr_scan3(struct ast_device *ast)
214
+
{
215
+
u32 patcnt, loop;
216
+
217
+
for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
218
+
ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
219
+
for (loop = 0; loop < 2; loop++) {
220
+
if (cbr_test3(ast))
221
+
break;
222
+
}
223
+
if (loop == 2)
224
+
return false;
225
+
}
226
+
return true;
227
+
}
228
+
229
+
static bool finetuneDQI_L(struct ast_device *ast, struct ast2300_dram_param *param)
230
+
{
231
+
u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, retry = 0;
232
+
bool status = false;
233
+
FINETUNE_START:
234
+
for (cnt = 0; cnt < 16; cnt++) {
235
+
dllmin[cnt] = 0xff;
236
+
dllmax[cnt] = 0x0;
237
+
}
238
+
passcnt = 0;
239
+
for (dlli = 0; dlli < 76; dlli++) {
240
+
ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
241
+
ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE1);
242
+
data = cbr_scan2(ast);
243
+
if (data != 0) {
244
+
mask = 0x00010001;
245
+
for (cnt = 0; cnt < 16; cnt++) {
246
+
if (data & mask) {
247
+
if (dllmin[cnt] > dlli)
248
+
dllmin[cnt] = dlli;
249
+
if (dllmax[cnt] < dlli)
250
+
dllmax[cnt] = dlli;
251
+
}
252
+
mask <<= 1;
253
+
}
254
+
passcnt++;
255
+
} else if (passcnt >= CBR_THRESHOLD2) {
256
+
break;
257
+
}
258
+
}
259
+
gold_sadj[0] = 0x0;
260
+
passcnt = 0;
261
+
for (cnt = 0; cnt < 16; cnt++) {
262
+
if ((dllmax[cnt] > dllmin[cnt]) &&
263
+
((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
264
+
gold_sadj[0] += dllmin[cnt];
265
+
passcnt++;
266
+
}
267
+
}
268
+
if (retry++ > 10)
269
+
goto FINETUNE_DONE;
270
+
if (passcnt != 16)
271
+
goto FINETUNE_START;
272
+
status = true;
273
+
FINETUNE_DONE:
274
+
gold_sadj[0] = gold_sadj[0] >> 4;
275
+
gold_sadj[1] = gold_sadj[0];
276
+
277
+
data = 0;
278
+
for (cnt = 0; cnt < 8; cnt++) {
279
+
data >>= 3;
280
+
if ((dllmax[cnt] > dllmin[cnt]) &&
281
+
((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
282
+
dlli = dllmin[cnt];
283
+
if (gold_sadj[0] >= dlli) {
284
+
dlli = ((gold_sadj[0] - dlli) * 19) >> 5;
285
+
if (dlli > 3)
286
+
dlli = 3;
287
+
} else {
288
+
dlli = ((dlli - gold_sadj[0]) * 19) >> 5;
289
+
if (dlli > 4)
290
+
dlli = 4;
291
+
dlli = (8 - dlli) & 0x7;
292
+
}
293
+
data |= dlli << 21;
294
+
}
295
+
}
296
+
ast_moutdwm(ast, 0x1E6E0080, data);
297
+
298
+
data = 0;
299
+
for (cnt = 8; cnt < 16; cnt++) {
300
+
data >>= 3;
301
+
if ((dllmax[cnt] > dllmin[cnt]) &&
302
+
((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
303
+
dlli = dllmin[cnt];
304
+
if (gold_sadj[1] >= dlli) {
305
+
dlli = ((gold_sadj[1] - dlli) * 19) >> 5;
306
+
if (dlli > 3)
307
+
dlli = 3;
308
+
else
309
+
dlli = (dlli - 1) & 0x7;
310
+
} else {
311
+
dlli = ((dlli - gold_sadj[1]) * 19) >> 5;
312
+
dlli += 1;
313
+
if (dlli > 4)
314
+
dlli = 4;
315
+
dlli = (8 - dlli) & 0x7;
316
+
}
317
+
data |= dlli << 21;
318
+
}
319
+
}
320
+
ast_moutdwm(ast, 0x1E6E0084, data);
321
+
return status;
322
+
} /* finetuneDQI_L */
323
+
324
+
static void finetuneDQSI(struct ast_device *ast)
325
+
{
326
+
u32 dlli, dqsip, dqidly;
327
+
u32 reg_mcr18, reg_mcr0c, passcnt[2], diff;
328
+
u32 g_dqidly, g_dqsip, g_margin, g_side;
329
+
u16 pass[32][2][2];
330
+
char tag[2][76];
331
+
332
+
/* Disable DQI CBR */
333
+
reg_mcr0c = ast_mindwm(ast, 0x1E6E000C);
334
+
reg_mcr18 = ast_mindwm(ast, 0x1E6E0018);
335
+
reg_mcr18 &= 0x0000ffff;
336
+
ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
337
+
338
+
for (dlli = 0; dlli < 76; dlli++) {
339
+
tag[0][dlli] = 0x0;
340
+
tag[1][dlli] = 0x0;
341
+
}
342
+
for (dqidly = 0; dqidly < 32; dqidly++) {
343
+
pass[dqidly][0][0] = 0xff;
344
+
pass[dqidly][0][1] = 0x0;
345
+
pass[dqidly][1][0] = 0xff;
346
+
pass[dqidly][1][1] = 0x0;
347
+
}
348
+
for (dqidly = 0; dqidly < 32; dqidly++) {
349
+
passcnt[0] = 0;
350
+
passcnt[1] = 0;
351
+
for (dqsip = 0; dqsip < 2; dqsip++) {
352
+
ast_moutdwm(ast, 0x1E6E000C, 0);
353
+
ast_moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23));
354
+
ast_moutdwm(ast, 0x1E6E000C, reg_mcr0c);
355
+
for (dlli = 0; dlli < 76; dlli++) {
356
+
ast_moutdwm(ast, 0x1E6E0068,
357
+
0x00001300 | (dlli << 16) | (dlli << 24));
358
+
ast_moutdwm(ast, 0x1E6E0070, 0);
359
+
ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE0);
360
+
if (cbr_scan3(ast)) {
361
+
if (dlli == 0)
362
+
break;
363
+
passcnt[dqsip]++;
364
+
tag[dqsip][dlli] = 'P';
365
+
if (dlli < pass[dqidly][dqsip][0])
366
+
pass[dqidly][dqsip][0] = (u16)dlli;
367
+
if (dlli > pass[dqidly][dqsip][1])
368
+
pass[dqidly][dqsip][1] = (u16)dlli;
369
+
} else if (passcnt[dqsip] >= 5) {
370
+
break;
371
+
} else {
372
+
pass[dqidly][dqsip][0] = 0xff;
373
+
pass[dqidly][dqsip][1] = 0x0;
374
+
}
375
+
}
376
+
}
377
+
if (passcnt[0] == 0 && passcnt[1] == 0)
378
+
dqidly++;
379
+
}
380
+
/* Search margin */
381
+
g_dqidly = 0;
382
+
g_dqsip = 0;
383
+
g_margin = 0;
384
+
g_side = 0;
385
+
386
+
for (dqidly = 0; dqidly < 32; dqidly++) {
387
+
for (dqsip = 0; dqsip < 2; dqsip++) {
388
+
if (pass[dqidly][dqsip][0] > pass[dqidly][dqsip][1])
389
+
continue;
390
+
diff = pass[dqidly][dqsip][1] - pass[dqidly][dqsip][0];
391
+
if ((diff + 2) < g_margin)
392
+
continue;
393
+
passcnt[0] = 0;
394
+
passcnt[1] = 0;
395
+
for (dlli = pass[dqidly][dqsip][0];
396
+
dlli > 0 && tag[dqsip][dlli] != 0;
397
+
dlli--, passcnt[0]++) {
398
+
}
399
+
for (dlli = pass[dqidly][dqsip][1];
400
+
dlli < 76 && tag[dqsip][dlli] != 0;
401
+
dlli++, passcnt[1]++) {
402
+
}
403
+
if (passcnt[0] > passcnt[1])
404
+
passcnt[0] = passcnt[1];
405
+
passcnt[1] = 0;
406
+
if (passcnt[0] > g_side)
407
+
passcnt[1] = passcnt[0] - g_side;
408
+
if (diff > (g_margin + 1) && (passcnt[1] > 0 || passcnt[0] > 8)) {
409
+
g_margin = diff;
410
+
g_dqidly = dqidly;
411
+
g_dqsip = dqsip;
412
+
g_side = passcnt[0];
413
+
} else if (passcnt[1] > 1 && g_side < 8) {
414
+
if (diff > g_margin)
415
+
g_margin = diff;
416
+
g_dqidly = dqidly;
417
+
g_dqsip = dqsip;
418
+
g_side = passcnt[0];
419
+
}
420
+
}
421
+
}
422
+
reg_mcr18 = reg_mcr18 | (g_dqidly << 16) | (g_dqsip << 23);
423
+
ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
424
+
}
425
+
426
+
static bool cbr_dll2(struct ast_device *ast, struct ast2300_dram_param *param)
427
+
{
428
+
u32 dllmin[2], dllmax[2], dlli, data, passcnt, retry = 0;
429
+
bool status = false;
430
+
431
+
finetuneDQSI(ast);
432
+
if (finetuneDQI_L(ast, param) == false)
433
+
return status;
434
+
435
+
CBR_START2:
436
+
dllmin[0] = 0xff;
437
+
dllmin[1] = 0xff;
438
+
dllmax[0] = 0x0;
439
+
dllmax[1] = 0x0;
440
+
passcnt = 0;
441
+
for (dlli = 0; dlli < 76; dlli++) {
442
+
ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
443
+
ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
444
+
data = cbr_scan(ast);
445
+
if (data != 0) {
446
+
if (data & 0x1) {
447
+
if (dllmin[0] > dlli)
448
+
dllmin[0] = dlli;
449
+
if (dllmax[0] < dlli)
450
+
dllmax[0] = dlli;
451
+
}
452
+
if (data & 0x2) {
453
+
if (dllmin[1] > dlli)
454
+
dllmin[1] = dlli;
455
+
if (dllmax[1] < dlli)
456
+
dllmax[1] = dlli;
457
+
}
458
+
passcnt++;
459
+
} else if (passcnt >= CBR_THRESHOLD) {
460
+
break;
461
+
}
462
+
}
463
+
if (retry++ > 10)
464
+
goto CBR_DONE2;
465
+
if (dllmax[0] == 0 || (dllmax[0] - dllmin[0]) < CBR_THRESHOLD)
466
+
goto CBR_START2;
467
+
if (dllmax[1] == 0 || (dllmax[1] - dllmin[1]) < CBR_THRESHOLD)
468
+
goto CBR_START2;
469
+
status = true;
470
+
CBR_DONE2:
471
+
dlli = (dllmin[1] + dllmax[1]) >> 1;
472
+
dlli <<= 8;
473
+
dlli += (dllmin[0] + dllmax[0]) >> 1;
474
+
ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16));
475
+
return status;
476
+
} /* CBRDLL2 */
477
+
478
+
static void get_ddr3_info(struct ast_device *ast, struct ast2300_dram_param *param)
479
+
{
480
+
u32 trap, trap_AC2, trap_MRS;
481
+
482
+
ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
483
+
484
+
/* Ger trap info */
485
+
trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
486
+
trap_AC2 = 0x00020000 + (trap << 16);
487
+
trap_AC2 |= 0x00300000 + ((trap & 0x2) << 19);
488
+
trap_MRS = 0x00000010 + (trap << 4);
489
+
trap_MRS |= ((trap & 0x2) << 18);
490
+
491
+
param->reg_MADJ = 0x00034C4C;
492
+
param->reg_SADJ = 0x00001800;
493
+
param->reg_DRV = 0x000000F0;
494
+
param->reg_PERIOD = param->dram_freq;
495
+
param->rodt = 0;
496
+
497
+
switch (param->dram_freq) {
498
+
case 336:
499
+
ast_moutdwm(ast, 0x1E6E2020, 0x0190);
500
+
param->wodt = 0;
501
+
param->reg_AC1 = 0x22202725;
502
+
param->reg_AC2 = 0xAA007613 | trap_AC2;
503
+
param->reg_DQSIC = 0x000000BA;
504
+
param->reg_MRS = 0x04001400 | trap_MRS;
505
+
param->reg_EMRS = 0x00000000;
506
+
param->reg_IOZ = 0x00000023;
507
+
param->reg_DQIDLY = 0x00000074;
508
+
param->reg_FREQ = 0x00004DC0;
509
+
param->madj_max = 96;
510
+
param->dll2_finetune_step = 3;
511
+
switch (param->dram_chipid) {
512
+
default:
513
+
case AST_DRAM_512Mx16:
514
+
case AST_DRAM_1Gx16:
515
+
param->reg_AC2 = 0xAA007613 | trap_AC2;
516
+
break;
517
+
case AST_DRAM_2Gx16:
518
+
param->reg_AC2 = 0xAA00761C | trap_AC2;
519
+
break;
520
+
case AST_DRAM_4Gx16:
521
+
param->reg_AC2 = 0xAA007636 | trap_AC2;
522
+
break;
523
+
}
524
+
break;
525
+
default:
526
+
case 396:
527
+
ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
528
+
param->wodt = 1;
529
+
param->reg_AC1 = 0x33302825;
530
+
param->reg_AC2 = 0xCC009617 | trap_AC2;
531
+
param->reg_DQSIC = 0x000000E2;
532
+
param->reg_MRS = 0x04001600 | trap_MRS;
533
+
param->reg_EMRS = 0x00000000;
534
+
param->reg_IOZ = 0x00000034;
535
+
param->reg_DRV = 0x000000FA;
536
+
param->reg_DQIDLY = 0x00000089;
537
+
param->reg_FREQ = 0x00005040;
538
+
param->madj_max = 96;
539
+
param->dll2_finetune_step = 4;
540
+
541
+
switch (param->dram_chipid) {
542
+
default:
543
+
case AST_DRAM_512Mx16:
544
+
case AST_DRAM_1Gx16:
545
+
param->reg_AC2 = 0xCC009617 | trap_AC2;
546
+
break;
547
+
case AST_DRAM_2Gx16:
548
+
param->reg_AC2 = 0xCC009622 | trap_AC2;
549
+
break;
550
+
case AST_DRAM_4Gx16:
551
+
param->reg_AC2 = 0xCC00963F | trap_AC2;
552
+
break;
553
+
}
554
+
break;
555
+
556
+
case 408:
557
+
ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
558
+
param->wodt = 1;
559
+
param->reg_AC1 = 0x33302825;
560
+
param->reg_AC2 = 0xCC009617 | trap_AC2;
561
+
param->reg_DQSIC = 0x000000E2;
562
+
param->reg_MRS = 0x04001600 | trap_MRS;
563
+
param->reg_EMRS = 0x00000000;
564
+
param->reg_IOZ = 0x00000023;
565
+
param->reg_DRV = 0x000000FA;
566
+
param->reg_DQIDLY = 0x00000089;
567
+
param->reg_FREQ = 0x000050C0;
568
+
param->madj_max = 96;
569
+
param->dll2_finetune_step = 4;
570
+
571
+
switch (param->dram_chipid) {
572
+
default:
573
+
case AST_DRAM_512Mx16:
574
+
case AST_DRAM_1Gx16:
575
+
param->reg_AC2 = 0xCC009617 | trap_AC2;
576
+
break;
577
+
case AST_DRAM_2Gx16:
578
+
param->reg_AC2 = 0xCC009622 | trap_AC2;
579
+
break;
580
+
case AST_DRAM_4Gx16:
581
+
param->reg_AC2 = 0xCC00963F | trap_AC2;
582
+
break;
583
+
}
584
+
585
+
break;
586
+
case 456:
587
+
ast_moutdwm(ast, 0x1E6E2020, 0x0230);
588
+
param->wodt = 0;
589
+
param->reg_AC1 = 0x33302926;
590
+
param->reg_AC2 = 0xCD44961A;
591
+
param->reg_DQSIC = 0x000000FC;
592
+
param->reg_MRS = 0x00081830;
593
+
param->reg_EMRS = 0x00000000;
594
+
param->reg_IOZ = 0x00000045;
595
+
param->reg_DQIDLY = 0x00000097;
596
+
param->reg_FREQ = 0x000052C0;
597
+
param->madj_max = 88;
598
+
param->dll2_finetune_step = 4;
599
+
break;
600
+
case 504:
601
+
ast_moutdwm(ast, 0x1E6E2020, 0x0270);
602
+
param->wodt = 1;
603
+
param->reg_AC1 = 0x33302926;
604
+
param->reg_AC2 = 0xDE44A61D;
605
+
param->reg_DQSIC = 0x00000117;
606
+
param->reg_MRS = 0x00081A30;
607
+
param->reg_EMRS = 0x00000000;
608
+
param->reg_IOZ = 0x070000BB;
609
+
param->reg_DQIDLY = 0x000000A0;
610
+
param->reg_FREQ = 0x000054C0;
611
+
param->madj_max = 79;
612
+
param->dll2_finetune_step = 4;
613
+
break;
614
+
case 528:
615
+
ast_moutdwm(ast, 0x1E6E2020, 0x0290);
616
+
param->wodt = 1;
617
+
param->rodt = 1;
618
+
param->reg_AC1 = 0x33302926;
619
+
param->reg_AC2 = 0xEF44B61E;
620
+
param->reg_DQSIC = 0x00000125;
621
+
param->reg_MRS = 0x00081A30;
622
+
param->reg_EMRS = 0x00000040;
623
+
param->reg_DRV = 0x000000F5;
624
+
param->reg_IOZ = 0x00000023;
625
+
param->reg_DQIDLY = 0x00000088;
626
+
param->reg_FREQ = 0x000055C0;
627
+
param->madj_max = 76;
628
+
param->dll2_finetune_step = 3;
629
+
break;
630
+
case 576:
631
+
ast_moutdwm(ast, 0x1E6E2020, 0x0140);
632
+
param->reg_MADJ = 0x00136868;
633
+
param->reg_SADJ = 0x00004534;
634
+
param->wodt = 1;
635
+
param->rodt = 1;
636
+
param->reg_AC1 = 0x33302A37;
637
+
param->reg_AC2 = 0xEF56B61E;
638
+
param->reg_DQSIC = 0x0000013F;
639
+
param->reg_MRS = 0x00101A50;
640
+
param->reg_EMRS = 0x00000040;
641
+
param->reg_DRV = 0x000000FA;
642
+
param->reg_IOZ = 0x00000023;
643
+
param->reg_DQIDLY = 0x00000078;
644
+
param->reg_FREQ = 0x000057C0;
645
+
param->madj_max = 136;
646
+
param->dll2_finetune_step = 3;
647
+
break;
648
+
case 600:
649
+
ast_moutdwm(ast, 0x1E6E2020, 0x02E1);
650
+
param->reg_MADJ = 0x00136868;
651
+
param->reg_SADJ = 0x00004534;
652
+
param->wodt = 1;
653
+
param->rodt = 1;
654
+
param->reg_AC1 = 0x32302A37;
655
+
param->reg_AC2 = 0xDF56B61F;
656
+
param->reg_DQSIC = 0x0000014D;
657
+
param->reg_MRS = 0x00101A50;
658
+
param->reg_EMRS = 0x00000004;
659
+
param->reg_DRV = 0x000000F5;
660
+
param->reg_IOZ = 0x00000023;
661
+
param->reg_DQIDLY = 0x00000078;
662
+
param->reg_FREQ = 0x000058C0;
663
+
param->madj_max = 132;
664
+
param->dll2_finetune_step = 3;
665
+
break;
666
+
case 624:
667
+
ast_moutdwm(ast, 0x1E6E2020, 0x0160);
668
+
param->reg_MADJ = 0x00136868;
669
+
param->reg_SADJ = 0x00004534;
670
+
param->wodt = 1;
671
+
param->rodt = 1;
672
+
param->reg_AC1 = 0x32302A37;
673
+
param->reg_AC2 = 0xEF56B621;
674
+
param->reg_DQSIC = 0x0000015A;
675
+
param->reg_MRS = 0x02101A50;
676
+
param->reg_EMRS = 0x00000004;
677
+
param->reg_DRV = 0x000000F5;
678
+
param->reg_IOZ = 0x00000034;
679
+
param->reg_DQIDLY = 0x00000078;
680
+
param->reg_FREQ = 0x000059C0;
681
+
param->madj_max = 128;
682
+
param->dll2_finetune_step = 3;
683
+
break;
684
+
} /* switch freq */
685
+
686
+
switch (param->dram_chipid) {
687
+
case AST_DRAM_512Mx16:
688
+
param->dram_config = 0x130;
689
+
break;
690
+
default:
691
+
case AST_DRAM_1Gx16:
692
+
param->dram_config = 0x131;
693
+
break;
694
+
case AST_DRAM_2Gx16:
695
+
param->dram_config = 0x132;
696
+
break;
697
+
case AST_DRAM_4Gx16:
698
+
param->dram_config = 0x133;
699
+
break;
700
+
} /* switch size */
701
+
702
+
switch (param->vram_size) {
703
+
default:
704
+
case SZ_8M:
705
+
param->dram_config |= 0x00;
706
+
break;
707
+
case SZ_16M:
708
+
param->dram_config |= 0x04;
709
+
break;
710
+
case SZ_32M:
711
+
param->dram_config |= 0x08;
712
+
break;
713
+
case SZ_64M:
714
+
param->dram_config |= 0x0c;
715
+
break;
716
+
}
717
+
}
718
+
719
+
static void ddr3_init(struct ast_device *ast, struct ast2300_dram_param *param)
720
+
{
721
+
u32 data, data2, retry = 0;
722
+
723
+
ddr3_init_start:
724
+
ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
725
+
ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
726
+
ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
727
+
ast_moutdwm(ast, 0x1E6E0034, 0x00000000);
728
+
udelay(10);
729
+
ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
730
+
ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
731
+
udelay(10);
732
+
ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
733
+
udelay(10);
734
+
735
+
ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
736
+
ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
737
+
ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
738
+
ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
739
+
ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
740
+
ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
741
+
ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
742
+
ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
743
+
ast_moutdwm(ast, 0x1E6E0018, 0x4000A170);
744
+
ast_moutdwm(ast, 0x1E6E0018, 0x00002370);
745
+
ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
746
+
ast_moutdwm(ast, 0x1E6E0040, 0xFF444444);
747
+
ast_moutdwm(ast, 0x1E6E0044, 0x22222222);
748
+
ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
749
+
ast_moutdwm(ast, 0x1E6E004C, 0x00000002);
750
+
ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
751
+
ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
752
+
ast_moutdwm(ast, 0x1E6E0054, 0);
753
+
ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
754
+
ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
755
+
ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
756
+
ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
757
+
ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
758
+
ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
759
+
/* Wait MCLK2X lock to MCLK */
760
+
do {
761
+
data = ast_mindwm(ast, 0x1E6E001C);
762
+
} while (!(data & 0x08000000));
763
+
data = ast_mindwm(ast, 0x1E6E001C);
764
+
data = (data >> 8) & 0xff;
765
+
while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
766
+
data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
767
+
if ((data2 & 0xff) > param->madj_max)
768
+
break;
769
+
ast_moutdwm(ast, 0x1E6E0064, data2);
770
+
if (data2 & 0x00100000)
771
+
data2 = ((data2 & 0xff) >> 3) + 3;
772
+
else
773
+
data2 = ((data2 & 0xff) >> 2) + 5;
774
+
data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
775
+
data2 += data & 0xff;
776
+
data = data | (data2 << 8);
777
+
ast_moutdwm(ast, 0x1E6E0068, data);
778
+
udelay(10);
779
+
ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
780
+
udelay(10);
781
+
data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
782
+
ast_moutdwm(ast, 0x1E6E0018, data);
783
+
data = data | 0x200;
784
+
ast_moutdwm(ast, 0x1E6E0018, data);
785
+
do {
786
+
data = ast_mindwm(ast, 0x1E6E001C);
787
+
} while (!(data & 0x08000000));
788
+
789
+
data = ast_mindwm(ast, 0x1E6E001C);
790
+
data = (data >> 8) & 0xff;
791
+
}
792
+
ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff);
793
+
data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
794
+
ast_moutdwm(ast, 0x1E6E0018, data);
795
+
796
+
ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
797
+
ast_moutdwm(ast, 0x1E6E000C, 0x00000040);
798
+
udelay(50);
799
+
/* Mode Register Setting */
800
+
ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
801
+
ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
802
+
ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
803
+
ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
804
+
ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
805
+
ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
806
+
ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
807
+
ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
808
+
ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
809
+
810
+
ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
811
+
data = 0;
812
+
if (param->wodt)
813
+
data = 0x300;
814
+
if (param->rodt)
815
+
data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
816
+
ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
817
+
818
+
/* Calibrate the DQSI delay */
819
+
if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
820
+
goto ddr3_init_start;
821
+
822
+
ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
823
+
/* ECC Memory Initialization */
824
+
#ifdef ECC
825
+
ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
826
+
ast_moutdwm(ast, 0x1E6E0070, 0x221);
827
+
do {
828
+
data = ast_mindwm(ast, 0x1E6E0070);
829
+
} while (!(data & 0x00001000));
830
+
ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
831
+
ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
832
+
ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
833
+
#endif
834
+
}
835
+
836
+
static void get_ddr2_info(struct ast_device *ast, struct ast2300_dram_param *param)
837
+
{
838
+
u32 trap, trap_AC2, trap_MRS;
839
+
840
+
ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
841
+
842
+
/* Ger trap info */
843
+
trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
844
+
trap_AC2 = (trap << 20) | (trap << 16);
845
+
trap_AC2 += 0x00110000;
846
+
trap_MRS = 0x00000040 | (trap << 4);
847
+
848
+
param->reg_MADJ = 0x00034C4C;
849
+
param->reg_SADJ = 0x00001800;
850
+
param->reg_DRV = 0x000000F0;
851
+
param->reg_PERIOD = param->dram_freq;
852
+
param->rodt = 0;
853
+
854
+
switch (param->dram_freq) {
855
+
case 264:
856
+
ast_moutdwm(ast, 0x1E6E2020, 0x0130);
857
+
param->wodt = 0;
858
+
param->reg_AC1 = 0x11101513;
859
+
param->reg_AC2 = 0x78117011;
860
+
param->reg_DQSIC = 0x00000092;
861
+
param->reg_MRS = 0x00000842;
862
+
param->reg_EMRS = 0x00000000;
863
+
param->reg_DRV = 0x000000F0;
864
+
param->reg_IOZ = 0x00000034;
865
+
param->reg_DQIDLY = 0x0000005A;
866
+
param->reg_FREQ = 0x00004AC0;
867
+
param->madj_max = 138;
868
+
param->dll2_finetune_step = 3;
869
+
break;
870
+
case 336:
871
+
ast_moutdwm(ast, 0x1E6E2020, 0x0190);
872
+
param->wodt = 1;
873
+
param->reg_AC1 = 0x22202613;
874
+
param->reg_AC2 = 0xAA009016 | trap_AC2;
875
+
param->reg_DQSIC = 0x000000BA;
876
+
param->reg_MRS = 0x00000A02 | trap_MRS;
877
+
param->reg_EMRS = 0x00000040;
878
+
param->reg_DRV = 0x000000FA;
879
+
param->reg_IOZ = 0x00000034;
880
+
param->reg_DQIDLY = 0x00000074;
881
+
param->reg_FREQ = 0x00004DC0;
882
+
param->madj_max = 96;
883
+
param->dll2_finetune_step = 3;
884
+
switch (param->dram_chipid) {
885
+
default:
886
+
case AST_DRAM_512Mx16:
887
+
param->reg_AC2 = 0xAA009012 | trap_AC2;
888
+
break;
889
+
case AST_DRAM_1Gx16:
890
+
param->reg_AC2 = 0xAA009016 | trap_AC2;
891
+
break;
892
+
case AST_DRAM_2Gx16:
893
+
param->reg_AC2 = 0xAA009023 | trap_AC2;
894
+
break;
895
+
case AST_DRAM_4Gx16:
896
+
param->reg_AC2 = 0xAA00903B | trap_AC2;
897
+
break;
898
+
}
899
+
break;
900
+
default:
901
+
case 396:
902
+
ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
903
+
param->wodt = 1;
904
+
param->rodt = 0;
905
+
param->reg_AC1 = 0x33302714;
906
+
param->reg_AC2 = 0xCC00B01B | trap_AC2;
907
+
param->reg_DQSIC = 0x000000E2;
908
+
param->reg_MRS = 0x00000C02 | trap_MRS;
909
+
param->reg_EMRS = 0x00000040;
910
+
param->reg_DRV = 0x000000FA;
911
+
param->reg_IOZ = 0x00000034;
912
+
param->reg_DQIDLY = 0x00000089;
913
+
param->reg_FREQ = 0x00005040;
914
+
param->madj_max = 96;
915
+
param->dll2_finetune_step = 4;
916
+
917
+
switch (param->dram_chipid) {
918
+
case AST_DRAM_512Mx16:
919
+
param->reg_AC2 = 0xCC00B016 | trap_AC2;
920
+
break;
921
+
default:
922
+
case AST_DRAM_1Gx16:
923
+
param->reg_AC2 = 0xCC00B01B | trap_AC2;
924
+
break;
925
+
case AST_DRAM_2Gx16:
926
+
param->reg_AC2 = 0xCC00B02B | trap_AC2;
927
+
break;
928
+
case AST_DRAM_4Gx16:
929
+
param->reg_AC2 = 0xCC00B03F | trap_AC2;
930
+
break;
931
+
}
932
+
933
+
break;
934
+
935
+
case 408:
936
+
ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
937
+
param->wodt = 1;
938
+
param->rodt = 0;
939
+
param->reg_AC1 = 0x33302714;
940
+
param->reg_AC2 = 0xCC00B01B | trap_AC2;
941
+
param->reg_DQSIC = 0x000000E2;
942
+
param->reg_MRS = 0x00000C02 | trap_MRS;
943
+
param->reg_EMRS = 0x00000040;
944
+
param->reg_DRV = 0x000000FA;
945
+
param->reg_IOZ = 0x00000034;
946
+
param->reg_DQIDLY = 0x00000089;
947
+
param->reg_FREQ = 0x000050C0;
948
+
param->madj_max = 96;
949
+
param->dll2_finetune_step = 4;
950
+
951
+
switch (param->dram_chipid) {
952
+
case AST_DRAM_512Mx16:
953
+
param->reg_AC2 = 0xCC00B016 | trap_AC2;
954
+
break;
955
+
default:
956
+
case AST_DRAM_1Gx16:
957
+
param->reg_AC2 = 0xCC00B01B | trap_AC2;
958
+
break;
959
+
case AST_DRAM_2Gx16:
960
+
param->reg_AC2 = 0xCC00B02B | trap_AC2;
961
+
break;
962
+
case AST_DRAM_4Gx16:
963
+
param->reg_AC2 = 0xCC00B03F | trap_AC2;
964
+
break;
965
+
}
966
+
967
+
break;
968
+
case 456:
969
+
ast_moutdwm(ast, 0x1E6E2020, 0x0230);
970
+
param->wodt = 0;
971
+
param->reg_AC1 = 0x33302815;
972
+
param->reg_AC2 = 0xCD44B01E;
973
+
param->reg_DQSIC = 0x000000FC;
974
+
param->reg_MRS = 0x00000E72;
975
+
param->reg_EMRS = 0x00000000;
976
+
param->reg_DRV = 0x00000000;
977
+
param->reg_IOZ = 0x00000034;
978
+
param->reg_DQIDLY = 0x00000097;
979
+
param->reg_FREQ = 0x000052C0;
980
+
param->madj_max = 88;
981
+
param->dll2_finetune_step = 3;
982
+
break;
983
+
case 504:
984
+
ast_moutdwm(ast, 0x1E6E2020, 0x0261);
985
+
param->wodt = 1;
986
+
param->rodt = 1;
987
+
param->reg_AC1 = 0x33302815;
988
+
param->reg_AC2 = 0xDE44C022;
989
+
param->reg_DQSIC = 0x00000117;
990
+
param->reg_MRS = 0x00000E72;
991
+
param->reg_EMRS = 0x00000040;
992
+
param->reg_DRV = 0x0000000A;
993
+
param->reg_IOZ = 0x00000045;
994
+
param->reg_DQIDLY = 0x000000A0;
995
+
param->reg_FREQ = 0x000054C0;
996
+
param->madj_max = 79;
997
+
param->dll2_finetune_step = 3;
998
+
break;
999
+
case 528:
1000
+
ast_moutdwm(ast, 0x1E6E2020, 0x0120);
1001
+
param->wodt = 1;
1002
+
param->rodt = 1;
1003
+
param->reg_AC1 = 0x33302815;
1004
+
param->reg_AC2 = 0xEF44D024;
1005
+
param->reg_DQSIC = 0x00000125;
1006
+
param->reg_MRS = 0x00000E72;
1007
+
param->reg_EMRS = 0x00000004;
1008
+
param->reg_DRV = 0x000000F9;
1009
+
param->reg_IOZ = 0x00000045;
1010
+
param->reg_DQIDLY = 0x000000A7;
1011
+
param->reg_FREQ = 0x000055C0;
1012
+
param->madj_max = 76;
1013
+
param->dll2_finetune_step = 3;
1014
+
break;
1015
+
case 552:
1016
+
ast_moutdwm(ast, 0x1E6E2020, 0x02A1);
1017
+
param->wodt = 1;
1018
+
param->rodt = 1;
1019
+
param->reg_AC1 = 0x43402915;
1020
+
param->reg_AC2 = 0xFF44E025;
1021
+
param->reg_DQSIC = 0x00000132;
1022
+
param->reg_MRS = 0x00000E72;
1023
+
param->reg_EMRS = 0x00000040;
1024
+
param->reg_DRV = 0x0000000A;
1025
+
param->reg_IOZ = 0x00000045;
1026
+
param->reg_DQIDLY = 0x000000AD;
1027
+
param->reg_FREQ = 0x000056C0;
1028
+
param->madj_max = 76;
1029
+
param->dll2_finetune_step = 3;
1030
+
break;
1031
+
case 576:
1032
+
ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1033
+
param->wodt = 1;
1034
+
param->rodt = 1;
1035
+
param->reg_AC1 = 0x43402915;
1036
+
param->reg_AC2 = 0xFF44E027;
1037
+
param->reg_DQSIC = 0x0000013F;
1038
+
param->reg_MRS = 0x00000E72;
1039
+
param->reg_EMRS = 0x00000004;
1040
+
param->reg_DRV = 0x000000F5;
1041
+
param->reg_IOZ = 0x00000045;
1042
+
param->reg_DQIDLY = 0x000000B3;
1043
+
param->reg_FREQ = 0x000057C0;
1044
+
param->madj_max = 76;
1045
+
param->dll2_finetune_step = 3;
1046
+
break;
1047
+
}
1048
+
1049
+
switch (param->dram_chipid) {
1050
+
case AST_DRAM_512Mx16:
1051
+
param->dram_config = 0x100;
1052
+
break;
1053
+
default:
1054
+
case AST_DRAM_1Gx16:
1055
+
param->dram_config = 0x121;
1056
+
break;
1057
+
case AST_DRAM_2Gx16:
1058
+
param->dram_config = 0x122;
1059
+
break;
1060
+
case AST_DRAM_4Gx16:
1061
+
param->dram_config = 0x123;
1062
+
break;
1063
+
} /* switch size */
1064
+
1065
+
switch (param->vram_size) {
1066
+
default:
1067
+
case SZ_8M:
1068
+
param->dram_config |= 0x00;
1069
+
break;
1070
+
case SZ_16M:
1071
+
param->dram_config |= 0x04;
1072
+
break;
1073
+
case SZ_32M:
1074
+
param->dram_config |= 0x08;
1075
+
break;
1076
+
case SZ_64M:
1077
+
param->dram_config |= 0x0c;
1078
+
break;
1079
+
}
1080
+
}
1081
+
1082
+
static void ddr2_init(struct ast_device *ast, struct ast2300_dram_param *param)
1083
+
{
1084
+
u32 data, data2, retry = 0;
1085
+
1086
+
ddr2_init_start:
1087
+
ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1088
+
ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1089
+
ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1090
+
ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1091
+
ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1092
+
udelay(10);
1093
+
ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1094
+
udelay(10);
1095
+
1096
+
ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1097
+
ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1098
+
ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1099
+
ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1100
+
ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1101
+
ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1102
+
ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1103
+
ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1104
+
ast_moutdwm(ast, 0x1E6E0018, 0x4000A130);
1105
+
ast_moutdwm(ast, 0x1E6E0018, 0x00002330);
1106
+
ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1107
+
ast_moutdwm(ast, 0x1E6E0040, 0xFF808000);
1108
+
ast_moutdwm(ast, 0x1E6E0044, 0x88848466);
1109
+
ast_moutdwm(ast, 0x1E6E0048, 0x44440008);
1110
+
ast_moutdwm(ast, 0x1E6E004C, 0x00000000);
1111
+
ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1112
+
ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1113
+
ast_moutdwm(ast, 0x1E6E0054, 0);
1114
+
ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1115
+
ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1116
+
ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1117
+
ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1118
+
ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1119
+
ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1120
+
1121
+
/* Wait MCLK2X lock to MCLK */
1122
+
do {
1123
+
data = ast_mindwm(ast, 0x1E6E001C);
1124
+
} while (!(data & 0x08000000));
1125
+
data = ast_mindwm(ast, 0x1E6E001C);
1126
+
data = (data >> 8) & 0xff;
1127
+
while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1128
+
data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1129
+
if ((data2 & 0xff) > param->madj_max)
1130
+
break;
1131
+
ast_moutdwm(ast, 0x1E6E0064, data2);
1132
+
if (data2 & 0x00100000)
1133
+
data2 = ((data2 & 0xff) >> 3) + 3;
1134
+
else
1135
+
data2 = ((data2 & 0xff) >> 2) + 5;
1136
+
data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1137
+
data2 += data & 0xff;
1138
+
data = data | (data2 << 8);
1139
+
ast_moutdwm(ast, 0x1E6E0068, data);
1140
+
udelay(10);
1141
+
ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1142
+
udelay(10);
1143
+
data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1144
+
ast_moutdwm(ast, 0x1E6E0018, data);
1145
+
data = data | 0x200;
1146
+
ast_moutdwm(ast, 0x1E6E0018, data);
1147
+
do {
1148
+
data = ast_mindwm(ast, 0x1E6E001C);
1149
+
} while (!(data & 0x08000000));
1150
+
1151
+
data = ast_mindwm(ast, 0x1E6E001C);
1152
+
data = (data >> 8) & 0xff;
1153
+
}
1154
+
ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff);
1155
+
data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1156
+
ast_moutdwm(ast, 0x1E6E0018, data);
1157
+
1158
+
ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1159
+
ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1160
+
udelay(50);
1161
+
/* Mode Register Setting */
1162
+
ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1163
+
ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1164
+
ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1165
+
ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1166
+
ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1167
+
ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1168
+
1169
+
ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1170
+
ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1171
+
ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1172
+
ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380);
1173
+
ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1174
+
ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1175
+
ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1176
+
1177
+
ast_moutdwm(ast, 0x1E6E000C, 0x7FFF5C01);
1178
+
data = 0;
1179
+
if (param->wodt)
1180
+
data = 0x500;
1181
+
if (param->rodt)
1182
+
data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1183
+
ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1184
+
ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1185
+
1186
+
/* Calibrate the DQSI delay */
1187
+
if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1188
+
goto ddr2_init_start;
1189
+
1190
+
/* ECC Memory Initialization */
1191
+
#ifdef ECC
1192
+
ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1193
+
ast_moutdwm(ast, 0x1E6E0070, 0x221);
1194
+
do {
1195
+
data = ast_mindwm(ast, 0x1E6E0070);
1196
+
} while (!(data & 0x00001000));
1197
+
ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1198
+
ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1199
+
ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1200
+
#endif
1201
+
}
1202
+
1203
+
static void ast_post_chip_2300(struct ast_device *ast)
1204
+
{
1205
+
struct ast2300_dram_param param;
1206
+
u32 temp;
1207
+
u8 reg;
1208
+
1209
+
reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
1210
+
if ((reg & 0x80) == 0) {/* vga only */
1211
+
ast_write32(ast, 0xf004, 0x1e6e0000);
1212
+
ast_write32(ast, 0xf000, 0x1);
1213
+
ast_write32(ast, 0x12000, 0x1688a8a8);
1214
+
do {
1215
+
;
1216
+
} while (ast_read32(ast, 0x12000) != 0x1);
1217
+
1218
+
ast_write32(ast, 0x10000, 0xfc600309);
1219
+
do {
1220
+
;
1221
+
} while (ast_read32(ast, 0x10000) != 0x1);
1222
+
1223
+
/* Slow down CPU/AHB CLK in VGA only mode */
1224
+
temp = ast_read32(ast, 0x12008);
1225
+
temp |= 0x73;
1226
+
ast_write32(ast, 0x12008, temp);
1227
+
1228
+
param.dram_freq = 396;
1229
+
param.dram_type = AST_DDR3;
1230
+
temp = ast_mindwm(ast, 0x1e6e2070);
1231
+
if (temp & 0x01000000)
1232
+
param.dram_type = AST_DDR2;
1233
+
switch (temp & 0x18000000) {
1234
+
case 0:
1235
+
param.dram_chipid = AST_DRAM_512Mx16;
1236
+
break;
1237
+
default:
1238
+
case 0x08000000:
1239
+
param.dram_chipid = AST_DRAM_1Gx16;
1240
+
break;
1241
+
case 0x10000000:
1242
+
param.dram_chipid = AST_DRAM_2Gx16;
1243
+
break;
1244
+
case 0x18000000:
1245
+
param.dram_chipid = AST_DRAM_4Gx16;
1246
+
break;
1247
+
}
1248
+
switch (temp & 0x0c) {
1249
+
default:
1250
+
case 0x00:
1251
+
param.vram_size = SZ_8M;
1252
+
break;
1253
+
case 0x04:
1254
+
param.vram_size = SZ_16M;
1255
+
break;
1256
+
case 0x08:
1257
+
param.vram_size = SZ_32M;
1258
+
break;
1259
+
case 0x0c:
1260
+
param.vram_size = SZ_64M;
1261
+
break;
1262
+
}
1263
+
1264
+
if (param.dram_type == AST_DDR3) {
1265
+
get_ddr3_info(ast, ¶m);
1266
+
ddr3_init(ast, ¶m);
1267
+
} else {
1268
+
get_ddr2_info(ast, ¶m);
1269
+
ddr2_init(ast, ¶m);
1270
+
}
1271
+
1272
+
temp = ast_mindwm(ast, 0x1e6e2040);
1273
+
ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
1274
+
}
1275
+
1276
+
/* wait ready */
1277
+
do {
1278
+
reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
1279
+
} while ((reg & 0x40) == 0);
1280
+
}
1281
+
1282
+
int ast_2300_post(struct ast_device *ast)
1283
+
{
1284
+
if (ast->config_mode == ast_use_p2a) {
1285
+
ast_post_chip_2300(ast);
1286
+
ast_init_3rdtx(ast);
1287
+
} else {
1288
+
if (ast->tx_chip == AST_TX_SIL164) {
1289
+
/* Enable DVO */
1290
+
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80);
1291
+
}
1292
+
}
1293
+
1294
+
return 0;
1295
+
}
+3
drivers/gpu/drm/ast/ast_drv.h
+3
drivers/gpu/drm/ast/ast_drv.h
+3
-1262
drivers/gpu/drm/ast/ast_post.c
+3
-1262
drivers/gpu/drm/ast/ast_post.c
···
35
35
#include "ast_drv.h"
36
36
#include "ast_post.h"
37
37
38
-
static void ast_post_chip_2300(struct ast_device *ast);
39
-
40
38
static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
41
39
static const u8 extreginfo_ast2300[] = { 0x0f, 0x04, 0x1f, 0xff };
42
40
···
353
355
if (ret)
354
356
return ret;
355
357
} else if (AST_GEN(ast) >= 4) {
356
-
if (ast->config_mode == ast_use_p2a) {
357
-
ast_post_chip_2300(ast);
358
-
ast_init_3rdtx(ast);
359
-
} else {
360
-
if (ast->tx_chip == AST_TX_SIL164) {
361
-
/* Enable DVO */
362
-
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80);
363
-
}
364
-
}
358
+
ret = ast_2300_post(ast);
359
+
if (ret)
360
+
return ret;
365
361
} else {
366
362
if (ast->config_mode == ast_use_p2a) {
367
363
ast_init_dram_reg(ast);
···
370
378
return 0;
371
379
}
372
380
373
-
/* AST 2300 DRAM settings */
374
-
#define AST_DDR3 0
375
-
#define AST_DDR2 1
376
-
377
-
struct ast2300_dram_param {
378
-
u32 dram_type;
379
-
u32 dram_chipid;
380
-
u32 dram_freq;
381
-
u32 vram_size;
382
-
u32 odt;
383
-
u32 wodt;
384
-
u32 rodt;
385
-
u32 dram_config;
386
-
u32 reg_PERIOD;
387
-
u32 reg_MADJ;
388
-
u32 reg_SADJ;
389
-
u32 reg_MRS;
390
-
u32 reg_EMRS;
391
-
u32 reg_AC1;
392
-
u32 reg_AC2;
393
-
u32 reg_DQSIC;
394
-
u32 reg_DRV;
395
-
u32 reg_IOZ;
396
-
u32 reg_DQIDLY;
397
-
u32 reg_FREQ;
398
-
u32 madj_max;
399
-
u32 dll2_finetune_step;
400
-
};
401
-
402
-
/*
403
-
* DQSI DLL CBR Setting
404
-
*/
405
-
#define CBR_SIZE0 ((1 << 10) - 1)
406
-
#define CBR_SIZE1 ((4 << 10) - 1)
407
-
#define CBR_SIZE2 ((64 << 10) - 1)
408
-
#define CBR_PASSNUM 5
409
-
#define CBR_PASSNUM2 5
410
-
#define CBR_THRESHOLD 10
411
-
#define CBR_THRESHOLD2 10
412
381
#define TIMEOUT 5000000
413
-
#define CBR_PATNUM 8
414
-
415
-
static const u32 pattern[8] = {
416
-
0xFF00FF00,
417
-
0xCC33CC33,
418
-
0xAA55AA55,
419
-
0x88778877,
420
-
0x92CC4D6E,
421
-
0x543D3CDE,
422
-
0xF1E843C7,
423
-
0x7C61D253
424
-
};
425
382
426
383
bool mmc_test(struct ast_device *ast, u32 datagen, u8 test_ctl)
427
384
{
···
392
451
return true;
393
452
}
394
453
395
-
static u32 mmc_test2(struct ast_device *ast, u32 datagen, u8 test_ctl)
396
-
{
397
-
u32 data, timeout;
398
-
399
-
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
400
-
ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
401
-
timeout = 0;
402
-
do {
403
-
data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
404
-
if (++timeout > TIMEOUT) {
405
-
ast_moutdwm(ast, 0x1e6e0070, 0x0);
406
-
return 0xffffffff;
407
-
}
408
-
} while (!data);
409
-
data = ast_mindwm(ast, 0x1e6e0078);
410
-
data = (data | (data >> 16)) & 0xffff;
411
-
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
412
-
return data;
413
-
}
414
-
415
454
bool mmc_test_burst(struct ast_device *ast, u32 datagen)
416
455
{
417
456
return mmc_test(ast, datagen, 0xc1);
418
-
}
419
-
420
-
static u32 mmc_test_burst2(struct ast_device *ast, u32 datagen)
421
-
{
422
-
return mmc_test2(ast, datagen, 0x41);
423
-
}
424
-
425
-
static bool mmc_test_single(struct ast_device *ast, u32 datagen)
426
-
{
427
-
return mmc_test(ast, datagen, 0xc5);
428
-
}
429
-
430
-
static u32 mmc_test_single2(struct ast_device *ast, u32 datagen)
431
-
{
432
-
return mmc_test2(ast, datagen, 0x05);
433
-
}
434
-
435
-
static int cbr_test(struct ast_device *ast)
436
-
{
437
-
u32 data;
438
-
int i;
439
-
data = mmc_test_single2(ast, 0);
440
-
if ((data & 0xff) && (data & 0xff00))
441
-
return 0;
442
-
for (i = 0; i < 8; i++) {
443
-
data = mmc_test_burst2(ast, i);
444
-
if ((data & 0xff) && (data & 0xff00))
445
-
return 0;
446
-
}
447
-
if (!data)
448
-
return 3;
449
-
else if (data & 0xff)
450
-
return 2;
451
-
return 1;
452
-
}
453
-
454
-
static int cbr_scan(struct ast_device *ast)
455
-
{
456
-
u32 data, data2, patcnt, loop;
457
-
458
-
data2 = 3;
459
-
for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
460
-
ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
461
-
for (loop = 0; loop < CBR_PASSNUM2; loop++) {
462
-
if ((data = cbr_test(ast)) != 0) {
463
-
data2 &= data;
464
-
if (!data2)
465
-
return 0;
466
-
break;
467
-
}
468
-
}
469
-
if (loop == CBR_PASSNUM2)
470
-
return 0;
471
-
}
472
-
return data2;
473
-
}
474
-
475
-
static u32 cbr_test2(struct ast_device *ast)
476
-
{
477
-
u32 data;
478
-
479
-
data = mmc_test_burst2(ast, 0);
480
-
if (data == 0xffff)
481
-
return 0;
482
-
data |= mmc_test_single2(ast, 0);
483
-
if (data == 0xffff)
484
-
return 0;
485
-
486
-
return ~data & 0xffff;
487
-
}
488
-
489
-
static u32 cbr_scan2(struct ast_device *ast)
490
-
{
491
-
u32 data, data2, patcnt, loop;
492
-
493
-
data2 = 0xffff;
494
-
for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
495
-
ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
496
-
for (loop = 0; loop < CBR_PASSNUM2; loop++) {
497
-
if ((data = cbr_test2(ast)) != 0) {
498
-
data2 &= data;
499
-
if (!data2)
500
-
return 0;
501
-
break;
502
-
}
503
-
}
504
-
if (loop == CBR_PASSNUM2)
505
-
return 0;
506
-
}
507
-
return data2;
508
-
}
509
-
510
-
static bool cbr_test3(struct ast_device *ast)
511
-
{
512
-
if (!mmc_test_burst(ast, 0))
513
-
return false;
514
-
if (!mmc_test_single(ast, 0))
515
-
return false;
516
-
return true;
517
-
}
518
-
519
-
static bool cbr_scan3(struct ast_device *ast)
520
-
{
521
-
u32 patcnt, loop;
522
-
523
-
for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
524
-
ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
525
-
for (loop = 0; loop < 2; loop++) {
526
-
if (cbr_test3(ast))
527
-
break;
528
-
}
529
-
if (loop == 2)
530
-
return false;
531
-
}
532
-
return true;
533
-
}
534
-
535
-
static bool finetuneDQI_L(struct ast_device *ast, struct ast2300_dram_param *param)
536
-
{
537
-
u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, retry = 0;
538
-
bool status = false;
539
-
FINETUNE_START:
540
-
for (cnt = 0; cnt < 16; cnt++) {
541
-
dllmin[cnt] = 0xff;
542
-
dllmax[cnt] = 0x0;
543
-
}
544
-
passcnt = 0;
545
-
for (dlli = 0; dlli < 76; dlli++) {
546
-
ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
547
-
ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE1);
548
-
data = cbr_scan2(ast);
549
-
if (data != 0) {
550
-
mask = 0x00010001;
551
-
for (cnt = 0; cnt < 16; cnt++) {
552
-
if (data & mask) {
553
-
if (dllmin[cnt] > dlli) {
554
-
dllmin[cnt] = dlli;
555
-
}
556
-
if (dllmax[cnt] < dlli) {
557
-
dllmax[cnt] = dlli;
558
-
}
559
-
}
560
-
mask <<= 1;
561
-
}
562
-
passcnt++;
563
-
} else if (passcnt >= CBR_THRESHOLD2) {
564
-
break;
565
-
}
566
-
}
567
-
gold_sadj[0] = 0x0;
568
-
passcnt = 0;
569
-
for (cnt = 0; cnt < 16; cnt++) {
570
-
if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
571
-
gold_sadj[0] += dllmin[cnt];
572
-
passcnt++;
573
-
}
574
-
}
575
-
if (retry++ > 10)
576
-
goto FINETUNE_DONE;
577
-
if (passcnt != 16) {
578
-
goto FINETUNE_START;
579
-
}
580
-
status = true;
581
-
FINETUNE_DONE:
582
-
gold_sadj[0] = gold_sadj[0] >> 4;
583
-
gold_sadj[1] = gold_sadj[0];
584
-
585
-
data = 0;
586
-
for (cnt = 0; cnt < 8; cnt++) {
587
-
data >>= 3;
588
-
if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
589
-
dlli = dllmin[cnt];
590
-
if (gold_sadj[0] >= dlli) {
591
-
dlli = ((gold_sadj[0] - dlli) * 19) >> 5;
592
-
if (dlli > 3) {
593
-
dlli = 3;
594
-
}
595
-
} else {
596
-
dlli = ((dlli - gold_sadj[0]) * 19) >> 5;
597
-
if (dlli > 4) {
598
-
dlli = 4;
599
-
}
600
-
dlli = (8 - dlli) & 0x7;
601
-
}
602
-
data |= dlli << 21;
603
-
}
604
-
}
605
-
ast_moutdwm(ast, 0x1E6E0080, data);
606
-
607
-
data = 0;
608
-
for (cnt = 8; cnt < 16; cnt++) {
609
-
data >>= 3;
610
-
if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
611
-
dlli = dllmin[cnt];
612
-
if (gold_sadj[1] >= dlli) {
613
-
dlli = ((gold_sadj[1] - dlli) * 19) >> 5;
614
-
if (dlli > 3) {
615
-
dlli = 3;
616
-
} else {
617
-
dlli = (dlli - 1) & 0x7;
618
-
}
619
-
} else {
620
-
dlli = ((dlli - gold_sadj[1]) * 19) >> 5;
621
-
dlli += 1;
622
-
if (dlli > 4) {
623
-
dlli = 4;
624
-
}
625
-
dlli = (8 - dlli) & 0x7;
626
-
}
627
-
data |= dlli << 21;
628
-
}
629
-
}
630
-
ast_moutdwm(ast, 0x1E6E0084, data);
631
-
return status;
632
-
} /* finetuneDQI_L */
633
-
634
-
static void finetuneDQSI(struct ast_device *ast)
635
-
{
636
-
u32 dlli, dqsip, dqidly;
637
-
u32 reg_mcr18, reg_mcr0c, passcnt[2], diff;
638
-
u32 g_dqidly, g_dqsip, g_margin, g_side;
639
-
u16 pass[32][2][2];
640
-
char tag[2][76];
641
-
642
-
/* Disable DQI CBR */
643
-
reg_mcr0c = ast_mindwm(ast, 0x1E6E000C);
644
-
reg_mcr18 = ast_mindwm(ast, 0x1E6E0018);
645
-
reg_mcr18 &= 0x0000ffff;
646
-
ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
647
-
648
-
for (dlli = 0; dlli < 76; dlli++) {
649
-
tag[0][dlli] = 0x0;
650
-
tag[1][dlli] = 0x0;
651
-
}
652
-
for (dqidly = 0; dqidly < 32; dqidly++) {
653
-
pass[dqidly][0][0] = 0xff;
654
-
pass[dqidly][0][1] = 0x0;
655
-
pass[dqidly][1][0] = 0xff;
656
-
pass[dqidly][1][1] = 0x0;
657
-
}
658
-
for (dqidly = 0; dqidly < 32; dqidly++) {
659
-
passcnt[0] = passcnt[1] = 0;
660
-
for (dqsip = 0; dqsip < 2; dqsip++) {
661
-
ast_moutdwm(ast, 0x1E6E000C, 0);
662
-
ast_moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23));
663
-
ast_moutdwm(ast, 0x1E6E000C, reg_mcr0c);
664
-
for (dlli = 0; dlli < 76; dlli++) {
665
-
ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
666
-
ast_moutdwm(ast, 0x1E6E0070, 0);
667
-
ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE0);
668
-
if (cbr_scan3(ast)) {
669
-
if (dlli == 0)
670
-
break;
671
-
passcnt[dqsip]++;
672
-
tag[dqsip][dlli] = 'P';
673
-
if (dlli < pass[dqidly][dqsip][0])
674
-
pass[dqidly][dqsip][0] = (u16) dlli;
675
-
if (dlli > pass[dqidly][dqsip][1])
676
-
pass[dqidly][dqsip][1] = (u16) dlli;
677
-
} else if (passcnt[dqsip] >= 5)
678
-
break;
679
-
else {
680
-
pass[dqidly][dqsip][0] = 0xff;
681
-
pass[dqidly][dqsip][1] = 0x0;
682
-
}
683
-
}
684
-
}
685
-
if (passcnt[0] == 0 && passcnt[1] == 0)
686
-
dqidly++;
687
-
}
688
-
/* Search margin */
689
-
g_dqidly = g_dqsip = g_margin = g_side = 0;
690
-
691
-
for (dqidly = 0; dqidly < 32; dqidly++) {
692
-
for (dqsip = 0; dqsip < 2; dqsip++) {
693
-
if (pass[dqidly][dqsip][0] > pass[dqidly][dqsip][1])
694
-
continue;
695
-
diff = pass[dqidly][dqsip][1] - pass[dqidly][dqsip][0];
696
-
if ((diff+2) < g_margin)
697
-
continue;
698
-
passcnt[0] = passcnt[1] = 0;
699
-
for (dlli = pass[dqidly][dqsip][0]; dlli > 0 && tag[dqsip][dlli] != 0; dlli--, passcnt[0]++);
700
-
for (dlli = pass[dqidly][dqsip][1]; dlli < 76 && tag[dqsip][dlli] != 0; dlli++, passcnt[1]++);
701
-
if (passcnt[0] > passcnt[1])
702
-
passcnt[0] = passcnt[1];
703
-
passcnt[1] = 0;
704
-
if (passcnt[0] > g_side)
705
-
passcnt[1] = passcnt[0] - g_side;
706
-
if (diff > (g_margin+1) && (passcnt[1] > 0 || passcnt[0] > 8)) {
707
-
g_margin = diff;
708
-
g_dqidly = dqidly;
709
-
g_dqsip = dqsip;
710
-
g_side = passcnt[0];
711
-
} else if (passcnt[1] > 1 && g_side < 8) {
712
-
if (diff > g_margin)
713
-
g_margin = diff;
714
-
g_dqidly = dqidly;
715
-
g_dqsip = dqsip;
716
-
g_side = passcnt[0];
717
-
}
718
-
}
719
-
}
720
-
reg_mcr18 = reg_mcr18 | (g_dqidly << 16) | (g_dqsip << 23);
721
-
ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
722
-
723
-
}
724
-
static bool cbr_dll2(struct ast_device *ast, struct ast2300_dram_param *param)
725
-
{
726
-
u32 dllmin[2], dllmax[2], dlli, data, passcnt, retry = 0;
727
-
bool status = false;
728
-
729
-
finetuneDQSI(ast);
730
-
if (finetuneDQI_L(ast, param) == false)
731
-
return status;
732
-
733
-
CBR_START2:
734
-
dllmin[0] = dllmin[1] = 0xff;
735
-
dllmax[0] = dllmax[1] = 0x0;
736
-
passcnt = 0;
737
-
for (dlli = 0; dlli < 76; dlli++) {
738
-
ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
739
-
ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
740
-
data = cbr_scan(ast);
741
-
if (data != 0) {
742
-
if (data & 0x1) {
743
-
if (dllmin[0] > dlli) {
744
-
dllmin[0] = dlli;
745
-
}
746
-
if (dllmax[0] < dlli) {
747
-
dllmax[0] = dlli;
748
-
}
749
-
}
750
-
if (data & 0x2) {
751
-
if (dllmin[1] > dlli) {
752
-
dllmin[1] = dlli;
753
-
}
754
-
if (dllmax[1] < dlli) {
755
-
dllmax[1] = dlli;
756
-
}
757
-
}
758
-
passcnt++;
759
-
} else if (passcnt >= CBR_THRESHOLD) {
760
-
break;
761
-
}
762
-
}
763
-
if (retry++ > 10)
764
-
goto CBR_DONE2;
765
-
if (dllmax[0] == 0 || (dllmax[0]-dllmin[0]) < CBR_THRESHOLD) {
766
-
goto CBR_START2;
767
-
}
768
-
if (dllmax[1] == 0 || (dllmax[1]-dllmin[1]) < CBR_THRESHOLD) {
769
-
goto CBR_START2;
770
-
}
771
-
status = true;
772
-
CBR_DONE2:
773
-
dlli = (dllmin[1] + dllmax[1]) >> 1;
774
-
dlli <<= 8;
775
-
dlli += (dllmin[0] + dllmax[0]) >> 1;
776
-
ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16));
777
-
return status;
778
-
} /* CBRDLL2 */
779
-
780
-
static void get_ddr3_info(struct ast_device *ast, struct ast2300_dram_param *param)
781
-
{
782
-
u32 trap, trap_AC2, trap_MRS;
783
-
784
-
ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
785
-
786
-
/* Ger trap info */
787
-
trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
788
-
trap_AC2 = 0x00020000 + (trap << 16);
789
-
trap_AC2 |= 0x00300000 + ((trap & 0x2) << 19);
790
-
trap_MRS = 0x00000010 + (trap << 4);
791
-
trap_MRS |= ((trap & 0x2) << 18);
792
-
793
-
param->reg_MADJ = 0x00034C4C;
794
-
param->reg_SADJ = 0x00001800;
795
-
param->reg_DRV = 0x000000F0;
796
-
param->reg_PERIOD = param->dram_freq;
797
-
param->rodt = 0;
798
-
799
-
switch (param->dram_freq) {
800
-
case 336:
801
-
ast_moutdwm(ast, 0x1E6E2020, 0x0190);
802
-
param->wodt = 0;
803
-
param->reg_AC1 = 0x22202725;
804
-
param->reg_AC2 = 0xAA007613 | trap_AC2;
805
-
param->reg_DQSIC = 0x000000BA;
806
-
param->reg_MRS = 0x04001400 | trap_MRS;
807
-
param->reg_EMRS = 0x00000000;
808
-
param->reg_IOZ = 0x00000023;
809
-
param->reg_DQIDLY = 0x00000074;
810
-
param->reg_FREQ = 0x00004DC0;
811
-
param->madj_max = 96;
812
-
param->dll2_finetune_step = 3;
813
-
switch (param->dram_chipid) {
814
-
default:
815
-
case AST_DRAM_512Mx16:
816
-
case AST_DRAM_1Gx16:
817
-
param->reg_AC2 = 0xAA007613 | trap_AC2;
818
-
break;
819
-
case AST_DRAM_2Gx16:
820
-
param->reg_AC2 = 0xAA00761C | trap_AC2;
821
-
break;
822
-
case AST_DRAM_4Gx16:
823
-
param->reg_AC2 = 0xAA007636 | trap_AC2;
824
-
break;
825
-
}
826
-
break;
827
-
default:
828
-
case 396:
829
-
ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
830
-
param->wodt = 1;
831
-
param->reg_AC1 = 0x33302825;
832
-
param->reg_AC2 = 0xCC009617 | trap_AC2;
833
-
param->reg_DQSIC = 0x000000E2;
834
-
param->reg_MRS = 0x04001600 | trap_MRS;
835
-
param->reg_EMRS = 0x00000000;
836
-
param->reg_IOZ = 0x00000034;
837
-
param->reg_DRV = 0x000000FA;
838
-
param->reg_DQIDLY = 0x00000089;
839
-
param->reg_FREQ = 0x00005040;
840
-
param->madj_max = 96;
841
-
param->dll2_finetune_step = 4;
842
-
843
-
switch (param->dram_chipid) {
844
-
default:
845
-
case AST_DRAM_512Mx16:
846
-
case AST_DRAM_1Gx16:
847
-
param->reg_AC2 = 0xCC009617 | trap_AC2;
848
-
break;
849
-
case AST_DRAM_2Gx16:
850
-
param->reg_AC2 = 0xCC009622 | trap_AC2;
851
-
break;
852
-
case AST_DRAM_4Gx16:
853
-
param->reg_AC2 = 0xCC00963F | trap_AC2;
854
-
break;
855
-
}
856
-
break;
857
-
858
-
case 408:
859
-
ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
860
-
param->wodt = 1;
861
-
param->reg_AC1 = 0x33302825;
862
-
param->reg_AC2 = 0xCC009617 | trap_AC2;
863
-
param->reg_DQSIC = 0x000000E2;
864
-
param->reg_MRS = 0x04001600 | trap_MRS;
865
-
param->reg_EMRS = 0x00000000;
866
-
param->reg_IOZ = 0x00000023;
867
-
param->reg_DRV = 0x000000FA;
868
-
param->reg_DQIDLY = 0x00000089;
869
-
param->reg_FREQ = 0x000050C0;
870
-
param->madj_max = 96;
871
-
param->dll2_finetune_step = 4;
872
-
873
-
switch (param->dram_chipid) {
874
-
default:
875
-
case AST_DRAM_512Mx16:
876
-
case AST_DRAM_1Gx16:
877
-
param->reg_AC2 = 0xCC009617 | trap_AC2;
878
-
break;
879
-
case AST_DRAM_2Gx16:
880
-
param->reg_AC2 = 0xCC009622 | trap_AC2;
881
-
break;
882
-
case AST_DRAM_4Gx16:
883
-
param->reg_AC2 = 0xCC00963F | trap_AC2;
884
-
break;
885
-
}
886
-
887
-
break;
888
-
case 456:
889
-
ast_moutdwm(ast, 0x1E6E2020, 0x0230);
890
-
param->wodt = 0;
891
-
param->reg_AC1 = 0x33302926;
892
-
param->reg_AC2 = 0xCD44961A;
893
-
param->reg_DQSIC = 0x000000FC;
894
-
param->reg_MRS = 0x00081830;
895
-
param->reg_EMRS = 0x00000000;
896
-
param->reg_IOZ = 0x00000045;
897
-
param->reg_DQIDLY = 0x00000097;
898
-
param->reg_FREQ = 0x000052C0;
899
-
param->madj_max = 88;
900
-
param->dll2_finetune_step = 4;
901
-
break;
902
-
case 504:
903
-
ast_moutdwm(ast, 0x1E6E2020, 0x0270);
904
-
param->wodt = 1;
905
-
param->reg_AC1 = 0x33302926;
906
-
param->reg_AC2 = 0xDE44A61D;
907
-
param->reg_DQSIC = 0x00000117;
908
-
param->reg_MRS = 0x00081A30;
909
-
param->reg_EMRS = 0x00000000;
910
-
param->reg_IOZ = 0x070000BB;
911
-
param->reg_DQIDLY = 0x000000A0;
912
-
param->reg_FREQ = 0x000054C0;
913
-
param->madj_max = 79;
914
-
param->dll2_finetune_step = 4;
915
-
break;
916
-
case 528:
917
-
ast_moutdwm(ast, 0x1E6E2020, 0x0290);
918
-
param->wodt = 1;
919
-
param->rodt = 1;
920
-
param->reg_AC1 = 0x33302926;
921
-
param->reg_AC2 = 0xEF44B61E;
922
-
param->reg_DQSIC = 0x00000125;
923
-
param->reg_MRS = 0x00081A30;
924
-
param->reg_EMRS = 0x00000040;
925
-
param->reg_DRV = 0x000000F5;
926
-
param->reg_IOZ = 0x00000023;
927
-
param->reg_DQIDLY = 0x00000088;
928
-
param->reg_FREQ = 0x000055C0;
929
-
param->madj_max = 76;
930
-
param->dll2_finetune_step = 3;
931
-
break;
932
-
case 576:
933
-
ast_moutdwm(ast, 0x1E6E2020, 0x0140);
934
-
param->reg_MADJ = 0x00136868;
935
-
param->reg_SADJ = 0x00004534;
936
-
param->wodt = 1;
937
-
param->rodt = 1;
938
-
param->reg_AC1 = 0x33302A37;
939
-
param->reg_AC2 = 0xEF56B61E;
940
-
param->reg_DQSIC = 0x0000013F;
941
-
param->reg_MRS = 0x00101A50;
942
-
param->reg_EMRS = 0x00000040;
943
-
param->reg_DRV = 0x000000FA;
944
-
param->reg_IOZ = 0x00000023;
945
-
param->reg_DQIDLY = 0x00000078;
946
-
param->reg_FREQ = 0x000057C0;
947
-
param->madj_max = 136;
948
-
param->dll2_finetune_step = 3;
949
-
break;
950
-
case 600:
951
-
ast_moutdwm(ast, 0x1E6E2020, 0x02E1);
952
-
param->reg_MADJ = 0x00136868;
953
-
param->reg_SADJ = 0x00004534;
954
-
param->wodt = 1;
955
-
param->rodt = 1;
956
-
param->reg_AC1 = 0x32302A37;
957
-
param->reg_AC2 = 0xDF56B61F;
958
-
param->reg_DQSIC = 0x0000014D;
959
-
param->reg_MRS = 0x00101A50;
960
-
param->reg_EMRS = 0x00000004;
961
-
param->reg_DRV = 0x000000F5;
962
-
param->reg_IOZ = 0x00000023;
963
-
param->reg_DQIDLY = 0x00000078;
964
-
param->reg_FREQ = 0x000058C0;
965
-
param->madj_max = 132;
966
-
param->dll2_finetune_step = 3;
967
-
break;
968
-
case 624:
969
-
ast_moutdwm(ast, 0x1E6E2020, 0x0160);
970
-
param->reg_MADJ = 0x00136868;
971
-
param->reg_SADJ = 0x00004534;
972
-
param->wodt = 1;
973
-
param->rodt = 1;
974
-
param->reg_AC1 = 0x32302A37;
975
-
param->reg_AC2 = 0xEF56B621;
976
-
param->reg_DQSIC = 0x0000015A;
977
-
param->reg_MRS = 0x02101A50;
978
-
param->reg_EMRS = 0x00000004;
979
-
param->reg_DRV = 0x000000F5;
980
-
param->reg_IOZ = 0x00000034;
981
-
param->reg_DQIDLY = 0x00000078;
982
-
param->reg_FREQ = 0x000059C0;
983
-
param->madj_max = 128;
984
-
param->dll2_finetune_step = 3;
985
-
break;
986
-
} /* switch freq */
987
-
988
-
switch (param->dram_chipid) {
989
-
case AST_DRAM_512Mx16:
990
-
param->dram_config = 0x130;
991
-
break;
992
-
default:
993
-
case AST_DRAM_1Gx16:
994
-
param->dram_config = 0x131;
995
-
break;
996
-
case AST_DRAM_2Gx16:
997
-
param->dram_config = 0x132;
998
-
break;
999
-
case AST_DRAM_4Gx16:
1000
-
param->dram_config = 0x133;
1001
-
break;
1002
-
} /* switch size */
1003
-
1004
-
switch (param->vram_size) {
1005
-
default:
1006
-
case SZ_8M:
1007
-
param->dram_config |= 0x00;
1008
-
break;
1009
-
case SZ_16M:
1010
-
param->dram_config |= 0x04;
1011
-
break;
1012
-
case SZ_32M:
1013
-
param->dram_config |= 0x08;
1014
-
break;
1015
-
case SZ_64M:
1016
-
param->dram_config |= 0x0c;
1017
-
break;
1018
-
}
1019
-
1020
-
}
1021
-
1022
-
static void ddr3_init(struct ast_device *ast, struct ast2300_dram_param *param)
1023
-
{
1024
-
u32 data, data2, retry = 0;
1025
-
1026
-
ddr3_init_start:
1027
-
ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1028
-
ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1029
-
ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1030
-
ast_moutdwm(ast, 0x1E6E0034, 0x00000000);
1031
-
udelay(10);
1032
-
ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1033
-
ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1034
-
udelay(10);
1035
-
ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1036
-
udelay(10);
1037
-
1038
-
ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1039
-
ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1040
-
ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1041
-
ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1042
-
ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1043
-
ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1044
-
ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1045
-
ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1046
-
ast_moutdwm(ast, 0x1E6E0018, 0x4000A170);
1047
-
ast_moutdwm(ast, 0x1E6E0018, 0x00002370);
1048
-
ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1049
-
ast_moutdwm(ast, 0x1E6E0040, 0xFF444444);
1050
-
ast_moutdwm(ast, 0x1E6E0044, 0x22222222);
1051
-
ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1052
-
ast_moutdwm(ast, 0x1E6E004C, 0x00000002);
1053
-
ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1054
-
ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1055
-
ast_moutdwm(ast, 0x1E6E0054, 0);
1056
-
ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1057
-
ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1058
-
ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1059
-
ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1060
-
ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1061
-
ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1062
-
/* Wait MCLK2X lock to MCLK */
1063
-
do {
1064
-
data = ast_mindwm(ast, 0x1E6E001C);
1065
-
} while (!(data & 0x08000000));
1066
-
data = ast_mindwm(ast, 0x1E6E001C);
1067
-
data = (data >> 8) & 0xff;
1068
-
while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1069
-
data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1070
-
if ((data2 & 0xff) > param->madj_max) {
1071
-
break;
1072
-
}
1073
-
ast_moutdwm(ast, 0x1E6E0064, data2);
1074
-
if (data2 & 0x00100000) {
1075
-
data2 = ((data2 & 0xff) >> 3) + 3;
1076
-
} else {
1077
-
data2 = ((data2 & 0xff) >> 2) + 5;
1078
-
}
1079
-
data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1080
-
data2 += data & 0xff;
1081
-
data = data | (data2 << 8);
1082
-
ast_moutdwm(ast, 0x1E6E0068, data);
1083
-
udelay(10);
1084
-
ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1085
-
udelay(10);
1086
-
data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1087
-
ast_moutdwm(ast, 0x1E6E0018, data);
1088
-
data = data | 0x200;
1089
-
ast_moutdwm(ast, 0x1E6E0018, data);
1090
-
do {
1091
-
data = ast_mindwm(ast, 0x1E6E001C);
1092
-
} while (!(data & 0x08000000));
1093
-
1094
-
data = ast_mindwm(ast, 0x1E6E001C);
1095
-
data = (data >> 8) & 0xff;
1096
-
}
1097
-
ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff);
1098
-
data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1099
-
ast_moutdwm(ast, 0x1E6E0018, data);
1100
-
1101
-
ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1102
-
ast_moutdwm(ast, 0x1E6E000C, 0x00000040);
1103
-
udelay(50);
1104
-
/* Mode Register Setting */
1105
-
ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1106
-
ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1107
-
ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1108
-
ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1109
-
ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1110
-
ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1111
-
ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1112
-
ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1113
-
ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1114
-
1115
-
ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1116
-
data = 0;
1117
-
if (param->wodt) {
1118
-
data = 0x300;
1119
-
}
1120
-
if (param->rodt) {
1121
-
data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1122
-
}
1123
-
ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1124
-
1125
-
/* Calibrate the DQSI delay */
1126
-
if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1127
-
goto ddr3_init_start;
1128
-
1129
-
ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1130
-
/* ECC Memory Initialization */
1131
-
#ifdef ECC
1132
-
ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1133
-
ast_moutdwm(ast, 0x1E6E0070, 0x221);
1134
-
do {
1135
-
data = ast_mindwm(ast, 0x1E6E0070);
1136
-
} while (!(data & 0x00001000));
1137
-
ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1138
-
ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1139
-
ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1140
-
#endif
1141
-
1142
-
1143
-
}
1144
-
1145
-
static void get_ddr2_info(struct ast_device *ast, struct ast2300_dram_param *param)
1146
-
{
1147
-
u32 trap, trap_AC2, trap_MRS;
1148
-
1149
-
ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1150
-
1151
-
/* Ger trap info */
1152
-
trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
1153
-
trap_AC2 = (trap << 20) | (trap << 16);
1154
-
trap_AC2 += 0x00110000;
1155
-
trap_MRS = 0x00000040 | (trap << 4);
1156
-
1157
-
1158
-
param->reg_MADJ = 0x00034C4C;
1159
-
param->reg_SADJ = 0x00001800;
1160
-
param->reg_DRV = 0x000000F0;
1161
-
param->reg_PERIOD = param->dram_freq;
1162
-
param->rodt = 0;
1163
-
1164
-
switch (param->dram_freq) {
1165
-
case 264:
1166
-
ast_moutdwm(ast, 0x1E6E2020, 0x0130);
1167
-
param->wodt = 0;
1168
-
param->reg_AC1 = 0x11101513;
1169
-
param->reg_AC2 = 0x78117011;
1170
-
param->reg_DQSIC = 0x00000092;
1171
-
param->reg_MRS = 0x00000842;
1172
-
param->reg_EMRS = 0x00000000;
1173
-
param->reg_DRV = 0x000000F0;
1174
-
param->reg_IOZ = 0x00000034;
1175
-
param->reg_DQIDLY = 0x0000005A;
1176
-
param->reg_FREQ = 0x00004AC0;
1177
-
param->madj_max = 138;
1178
-
param->dll2_finetune_step = 3;
1179
-
break;
1180
-
case 336:
1181
-
ast_moutdwm(ast, 0x1E6E2020, 0x0190);
1182
-
param->wodt = 1;
1183
-
param->reg_AC1 = 0x22202613;
1184
-
param->reg_AC2 = 0xAA009016 | trap_AC2;
1185
-
param->reg_DQSIC = 0x000000BA;
1186
-
param->reg_MRS = 0x00000A02 | trap_MRS;
1187
-
param->reg_EMRS = 0x00000040;
1188
-
param->reg_DRV = 0x000000FA;
1189
-
param->reg_IOZ = 0x00000034;
1190
-
param->reg_DQIDLY = 0x00000074;
1191
-
param->reg_FREQ = 0x00004DC0;
1192
-
param->madj_max = 96;
1193
-
param->dll2_finetune_step = 3;
1194
-
switch (param->dram_chipid) {
1195
-
default:
1196
-
case AST_DRAM_512Mx16:
1197
-
param->reg_AC2 = 0xAA009012 | trap_AC2;
1198
-
break;
1199
-
case AST_DRAM_1Gx16:
1200
-
param->reg_AC2 = 0xAA009016 | trap_AC2;
1201
-
break;
1202
-
case AST_DRAM_2Gx16:
1203
-
param->reg_AC2 = 0xAA009023 | trap_AC2;
1204
-
break;
1205
-
case AST_DRAM_4Gx16:
1206
-
param->reg_AC2 = 0xAA00903B | trap_AC2;
1207
-
break;
1208
-
}
1209
-
break;
1210
-
default:
1211
-
case 396:
1212
-
ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
1213
-
param->wodt = 1;
1214
-
param->rodt = 0;
1215
-
param->reg_AC1 = 0x33302714;
1216
-
param->reg_AC2 = 0xCC00B01B | trap_AC2;
1217
-
param->reg_DQSIC = 0x000000E2;
1218
-
param->reg_MRS = 0x00000C02 | trap_MRS;
1219
-
param->reg_EMRS = 0x00000040;
1220
-
param->reg_DRV = 0x000000FA;
1221
-
param->reg_IOZ = 0x00000034;
1222
-
param->reg_DQIDLY = 0x00000089;
1223
-
param->reg_FREQ = 0x00005040;
1224
-
param->madj_max = 96;
1225
-
param->dll2_finetune_step = 4;
1226
-
1227
-
switch (param->dram_chipid) {
1228
-
case AST_DRAM_512Mx16:
1229
-
param->reg_AC2 = 0xCC00B016 | trap_AC2;
1230
-
break;
1231
-
default:
1232
-
case AST_DRAM_1Gx16:
1233
-
param->reg_AC2 = 0xCC00B01B | trap_AC2;
1234
-
break;
1235
-
case AST_DRAM_2Gx16:
1236
-
param->reg_AC2 = 0xCC00B02B | trap_AC2;
1237
-
break;
1238
-
case AST_DRAM_4Gx16:
1239
-
param->reg_AC2 = 0xCC00B03F | trap_AC2;
1240
-
break;
1241
-
}
1242
-
1243
-
break;
1244
-
1245
-
case 408:
1246
-
ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
1247
-
param->wodt = 1;
1248
-
param->rodt = 0;
1249
-
param->reg_AC1 = 0x33302714;
1250
-
param->reg_AC2 = 0xCC00B01B | trap_AC2;
1251
-
param->reg_DQSIC = 0x000000E2;
1252
-
param->reg_MRS = 0x00000C02 | trap_MRS;
1253
-
param->reg_EMRS = 0x00000040;
1254
-
param->reg_DRV = 0x000000FA;
1255
-
param->reg_IOZ = 0x00000034;
1256
-
param->reg_DQIDLY = 0x00000089;
1257
-
param->reg_FREQ = 0x000050C0;
1258
-
param->madj_max = 96;
1259
-
param->dll2_finetune_step = 4;
1260
-
1261
-
switch (param->dram_chipid) {
1262
-
case AST_DRAM_512Mx16:
1263
-
param->reg_AC2 = 0xCC00B016 | trap_AC2;
1264
-
break;
1265
-
default:
1266
-
case AST_DRAM_1Gx16:
1267
-
param->reg_AC2 = 0xCC00B01B | trap_AC2;
1268
-
break;
1269
-
case AST_DRAM_2Gx16:
1270
-
param->reg_AC2 = 0xCC00B02B | trap_AC2;
1271
-
break;
1272
-
case AST_DRAM_4Gx16:
1273
-
param->reg_AC2 = 0xCC00B03F | trap_AC2;
1274
-
break;
1275
-
}
1276
-
1277
-
break;
1278
-
case 456:
1279
-
ast_moutdwm(ast, 0x1E6E2020, 0x0230);
1280
-
param->wodt = 0;
1281
-
param->reg_AC1 = 0x33302815;
1282
-
param->reg_AC2 = 0xCD44B01E;
1283
-
param->reg_DQSIC = 0x000000FC;
1284
-
param->reg_MRS = 0x00000E72;
1285
-
param->reg_EMRS = 0x00000000;
1286
-
param->reg_DRV = 0x00000000;
1287
-
param->reg_IOZ = 0x00000034;
1288
-
param->reg_DQIDLY = 0x00000097;
1289
-
param->reg_FREQ = 0x000052C0;
1290
-
param->madj_max = 88;
1291
-
param->dll2_finetune_step = 3;
1292
-
break;
1293
-
case 504:
1294
-
ast_moutdwm(ast, 0x1E6E2020, 0x0261);
1295
-
param->wodt = 1;
1296
-
param->rodt = 1;
1297
-
param->reg_AC1 = 0x33302815;
1298
-
param->reg_AC2 = 0xDE44C022;
1299
-
param->reg_DQSIC = 0x00000117;
1300
-
param->reg_MRS = 0x00000E72;
1301
-
param->reg_EMRS = 0x00000040;
1302
-
param->reg_DRV = 0x0000000A;
1303
-
param->reg_IOZ = 0x00000045;
1304
-
param->reg_DQIDLY = 0x000000A0;
1305
-
param->reg_FREQ = 0x000054C0;
1306
-
param->madj_max = 79;
1307
-
param->dll2_finetune_step = 3;
1308
-
break;
1309
-
case 528:
1310
-
ast_moutdwm(ast, 0x1E6E2020, 0x0120);
1311
-
param->wodt = 1;
1312
-
param->rodt = 1;
1313
-
param->reg_AC1 = 0x33302815;
1314
-
param->reg_AC2 = 0xEF44D024;
1315
-
param->reg_DQSIC = 0x00000125;
1316
-
param->reg_MRS = 0x00000E72;
1317
-
param->reg_EMRS = 0x00000004;
1318
-
param->reg_DRV = 0x000000F9;
1319
-
param->reg_IOZ = 0x00000045;
1320
-
param->reg_DQIDLY = 0x000000A7;
1321
-
param->reg_FREQ = 0x000055C0;
1322
-
param->madj_max = 76;
1323
-
param->dll2_finetune_step = 3;
1324
-
break;
1325
-
case 552:
1326
-
ast_moutdwm(ast, 0x1E6E2020, 0x02A1);
1327
-
param->wodt = 1;
1328
-
param->rodt = 1;
1329
-
param->reg_AC1 = 0x43402915;
1330
-
param->reg_AC2 = 0xFF44E025;
1331
-
param->reg_DQSIC = 0x00000132;
1332
-
param->reg_MRS = 0x00000E72;
1333
-
param->reg_EMRS = 0x00000040;
1334
-
param->reg_DRV = 0x0000000A;
1335
-
param->reg_IOZ = 0x00000045;
1336
-
param->reg_DQIDLY = 0x000000AD;
1337
-
param->reg_FREQ = 0x000056C0;
1338
-
param->madj_max = 76;
1339
-
param->dll2_finetune_step = 3;
1340
-
break;
1341
-
case 576:
1342
-
ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1343
-
param->wodt = 1;
1344
-
param->rodt = 1;
1345
-
param->reg_AC1 = 0x43402915;
1346
-
param->reg_AC2 = 0xFF44E027;
1347
-
param->reg_DQSIC = 0x0000013F;
1348
-
param->reg_MRS = 0x00000E72;
1349
-
param->reg_EMRS = 0x00000004;
1350
-
param->reg_DRV = 0x000000F5;
1351
-
param->reg_IOZ = 0x00000045;
1352
-
param->reg_DQIDLY = 0x000000B3;
1353
-
param->reg_FREQ = 0x000057C0;
1354
-
param->madj_max = 76;
1355
-
param->dll2_finetune_step = 3;
1356
-
break;
1357
-
}
1358
-
1359
-
switch (param->dram_chipid) {
1360
-
case AST_DRAM_512Mx16:
1361
-
param->dram_config = 0x100;
1362
-
break;
1363
-
default:
1364
-
case AST_DRAM_1Gx16:
1365
-
param->dram_config = 0x121;
1366
-
break;
1367
-
case AST_DRAM_2Gx16:
1368
-
param->dram_config = 0x122;
1369
-
break;
1370
-
case AST_DRAM_4Gx16:
1371
-
param->dram_config = 0x123;
1372
-
break;
1373
-
} /* switch size */
1374
-
1375
-
switch (param->vram_size) {
1376
-
default:
1377
-
case SZ_8M:
1378
-
param->dram_config |= 0x00;
1379
-
break;
1380
-
case SZ_16M:
1381
-
param->dram_config |= 0x04;
1382
-
break;
1383
-
case SZ_32M:
1384
-
param->dram_config |= 0x08;
1385
-
break;
1386
-
case SZ_64M:
1387
-
param->dram_config |= 0x0c;
1388
-
break;
1389
-
}
1390
-
}
1391
-
1392
-
static void ddr2_init(struct ast_device *ast, struct ast2300_dram_param *param)
1393
-
{
1394
-
u32 data, data2, retry = 0;
1395
-
1396
-
ddr2_init_start:
1397
-
ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1398
-
ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1399
-
ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1400
-
ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1401
-
ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1402
-
udelay(10);
1403
-
ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1404
-
udelay(10);
1405
-
1406
-
ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1407
-
ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1408
-
ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1409
-
ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1410
-
ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1411
-
ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1412
-
ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1413
-
ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1414
-
ast_moutdwm(ast, 0x1E6E0018, 0x4000A130);
1415
-
ast_moutdwm(ast, 0x1E6E0018, 0x00002330);
1416
-
ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1417
-
ast_moutdwm(ast, 0x1E6E0040, 0xFF808000);
1418
-
ast_moutdwm(ast, 0x1E6E0044, 0x88848466);
1419
-
ast_moutdwm(ast, 0x1E6E0048, 0x44440008);
1420
-
ast_moutdwm(ast, 0x1E6E004C, 0x00000000);
1421
-
ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1422
-
ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1423
-
ast_moutdwm(ast, 0x1E6E0054, 0);
1424
-
ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1425
-
ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1426
-
ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1427
-
ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1428
-
ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1429
-
ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1430
-
1431
-
/* Wait MCLK2X lock to MCLK */
1432
-
do {
1433
-
data = ast_mindwm(ast, 0x1E6E001C);
1434
-
} while (!(data & 0x08000000));
1435
-
data = ast_mindwm(ast, 0x1E6E001C);
1436
-
data = (data >> 8) & 0xff;
1437
-
while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1438
-
data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1439
-
if ((data2 & 0xff) > param->madj_max) {
1440
-
break;
1441
-
}
1442
-
ast_moutdwm(ast, 0x1E6E0064, data2);
1443
-
if (data2 & 0x00100000) {
1444
-
data2 = ((data2 & 0xff) >> 3) + 3;
1445
-
} else {
1446
-
data2 = ((data2 & 0xff) >> 2) + 5;
1447
-
}
1448
-
data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1449
-
data2 += data & 0xff;
1450
-
data = data | (data2 << 8);
1451
-
ast_moutdwm(ast, 0x1E6E0068, data);
1452
-
udelay(10);
1453
-
ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1454
-
udelay(10);
1455
-
data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1456
-
ast_moutdwm(ast, 0x1E6E0018, data);
1457
-
data = data | 0x200;
1458
-
ast_moutdwm(ast, 0x1E6E0018, data);
1459
-
do {
1460
-
data = ast_mindwm(ast, 0x1E6E001C);
1461
-
} while (!(data & 0x08000000));
1462
-
1463
-
data = ast_mindwm(ast, 0x1E6E001C);
1464
-
data = (data >> 8) & 0xff;
1465
-
}
1466
-
ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff);
1467
-
data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1468
-
ast_moutdwm(ast, 0x1E6E0018, data);
1469
-
1470
-
ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1471
-
ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1472
-
udelay(50);
1473
-
/* Mode Register Setting */
1474
-
ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1475
-
ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1476
-
ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1477
-
ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1478
-
ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1479
-
ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1480
-
1481
-
ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1482
-
ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1483
-
ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1484
-
ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380);
1485
-
ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1486
-
ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1487
-
ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1488
-
1489
-
ast_moutdwm(ast, 0x1E6E000C, 0x7FFF5C01);
1490
-
data = 0;
1491
-
if (param->wodt) {
1492
-
data = 0x500;
1493
-
}
1494
-
if (param->rodt) {
1495
-
data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1496
-
}
1497
-
ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1498
-
ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1499
-
1500
-
/* Calibrate the DQSI delay */
1501
-
if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1502
-
goto ddr2_init_start;
1503
-
1504
-
/* ECC Memory Initialization */
1505
-
#ifdef ECC
1506
-
ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1507
-
ast_moutdwm(ast, 0x1E6E0070, 0x221);
1508
-
do {
1509
-
data = ast_mindwm(ast, 0x1E6E0070);
1510
-
} while (!(data & 0x00001000));
1511
-
ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1512
-
ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1513
-
ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1514
-
#endif
1515
-
1516
-
}
1517
-
1518
-
static void ast_post_chip_2300(struct ast_device *ast)
1519
-
{
1520
-
struct ast2300_dram_param param;
1521
-
u32 temp;
1522
-
u8 reg;
1523
-
1524
-
reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
1525
-
if ((reg & 0x80) == 0) {/* vga only */
1526
-
ast_write32(ast, 0xf004, 0x1e6e0000);
1527
-
ast_write32(ast, 0xf000, 0x1);
1528
-
ast_write32(ast, 0x12000, 0x1688a8a8);
1529
-
do {
1530
-
;
1531
-
} while (ast_read32(ast, 0x12000) != 0x1);
1532
-
1533
-
ast_write32(ast, 0x10000, 0xfc600309);
1534
-
do {
1535
-
;
1536
-
} while (ast_read32(ast, 0x10000) != 0x1);
1537
-
1538
-
/* Slow down CPU/AHB CLK in VGA only mode */
1539
-
temp = ast_read32(ast, 0x12008);
1540
-
temp |= 0x73;
1541
-
ast_write32(ast, 0x12008, temp);
1542
-
1543
-
param.dram_freq = 396;
1544
-
param.dram_type = AST_DDR3;
1545
-
temp = ast_mindwm(ast, 0x1e6e2070);
1546
-
if (temp & 0x01000000)
1547
-
param.dram_type = AST_DDR2;
1548
-
switch (temp & 0x18000000) {
1549
-
case 0:
1550
-
param.dram_chipid = AST_DRAM_512Mx16;
1551
-
break;
1552
-
default:
1553
-
case 0x08000000:
1554
-
param.dram_chipid = AST_DRAM_1Gx16;
1555
-
break;
1556
-
case 0x10000000:
1557
-
param.dram_chipid = AST_DRAM_2Gx16;
1558
-
break;
1559
-
case 0x18000000:
1560
-
param.dram_chipid = AST_DRAM_4Gx16;
1561
-
break;
1562
-
}
1563
-
switch (temp & 0x0c) {
1564
-
default:
1565
-
case 0x00:
1566
-
param.vram_size = SZ_8M;
1567
-
break;
1568
-
1569
-
case 0x04:
1570
-
param.vram_size = SZ_16M;
1571
-
break;
1572
-
1573
-
case 0x08:
1574
-
param.vram_size = SZ_32M;
1575
-
break;
1576
-
1577
-
case 0x0c:
1578
-
param.vram_size = SZ_64M;
1579
-
break;
1580
-
}
1581
-
1582
-
if (param.dram_type == AST_DDR3) {
1583
-
get_ddr3_info(ast, ¶m);
1584
-
ddr3_init(ast, ¶m);
1585
-
} else {
1586
-
get_ddr2_info(ast, ¶m);
1587
-
ddr2_init(ast, ¶m);
1588
-
}
1589
-
1590
-
temp = ast_mindwm(ast, 0x1e6e2040);
1591
-
ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
1592
-
}
1593
-
1594
-
/* wait ready */
1595
-
do {
1596
-
reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
1597
-
} while ((reg & 0x40) == 0);
1598
457
}