drm/msm/dpu: Support CWB in dpu_hw_ctl · tjh.dev/kernel@0f3801d

+13

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

··· 2274 2274 intf_cfg.stream_sel = 0; /* Don't care value for video mode */ 2275 2275 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); 2276 2276 intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); 2277 + intf_cfg.cwb = dpu_enc->cwb_mask; 2277 2278 2278 2279 if (phys_enc->hw_intf) 2279 2280 intf_cfg.intf = phys_enc->hw_intf->idx; ··· 2297 2296 { 2298 2297 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 2299 2298 struct dpu_hw_cwb *hw_cwb; 2299 + struct dpu_hw_ctl *hw_ctl; 2300 2300 struct dpu_hw_cwb_setup_cfg cwb_cfg; 2301 2301 2302 2302 struct dpu_kms *dpu_kms; ··· 2307 2305 2308 2306 if (!phys_enc->hw_wb) 2309 2307 return; 2308 + 2309 + hw_ctl = phys_enc->hw_ctl; 2310 + 2311 + if (!phys_enc->hw_ctl) { 2312 + DPU_DEBUG("[wb:%d] no ctl assigned\n", 2313 + phys_enc->hw_wb->idx - WB_0); 2314 + return; 2315 + } 2310 2316 2311 2317 dpu_kms = phys_enc->dpu_kms; 2312 2318 global_state = dpu_kms_get_existing_global_state(dpu_kms); ··· 2348 2338 } 2349 2339 2350 2340 hw_cwb->ops.config_cwb(hw_cwb, &cwb_cfg); 2341 + 2342 + if (hw_ctl->ops.update_pending_flush_cwb) 2343 + hw_ctl->ops.update_pending_flush_cwb(hw_ctl, hw_cwb->idx); 2351 2344 } 2352 2345 } 2353 2346

+1

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c

··· 236 236 237 237 intf_cfg.intf = DPU_NONE; 238 238 intf_cfg.wb = hw_wb->idx; 239 + intf_cfg.cwb = dpu_encoder_helper_get_cwb_mask(phys_enc); 239 240 240 241 if (mode_3d && hw_pp && hw_pp->merge_3d) 241 242 intf_cfg.merge_3d = hw_pp->merge_3d->idx;

+29 -1

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

··· 1 1 // SPDX-License-Identifier: GPL-2.0-only 2 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 3 + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 4 */ 5 5 6 6 #include <linux/delay.h> ··· 31 31 #define CTL_MERGE_3D_ACTIVE 0x0E4 32 32 #define CTL_DSC_ACTIVE 0x0E8 33 33 #define CTL_WB_ACTIVE 0x0EC 34 + #define CTL_CWB_ACTIVE 0x0F0 34 35 #define CTL_INTF_ACTIVE 0x0F4 35 36 #define CTL_CDM_ACTIVE 0x0F8 36 37 #define CTL_FETCH_PIPE_ACTIVE 0x0FC 37 38 #define CTL_MERGE_3D_FLUSH 0x100 38 39 #define CTL_DSC_FLUSH 0x104 39 40 #define CTL_WB_FLUSH 0x108 41 + #define CTL_CWB_FLUSH 0x10C 40 42 #define CTL_INTF_FLUSH 0x110 41 43 #define CTL_CDM_FLUSH 0x114 42 44 #define CTL_PERIPH_FLUSH 0x128 ··· 55 53 #define PERIPH_IDX 30 56 54 #define INTF_IDX 31 57 55 #define WB_IDX 16 56 + #define CWB_IDX 28 58 57 #define DSPP_IDX 29 /* From DPU hw rev 7.x.x */ 59 58 #define CTL_INVALID_BIT 0xffff 60 59 #define CTL_DEFAULT_GROUP_ID 0xf ··· 113 110 ctx->pending_flush_mask = 0x0; 114 111 ctx->pending_intf_flush_mask = 0; 115 112 ctx->pending_wb_flush_mask = 0; 113 + ctx->pending_cwb_flush_mask = 0; 116 114 ctx->pending_merge_3d_flush_mask = 0; 117 115 ctx->pending_dsc_flush_mask = 0; 118 116 ctx->pending_cdm_flush_mask = 0; ··· 148 144 if (ctx->pending_flush_mask & BIT(WB_IDX)) 149 145 DPU_REG_WRITE(&ctx->hw, CTL_WB_FLUSH, 150 146 ctx->pending_wb_flush_mask); 147 + if (ctx->pending_flush_mask & BIT(CWB_IDX)) 148 + DPU_REG_WRITE(&ctx->hw, CTL_CWB_FLUSH, 149 + ctx->pending_cwb_flush_mask); 151 150 152 151 if (ctx->pending_flush_mask & BIT(DSPP_IDX)) 153 152 for (dspp = DSPP_0; dspp < DSPP_MAX; dspp++) { ··· 315 308 { 316 309 ctx->pending_wb_flush_mask |= BIT(wb - WB_0); 317 310 ctx->pending_flush_mask |= BIT(WB_IDX); 311 + } 312 + 313 + static void dpu_hw_ctl_update_pending_flush_cwb_v1(struct dpu_hw_ctl *ctx, 314 + enum dpu_cwb cwb) 315 + { 316 + ctx->pending_cwb_flush_mask |= BIT(cwb - CWB_0); 317 + ctx->pending_flush_mask |= BIT(CWB_IDX); 318 318 } 319 319 320 320 static void dpu_hw_ctl_update_pending_flush_intf_v1(struct dpu_hw_ctl *ctx, ··· 561 547 u32 intf_active = 0; 562 548 u32 dsc_active = 0; 563 549 u32 wb_active = 0; 550 + u32 cwb_active = 0; 564 551 u32 mode_sel = 0; 565 552 566 553 /* CTL_TOP[31:28] carries group_id to collate CTL paths ··· 576 561 577 562 intf_active = DPU_REG_READ(c, CTL_INTF_ACTIVE); 578 563 wb_active = DPU_REG_READ(c, CTL_WB_ACTIVE); 564 + cwb_active = DPU_REG_READ(c, CTL_CWB_ACTIVE); 579 565 dsc_active = DPU_REG_READ(c, CTL_DSC_ACTIVE); 580 566 581 567 if (cfg->intf) ··· 585 569 if (cfg->wb) 586 570 wb_active |= BIT(cfg->wb - WB_0); 587 571 572 + if (cfg->cwb) 573 + cwb_active |= cfg->cwb; 574 + 588 575 if (cfg->dsc) 589 576 dsc_active |= cfg->dsc; 590 577 591 578 DPU_REG_WRITE(c, CTL_TOP, mode_sel); 592 579 DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active); 593 580 DPU_REG_WRITE(c, CTL_WB_ACTIVE, wb_active); 581 + DPU_REG_WRITE(c, CTL_CWB_ACTIVE, cwb_active); 594 582 DPU_REG_WRITE(c, CTL_DSC_ACTIVE, dsc_active); 595 583 596 584 if (cfg->merge_3d) ··· 644 624 struct dpu_hw_blk_reg_map *c = &ctx->hw; 645 625 u32 intf_active = 0; 646 626 u32 wb_active = 0; 627 + u32 cwb_active = 0; 647 628 u32 merge3d_active = 0; 648 629 u32 dsc_active; 649 630 u32 cdm_active; ··· 670 649 intf_active = DPU_REG_READ(c, CTL_INTF_ACTIVE); 671 650 intf_active &= ~BIT(cfg->intf - INTF_0); 672 651 DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active); 652 + } 653 + 654 + if (cfg->cwb) { 655 + cwb_active = DPU_REG_READ(c, CTL_CWB_ACTIVE); 656 + cwb_active &= ~cfg->cwb; 657 + DPU_REG_WRITE(c, CTL_CWB_ACTIVE, cwb_active); 673 658 } 674 659 675 660 if (cfg->wb) { ··· 730 703 ops->update_pending_flush_merge_3d = 731 704 dpu_hw_ctl_update_pending_flush_merge_3d_v1; 732 705 ops->update_pending_flush_wb = dpu_hw_ctl_update_pending_flush_wb_v1; 706 + ops->update_pending_flush_cwb = dpu_hw_ctl_update_pending_flush_cwb_v1; 733 707 ops->update_pending_flush_dsc = 734 708 dpu_hw_ctl_update_pending_flush_dsc_v1; 735 709 ops->update_pending_flush_cdm = dpu_hw_ctl_update_pending_flush_cdm_v1;

+14 -1

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h

··· 1 1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 3 + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 4 */ 5 5 6 6 #ifndef _DPU_HW_CTL_H ··· 42 42 * @cdm: CDM block used 43 43 * @stream_sel: Stream selection for multi-stream interfaces 44 44 * @dsc: DSC BIT masks used 45 + * @cwb: CWB BIT masks used 45 46 */ 46 47 struct dpu_hw_intf_cfg { 47 48 enum dpu_intf intf; ··· 52 51 enum dpu_ctl_mode_sel intf_mode_sel; 53 52 enum dpu_cdm cdm; 54 53 int stream_sel; 54 + unsigned int cwb; 55 55 unsigned int dsc; 56 56 }; 57 57 ··· 115 113 */ 116 114 void (*update_pending_flush_wb)(struct dpu_hw_ctl *ctx, 117 115 enum dpu_wb blk); 116 + 117 + /** 118 + * OR in the given flushbits to the cached pending_(cwb_)flush_mask 119 + * No effect on hardware 120 + * @ctx : ctl path ctx pointer 121 + * @blk : concurrent writeback block index 122 + */ 123 + void (*update_pending_flush_cwb)(struct dpu_hw_ctl *ctx, 124 + enum dpu_cwb blk); 118 125 119 126 /** 120 127 * OR in the given flushbits to the cached pending_(intf_)flush_mask ··· 269 258 * @pending_flush_mask: storage for pending ctl_flush managed via ops 270 259 * @pending_intf_flush_mask: pending INTF flush 271 260 * @pending_wb_flush_mask: pending WB flush 261 + * @pending_cwb_flush_mask: pending CWB flush 272 262 * @pending_dsc_flush_mask: pending DSC flush 273 263 * @pending_cdm_flush_mask: pending CDM flush 274 264 * @ops: operation list ··· 286 274 u32 pending_flush_mask; 287 275 u32 pending_intf_flush_mask; 288 276 u32 pending_wb_flush_mask; 277 + u32 pending_cwb_flush_mask; 289 278 u32 pending_periph_flush_mask; 290 279 u32 pending_merge_3d_flush_mask; 291 280 u32 pending_dspp_flush_mask[DSPP_MAX - DSPP_0];

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