drm/msm/dpu: Configure CWB in writeback encoder

+74 -1

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

··· 24 24 #include "dpu_hw_catalog.h" 25 25 #include "dpu_hw_intf.h" 26 26 #include "dpu_hw_ctl.h" 27 + #include "dpu_hw_cwb.h" 27 28 #include "dpu_hw_dspp.h" 28 29 #include "dpu_hw_dsc.h" 29 30 #include "dpu_hw_merge3d.h" ··· 140 139 * num_phys_encs. 141 140 * @hw_dsc: Handle to the DSC blocks used for the display. 142 141 * @dsc_mask: Bitmask of used DSC blocks. 142 + * @cwb_mask Bitmask of used CWB muxes 143 143 * @intfs_swapped: Whether or not the phys_enc interfaces have been swapped 144 144 * for partial update right-only cases, such as pingpong 145 145 * split where virtual pingpong does not generate IRQs ··· 187 185 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; 188 186 189 187 unsigned int dsc_mask; 188 + unsigned int cwb_mask; 190 189 191 190 bool intfs_swapped; 192 191 ··· 1162 1159 int num_cwb = 0; 1163 1160 bool is_cwb_encoder; 1164 1161 unsigned int dsc_mask = 0; 1162 + unsigned int cwb_mask = 0; 1165 1163 int i; 1166 1164 1167 1165 if (!drm_enc) { ··· 1203 1199 ARRAY_SIZE(hw_pp)); 1204 1200 } 1205 1201 1206 - for (i = 0; i < num_cwb; i++) 1202 + for (i = 0; i < num_cwb; i++) { 1207 1203 dpu_enc->hw_cwb[i] = to_dpu_hw_cwb(hw_cwb[i]); 1204 + cwb_mask |= BIT(dpu_enc->hw_cwb[i]->idx - CWB_0); 1205 + } 1206 + 1207 + dpu_enc->cwb_mask = cwb_mask; 1208 1208 1209 1209 num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1210 1210 drm_enc->crtc, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); ··· 2245 2237 if (phys_enc->hw_pp && phys_enc->hw_pp->ops.setup_dither) 2246 2238 phys_enc->hw_pp->ops.setup_dither(phys_enc->hw_pp, NULL); 2247 2239 2240 + if (dpu_enc->cwb_mask) 2241 + dpu_encoder_helper_phys_setup_cwb(phys_enc, false); 2242 + 2248 2243 /* reset the merge 3D HW block */ 2249 2244 if (phys_enc->hw_pp && phys_enc->hw_pp->merge_3d) { 2250 2245 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, ··· 2289 2278 ctl->ops.trigger_flush(ctl); 2290 2279 ctl->ops.trigger_start(ctl); 2291 2280 ctl->ops.clear_pending_flush(ctl); 2281 + } 2282 + 2283 + void dpu_encoder_helper_phys_setup_cwb(struct dpu_encoder_phys *phys_enc, 2284 + bool enable) 2285 + { 2286 + struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 2287 + struct dpu_hw_cwb *hw_cwb; 2288 + struct dpu_hw_cwb_setup_cfg cwb_cfg; 2289 + 2290 + struct dpu_kms *dpu_kms; 2291 + struct dpu_global_state *global_state; 2292 + struct dpu_hw_blk *rt_pp_list[MAX_CHANNELS_PER_ENC]; 2293 + int num_pp; 2294 + 2295 + if (!phys_enc->hw_wb) 2296 + return; 2297 + 2298 + dpu_kms = phys_enc->dpu_kms; 2299 + global_state = dpu_kms_get_existing_global_state(dpu_kms); 2300 + num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 2301 + phys_enc->parent->crtc, 2302 + DPU_HW_BLK_PINGPONG, rt_pp_list, 2303 + ARRAY_SIZE(rt_pp_list)); 2304 + 2305 + if (num_pp == 0 || num_pp > MAX_CHANNELS_PER_ENC) { 2306 + DPU_DEBUG_ENC(dpu_enc, "invalid num_pp %d\n", num_pp); 2307 + return; 2308 + } 2309 + 2310 + /* 2311 + * The CWB mux supports using LM or DSPP as tap points. For now, 2312 + * always use LM tap point 2313 + */ 2314 + cwb_cfg.input = INPUT_MODE_LM_OUT; 2315 + 2316 + for (int i = 0; i < MAX_CHANNELS_PER_ENC; i++) { 2317 + hw_cwb = dpu_enc->hw_cwb[i]; 2318 + if (!hw_cwb) 2319 + continue; 2320 + 2321 + if (enable) { 2322 + struct dpu_hw_pingpong *hw_pp = 2323 + to_dpu_hw_pingpong(rt_pp_list[i]); 2324 + cwb_cfg.pp_idx = hw_pp->idx; 2325 + } else { 2326 + cwb_cfg.pp_idx = PINGPONG_NONE; 2327 + } 2328 + 2329 + hw_cwb->ops.config_cwb(hw_cwb, &cwb_cfg); 2330 + } 2292 2331 } 2293 2332 2294 2333 /** ··· 2799 2738 return dpu_enc->phys_encs[0]->intf_mode; 2800 2739 2801 2740 return INTF_MODE_NONE; 2741 + } 2742 + 2743 + /** 2744 + * dpu_encoder_helper_get_cwb_mask - get CWB blocks mask for the DPU encoder 2745 + * @phys_enc: Pointer to physical encoder structure 2746 + */ 2747 + unsigned int dpu_encoder_helper_get_cwb_mask(struct dpu_encoder_phys *phys_enc) 2748 + { 2749 + struct drm_encoder *encoder = phys_enc->parent; 2750 + struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder); 2751 + 2752 + return dpu_enc->cwb_mask; 2802 2753 } 2803 2754 2804 2755 /**

+6 -1

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h

··· 1 1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 2 /* 3 - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 3 + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 4 * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved. 5 5 */ 6 6 ··· 309 309 return BLEND_3D_NONE; 310 310 } 311 311 312 + unsigned int dpu_encoder_helper_get_cwb_mask(struct dpu_encoder_phys *phys_enc); 313 + 312 314 unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc); 313 315 314 316 struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc); ··· 332 330 struct dpu_encoder_wait_info *wait_info); 333 331 334 332 void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc); 333 + 334 + void dpu_encoder_helper_phys_setup_cwb(struct dpu_encoder_phys *phys_enc, 335 + bool enable); 335 336 336 337 void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc, 337 338 const struct msm_format *dpu_fmt,

+3 -1

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c

··· 1 1 // SPDX-License-Identifier: GPL-2.0-only 2 2 /* 3 - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 3 + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 4 */ 5 5 6 6 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ ··· 339 339 dpu_encoder_phys_wb_setup_fb(phys_enc, format); 340 340 341 341 dpu_encoder_helper_phys_setup_cdm(phys_enc, format, CDM_CDWN_OUTPUT_WB); 342 + 343 + dpu_encoder_helper_phys_setup_cwb(phys_enc, true); 342 344 343 345 dpu_encoder_phys_wb_setup_ctl(phys_enc); 344 346 }

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