Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: renesas: r9a09g057: Add clock and reset entries for ISP
Add entries detailing the clocks and resets for the ISP in the
RZ/V2H(P) SoC.
Signed-off-by: Daniel Scally <dan.scally@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251010-rzv2h_isp_clk-v2-1-2c8853a9af7c@ideasonboard.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
authored by
Daniel Scally
and committed by
Geert Uytterhoeven
0f537c41
e43b186d
+16
+14
drivers/clk/renesas/r9a09g057-cpg.c
+14
drivers/clk/renesas/r9a09g057-cpg.c
···
55
55
CLK_PLLVDO_CRU1,
56
56
CLK_PLLVDO_CRU2,
57
57
CLK_PLLVDO_CRU3,
58
+
CLK_PLLVDO_ISP,
58
59
CLK_PLLETH_DIV_250_FIX,
59
60
CLK_PLLETH_DIV_125_FIX,
60
61
CLK_CSDIV_PLLETH_GBE0,
···
158
157
DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4),
159
158
DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4),
160
159
DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4),
160
+
DEF_DDIV(".pllvdo_isp", CLK_PLLVDO_ISP, CLK_PLLVDO, CDDIV2_DIVCTL3, dtable_2_64),
161
161
162
162
DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
163
163
DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
···
373
371
BUS_MSTOP(9, BIT(7))),
374
372
DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29,
375
373
BUS_MSTOP(9, BIT(7))),
374
+
DEF_MOD("isp_0_reg_aclk", CLK_PLLDTY_ACPU_DIV2, 14, 2, 7, 2,
375
+
BUS_MSTOP(9, BIT(8))),
376
+
DEF_MOD("isp_0_pclk", CLK_PLLDTY_DIV16, 14, 3, 7, 3,
377
+
BUS_MSTOP(9, BIT(8))),
378
+
DEF_MOD("isp_0_vin_aclk", CLK_PLLDTY_ACPU_DIV2, 14, 4, 7, 4,
379
+
BUS_MSTOP(9, BIT(9))),
380
+
DEF_MOD("isp_0_isp_sclk", CLK_PLLVDO_ISP, 14, 5, 7, 5,
381
+
BUS_MSTOP(9, BIT(9))),
376
382
DEF_MOD("gpu_0_clk", CLK_PLLGPU_GEAR, 15, 0, 7, 16,
377
383
BUS_MSTOP(3, BIT(4))),
378
384
DEF_MOD("gpu_0_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
···
452
442
DEF_RST(12, 14, 5, 31), /* CRU_3_PRESETN */
453
443
DEF_RST(12, 15, 6, 0), /* CRU_3_ARESETN */
454
444
DEF_RST(13, 0, 6, 1), /* CRU_3_S_RESETN */
445
+
DEF_RST(13, 1, 6, 2), /* ISP_0_VIN_ARESETN */
446
+
DEF_RST(13, 2, 6, 3), /* ISP_0_REG_ARESETN */
447
+
DEF_RST(13, 3, 6, 4), /* ISP_0_ISP_SRESETN */
448
+
DEF_RST(13, 4, 6, 5), /* ISP_0_PRESETN */
455
449
DEF_RST(13, 13, 6, 14), /* GPU_0_RESETN */
456
450
DEF_RST(13, 14, 6, 15), /* GPU_0_AXI_RESETN */
457
451
DEF_RST(13, 15, 6, 16), /* GPU_0_ACE_RESETN */
+2
drivers/clk/renesas/rzv2h-cpg.h
+2
drivers/clk/renesas/rzv2h-cpg.h
···
115
115
#define CPG_SSEL1 (0x304)
116
116
#define CPG_CDDIV0 (0x400)
117
117
#define CPG_CDDIV1 (0x404)
118
+
#define CPG_CDDIV2 (0x408)
118
119
#define CPG_CDDIV3 (0x40C)
119
120
#define CPG_CDDIV4 (0x410)
120
121
#define CPG_CSDIV0 (0x500)
···
126
125
#define CDDIV1_DIVCTL1 DDIV_PACK(CPG_CDDIV1, 4, 2, 5)
127
126
#define CDDIV1_DIVCTL2 DDIV_PACK(CPG_CDDIV1, 8, 2, 6)
128
127
#define CDDIV1_DIVCTL3 DDIV_PACK(CPG_CDDIV1, 12, 2, 7)
128
+
#define CDDIV2_DIVCTL3 DDIV_PACK(CPG_CDDIV2, 12, 3, 11)
129
129
#define CDDIV3_DIVCTL1 DDIV_PACK(CPG_CDDIV3, 4, 3, 13)
130
130
#define CDDIV3_DIVCTL2 DDIV_PACK(CPG_CDDIV3, 8, 3, 14)
131
131
#define CDDIV3_DIVCTL3 DDIV_PACK(CPG_CDDIV3, 12, 1, 15)