Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'qcom-arm64-for-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm ARM64 updates for v6.4
PCI I/O and MEM ranges are corrected across all targets with PCIe
enabled. Likewise is CPU clocks defined to be provided from CPUfreq for
a wide range of platforms, to satisfy the OPP definitions, and LLCC bank
information is corrected for all relevant platforms.
IPQ5332 gains SMEM, CPUfreq and support for triggering download mode.
The MI01.2 board is introduced.
On MSM8916 WCN compatibles are moved to be defined per board, to avoid
issues when boards rely on the incorrect defaults. Support for Yiming
UZ801 4G modem stick is introduced.
XO clock is defined and fed to RPMCC on MSM8953 and MSM8976, to ensure
clock trees are properly rooted. DSI clocks feeding into gcc are
described on MSM8953.
On MSM8996 the external audio components are moved from the SoC dtsi. A
few DWC3 quirks are added.
On MSM8998 GPIO names are introduced for Sony Xperia XZ Premium, XZ1 and
XZ1 Compact. A numbe of boards have GPIO keys properly marked as
wakeup-source.
The SA8775P platform is extended with CPUfreq, UARTs, I2C controllers,
SPI controllers, SPMI and PMICs, PDC support. The associated PMICs gains
reset and power key support, as well as thermal zones defined. Nodes are
sorted. On top of this the SA8775P Ride board/platform is introduced.
On SC7180 and SC7280 a range of fixes coming from DeviceTree validation are
introduced, some clearing up unused properties, others correcting
errors. A number of Google rev0 boards on SC7180 are dropped, as these
are not considered to be in use by anyone anymore.
On SC8280XP RTC support is introduced and enabled for the CRD and Lenovo
Thinkpad X13s. It gains another UART, upon which Bluetooth is enabled on
the Lenovo ThinkPad X13s. The touchpad definition is altered to attempt
to probe both devices seen in the wild. A number of bug fixes are also
introduced, and the regulator definitions on X13s are corrected.
On SDM845 dynamic power coefficients are improved. BWMON compatible is
corrected. Xiaomi Pocophone F1 gains notification LED. Sony Xperia XZ2,
XZ2 Compact and XZ3 gains display, touchscreen, gpu and remoteproc
support. OnePlus 6 and 6T gains hall sensor.
GPU clock controller and remoteproc nodes are added for SM6115. CPU
clock are defined to come from CPUfreq. Board-specific USB-properties
are moved out of the SoC dtsi.
On SM6375 L3 scaling, IMEM, RMTFS, RPM sleep stats, Tsens, modem
remoteproc and WiFi nodes are added. Tsens thermal zones are defined and additional low power states
are defined. Sony Xperia 10 IV gains volume down key support.
On SM8150 another UART is introduced, to be used by GNSS on the SA8155
ADP. Support for the Flash LED block in PM8150L is added.
On SM8250 TPDM MM and PRNG is defined, MHI region is added to PCIe node.
A few bug fixes are introduced after Devicetree validation.
The DisplayPort controller on both SM8350 and SM8450 is defined and the
related QMP instance is transitioned to the USB3/DP combo variant. IMEM
and PIL info is introduced, for post mortem debugging of remoteprocs. On
the HDK PMIC GLINK is enabled and role switch is enabled. Some audio
resources are corrected.
A typo in the USB role property of the Microsoft Surface is corrected,
thanks to DeviceTree validation.
PCIe controllers and PHYs descriptions are corrected, and pinctrl state
definitions are moved from the soc to the board definition. BWMON
compatibles are corrected. PM8550B gains the definition of the eUSB2
repeater and this is enabled on the MTP. PMIC GLINK is also defined for
the MTP and connected to DWC3, for role switching support.
In addition to this, a range of cleanups based on Devicetree validation
is introduced.
A few clock bindings are introduced, from topic-branches shared with the
clock tree, to aid introduction of references to these.
* tag 'qcom-arm64-for-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (256 commits)
arm64: dts: qcom: sc8280xp-x13s: Add bluetooth
arm64: dts: qcom: sc8280xp: Define uart2
arm64: dts: qcom: sc8280xp: Add "mhi" region to the PCIe nodes
arm64: dts: qcom: sm8250: Add "mhi" region to the PCIe nodes
arm64: dts: qcom: sdm845: Add "mhi" region to the PCIe nodes
arm64: dts: qcom: sa8775p-ride: set gpio-line-names for PMIC GPIOs
arm64: dts: qcom: sa8775p: add PMIC GPIO controller nodes
arm64: dts: qcom: sa8775p: pmic: add thermal zones
arm64: dts: qcom: sa8775p: pmic: add support for the pmm8654 RESIN input
arm64: dts: qcom: sa8775p: pmic: add the power key
arm64: dts: qcom: sa8775p: add the Power On device node
arm64: dts: qcom: sa8775p: add support for the on-board PMICs
arm64: dts: qcom: sa8775p: add the spmi node
arm64: dts: qcom: sa8775p: add the pdc node
arm64: dts: qcom: sa8775p: sort soc nodes by reg property
arm64: dts: qcom: sa8775p: pad reg properties to 8 digits
arm64: dts: qcom: sc8280xp: correct Soundwire wakeup interrupt name
arm64: dts: qcom: sdm845-tama: Enable GPI_DMA0/1
arm64: dts: qcom: sdm845-tama: Enable GPU
arm64: dts: qcom: sdm845-tama: Enable remoteprocs
...
Link: https://lore.kernel.org/r/20230410170233.5931-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+6598
-1432
+53
Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
+53
Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Global Clock & Reset Controller on IPQ5332
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
12
+
description: |
13
+
Qualcomm global clock control module provides the clocks, resets and power
14
+
domains on IPQ5332.
15
+
16
+
See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h
17
+
18
+
allOf:
19
+
- $ref: qcom,gcc.yaml#
20
+
21
+
properties:
22
+
compatible:
23
+
const: qcom,ipq5332-gcc
24
+
25
+
clocks:
26
+
items:
27
+
- description: Board XO clock source
28
+
- description: Sleep clock source
29
+
- description: PCIE 2lane PHY pipe clock source
30
+
- description: PCIE 2lane x1 PHY pipe clock source (For second lane)
31
+
- description: USB PCIE wrapper pipe clock source
32
+
33
+
required:
34
+
- compatible
35
+
- clocks
36
+
37
+
unevaluatedProperties: false
38
+
39
+
examples:
40
+
- |
41
+
clock-controller@1800000 {
42
+
compatible = "qcom,ipq5332-gcc";
43
+
reg = <0x01800000 0x80000>;
44
+
clocks = <&xo_board>,
45
+
<&sleep_clk>,
46
+
<&pcie_2lane_phy_pipe_clk>,
47
+
<&pcie_2lane_phy_pipe_clk_x1>,
48
+
<&usb_pcie_wrapper_pipe_clk>;
49
+
#clock-cells = <1>;
50
+
#power-domain-cells = <1>;
51
+
#reset-cells = <1>;
52
+
};
53
+
...
+58
Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml
+58
Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/qcom,sm6115-gpucc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Graphics Clock & Reset Controller on SM6115
8
+
9
+
maintainers:
10
+
- Konrad Dybcio <konrad.dybcio@linaro.org>
11
+
12
+
description: |
13
+
Qualcomm graphics clock control module provides clocks, resets and power
14
+
domains on Qualcomm SoCs.
15
+
16
+
See also:: include/dt-bindings/clock/qcom,sm6115-gpucc.h
17
+
18
+
properties:
19
+
compatible:
20
+
enum:
21
+
- qcom,sm6115-gpucc
22
+
23
+
clocks:
24
+
items:
25
+
- description: Board XO source
26
+
- description: GPLL0 main branch source
27
+
- description: GPLL0 main div source
28
+
29
+
required:
30
+
- compatible
31
+
- clocks
32
+
33
+
allOf:
34
+
- $ref: qcom,gcc.yaml#
35
+
36
+
unevaluatedProperties: false
37
+
38
+
examples:
39
+
- |
40
+
#include <dt-bindings/clock/qcom,gcc-sm6115.h>
41
+
#include <dt-bindings/clock/qcom,rpmcc.h>
42
+
43
+
soc {
44
+
#address-cells = <1>;
45
+
#size-cells = <1>;
46
+
47
+
clock-controller@5990000 {
48
+
compatible = "qcom,sm6115-gpucc";
49
+
reg = <0x05990000 0x9000>;
50
+
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
51
+
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
52
+
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
53
+
#clock-cells = <1>;
54
+
#reset-cells = <1>;
55
+
#power-domain-cells = <1>;
56
+
};
57
+
};
58
+
...
+64
Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml
+64
Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/qcom,sm6125-gpucc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Graphics Clock & Reset Controller on SM6125
8
+
9
+
maintainers:
10
+
- Konrad Dybcio <konrad.dybcio@linaro.org>
11
+
12
+
description: |
13
+
Qualcomm graphics clock control module provides clocks and power domains on
14
+
Qualcomm SoCs.
15
+
16
+
See also:: include/dt-bindings/clock/qcom,sm6125-gpucc.h
17
+
18
+
properties:
19
+
compatible:
20
+
enum:
21
+
- qcom,sm6125-gpucc
22
+
23
+
clocks:
24
+
items:
25
+
- description: Board XO source
26
+
- description: GPLL0 main branch source
27
+
28
+
'#clock-cells':
29
+
const: 1
30
+
31
+
'#power-domain-cells':
32
+
const: 1
33
+
34
+
reg:
35
+
maxItems: 1
36
+
37
+
required:
38
+
- compatible
39
+
- reg
40
+
- clocks
41
+
- '#clock-cells'
42
+
- '#power-domain-cells'
43
+
44
+
additionalProperties: false
45
+
46
+
examples:
47
+
- |
48
+
#include <dt-bindings/clock/qcom,gcc-sm6125.h>
49
+
#include <dt-bindings/clock/qcom,rpmcc.h>
50
+
51
+
soc {
52
+
#address-cells = <1>;
53
+
#size-cells = <1>;
54
+
55
+
clock-controller@5990000 {
56
+
compatible = "qcom,sm6125-gpucc";
57
+
reg = <0x05990000 0x9000>;
58
+
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
59
+
<&gcc GCC_GPU_GPLL0_CLK_SRC>;
60
+
#clock-cells = <1>;
61
+
#power-domain-cells = <1>;
62
+
};
63
+
};
64
+
...
+60
Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml
+60
Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/qcom,sm6375-gpucc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Graphics Clock & Reset Controller on SM6375
8
+
9
+
maintainers:
10
+
- Konrad Dybcio <konrad.dybcio@linaro.org>
11
+
12
+
description: |
13
+
Qualcomm graphics clock control module provides clocks, resets and power
14
+
domains on Qualcomm SoCs.
15
+
16
+
See also:: include/dt-bindings/clock/qcom,sm6375-gpucc.h
17
+
18
+
properties:
19
+
compatible:
20
+
enum:
21
+
- qcom,sm6375-gpucc
22
+
23
+
clocks:
24
+
items:
25
+
- description: Board XO source
26
+
- description: GPLL0 main branch source
27
+
- description: GPLL0 div branch source
28
+
- description: SNoC DVM GFX source
29
+
30
+
required:
31
+
- compatible
32
+
- clocks
33
+
34
+
allOf:
35
+
- $ref: qcom,gcc.yaml#
36
+
37
+
unevaluatedProperties: false
38
+
39
+
examples:
40
+
- |
41
+
#include <dt-bindings/clock/qcom,sm6375-gcc.h>
42
+
#include <dt-bindings/clock/qcom,rpmcc.h>
43
+
44
+
soc {
45
+
#address-cells = <2>;
46
+
#size-cells = <2>;
47
+
48
+
clock-controller@5990000 {
49
+
compatible = "qcom,sm6375-gpucc";
50
+
reg = <0 0x05990000 0 0x9000>;
51
+
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
52
+
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
53
+
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>,
54
+
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
55
+
#clock-cells = <1>;
56
+
#reset-cells = <1>;
57
+
#power-domain-cells = <1>;
58
+
};
59
+
};
60
+
...
+5
-9
arch/arm64/boot/dts/qcom/Makefile
+5
-9
arch/arm64/boot/dts/qcom/Makefile
···
3
3
dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb
4
4
dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
5
5
dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
6
+
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-mi01.2.dtb
6
7
dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
7
8
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
8
9
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb
···
29
28
dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-uf896.dtb
30
29
dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-ufi001c.dtb
31
30
dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb
31
+
dtb-$(CONFIG_ARCH_QCOM) += msm8916-yiming-uz801v3.dtb
32
32
dtb-$(CONFIG_ARCH_QCOM) += msm8953-motorola-potter.dtb
33
33
dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-daisy.dtb
34
34
dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-mido.dtb
···
77
75
dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb
78
76
dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb
79
77
dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb
78
+
dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb
80
79
dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb
81
80
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb
82
81
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb
···
86
83
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r2.dtb
87
84
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r3.dtb
88
85
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r4.dtb
89
-
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-kingoftown-r0.dtb
90
-
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-kingoftown-r1.dtb
91
-
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r0.dtb
86
+
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-kingoftown.dtb
92
87
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb
93
88
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-kb.dtb
94
89
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-lte.dtb
···
101
100
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r4.dtb
102
101
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r5.dtb
103
102
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r9.dtb
104
-
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev0-auo.dtb
105
-
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev0-boe.dtb
106
-
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev1-auo.dtb
107
-
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev1-boe.dtb
108
103
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-lte-parade.dtb
109
104
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-lte-ti.dtb
110
105
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-parade.dtb
···
115
118
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3-lte.dtb
116
119
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-quackingstick-r0.dtb
117
120
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-quackingstick-r0-lte.dtb
118
-
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev0-boe.dtb
119
-
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev0-inx.dtb
120
121
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-boe.dtb
121
122
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-inx.dtb
122
123
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-inx-rt5682s.dtb
···
195
200
dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx223.dtb
196
201
dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb
197
202
dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb
203
+
dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb
+9
-6
arch/arm64/boot/dts/qcom/apq8016-sbc.dts
+9
-6
arch/arm64/boot/dts/qcom/apq8016-sbc.dts
···
325
325
linux,code = <KEY_VOLUMEDOWN>;
326
326
};
327
327
328
-
&pronto {
329
-
status = "okay";
330
-
331
-
firmware-name = "qcom/apq8016/wcnss.mbn";
332
-
};
333
-
334
328
&sdhc_1 {
335
329
status = "okay";
336
330
···
405
411
qcom,mbhc-vthreshold-high = <75 150 237 450 500>;
406
412
};
407
413
414
+
&wcnss {
415
+
status = "okay";
416
+
firmware-name = "qcom/apq8016/wcnss.mbn";
417
+
};
418
+
408
419
&wcnss_ctrl {
409
420
firmware-name = "qcom/apq8016/WCNSS_qcom_wlan_nv_sbc.bin";
421
+
};
422
+
423
+
&wcnss_iris {
424
+
compatible = "qcom,wcn3620";
410
425
};
411
426
412
427
/* Enable CoreSight */
+46
-19
arch/arm64/boot/dts/qcom/apq8096-db820c.dts
+46
-19
arch/arm64/boot/dts/qcom/apq8096-db820c.dts
···
63
63
};
64
64
65
65
clocks {
66
-
compatible = "simple-bus";
67
66
divclk4: divclk4 {
68
67
compatible = "fixed-clock";
69
68
#clock-cells = <0>;
···
145
146
146
147
&blsp1_spi1 {
147
148
/* On Low speed expansion */
148
-
label = "LS-SPI0";
149
149
status = "okay";
150
150
};
151
151
···
181
183
182
184
&blsp2_spi6 {
183
185
/* On High speed expansion */
184
-
label = "HS-SPI1";
185
186
status = "okay";
186
187
};
187
188
···
703
706
&pmi8994_spmi_regulators {
704
707
vdd_s2-supply = <&vph_pwr>;
705
708
706
-
vdd_gfx: s2@1700 {
707
-
reg = <0x1700 0x100>;
709
+
vdd_gfx: s2 {
708
710
regulator-name = "VDD_GFX";
709
711
regulator-min-microvolt = <980000>;
710
712
regulator-max-microvolt = <980000>;
···
970
974
};
971
975
};
972
976
977
+
&slim_msm {
978
+
status = "okay";
979
+
980
+
slim@1 {
981
+
reg = <1>;
982
+
#address-cells = <2>;
983
+
#size-cells = <0>;
984
+
985
+
tasha_ifd: tas-ifd@0,0 {
986
+
compatible = "slim217,1a0";
987
+
reg = <0 0>;
988
+
};
989
+
990
+
wcd9335: codec@1,0 {
991
+
compatible = "slim217,1a0";
992
+
reg = <1 0>;
993
+
994
+
clock-names = "mclk", "slimbus";
995
+
clocks = <&div1_mclk>,
996
+
<&rpmcc RPM_SMD_BB_CLK1>;
997
+
interrupt-parent = <&tlmm>;
998
+
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
999
+
<53 IRQ_TYPE_LEVEL_HIGH>;
1000
+
interrupt-names = "intr1", "intr2";
1001
+
interrupt-controller;
1002
+
#interrupt-cells = <1>;
1003
+
1004
+
pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
1005
+
pinctrl-names = "default";
1006
+
1007
+
reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
1008
+
slim-ifc-dev = <&tasha_ifd>;
1009
+
1010
+
#sound-dai-cells = <1>;
1011
+
1012
+
vdd-buck-supply = <&vreg_s4a_1p8>;
1013
+
vdd-buck-sido-supply = <&vreg_s4a_1p8>;
1014
+
vdd-tx-supply = <&vreg_s4a_1p8>;
1015
+
vdd-rx-supply = <&vreg_s4a_1p8>;
1016
+
vdd-io-supply = <&vreg_s4a_1p8>;
1017
+
};
1018
+
};
1019
+
};
1020
+
973
1021
&sound {
974
1022
compatible = "qcom,apq8096-sndcard";
975
1023
model = "DB820c";
···
1066
1026
1067
1027
platform {
1068
1028
sound-dai = <&q6routing>;
1069
-
};
1029
+
};
1070
1030
1071
1031
codec {
1072
1032
sound-dai = <&wcd9335 AIF4_PB>;
···
1135
1095
1136
1096
vdda-phy-supply = <&vreg_l28a_0p925>;
1137
1097
vdda-pll-supply = <&vreg_l12a_1p8>;
1138
-
1139
1098
};
1140
1099
1141
1100
&venus {
1142
1101
status = "okay";
1143
-
};
1144
-
1145
-
&wcd9335 {
1146
-
clock-names = "mclk", "slimbus";
1147
-
clocks = <&div1_mclk>,
1148
-
<&rpmcc RPM_SMD_BB_CLK1>;
1149
-
1150
-
vdd-buck-supply = <&vreg_s4a_1p8>;
1151
-
vdd-buck-sido-supply = <&vreg_s4a_1p8>;
1152
-
vdd-tx-supply = <&vreg_s4a_1p8>;
1153
-
vdd-rx-supply = <&vreg_s4a_1p8>;
1154
-
vdd-io-supply = <&vreg_s4a_1p8>;
1155
1102
};
+75
arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts
+75
arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts
···
1
+
// SPDX-License-Identifier: BSD-3-Clause
2
+
/*
3
+
* IPQ5332 AP-MI01.2 board device tree source
4
+
*
5
+
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
6
+
*/
7
+
8
+
/dts-v1/;
9
+
10
+
#include "ipq5332.dtsi"
11
+
12
+
/ {
13
+
model = "Qualcomm Technologies, Inc. IPQ5332 MI01.2";
14
+
compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332";
15
+
16
+
aliases {
17
+
serial0 = &blsp1_uart0;
18
+
};
19
+
20
+
chosen {
21
+
stdout-path = "serial0";
22
+
};
23
+
};
24
+
25
+
&blsp1_uart0 {
26
+
pinctrl-0 = <&serial_0_pins>;
27
+
pinctrl-names = "default";
28
+
status = "okay";
29
+
};
30
+
31
+
&sdhc {
32
+
bus-width = <4>;
33
+
max-frequency = <192000000>;
34
+
mmc-ddr-1_8v;
35
+
mmc-hs200-1_8v;
36
+
non-removable;
37
+
pinctrl-0 = <&sdc_default_state>;
38
+
pinctrl-names = "default";
39
+
status = "okay";
40
+
};
41
+
42
+
&sleep_clk {
43
+
clock-frequency = <32000>;
44
+
};
45
+
46
+
&xo_board {
47
+
clock-frequency = <24000000>;
48
+
};
49
+
50
+
/* PINCTRL */
51
+
52
+
&tlmm {
53
+
sdc_default_state: sdc-default-state {
54
+
clk-pins {
55
+
pins = "gpio13";
56
+
function = "sdc_clk";
57
+
drive-strength = <8>;
58
+
bias-disable;
59
+
};
60
+
61
+
cmd-pins {
62
+
pins = "gpio12";
63
+
function = "sdc_cmd";
64
+
drive-strength = <8>;
65
+
bias-pull-up;
66
+
};
67
+
68
+
data-pins {
69
+
pins = "gpio8", "gpio9", "gpio10", "gpio11";
70
+
function = "sdc_data";
71
+
drive-strength = <8>;
72
+
bias-pull-up;
73
+
};
74
+
};
75
+
};
+320
arch/arm64/boot/dts/qcom/ipq5332.dtsi
+320
arch/arm64/boot/dts/qcom/ipq5332.dtsi
···
1
+
// SPDX-License-Identifier: BSD-3-Clause
2
+
/*
3
+
* IPQ5332 device tree source
4
+
*
5
+
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
6
+
*/
7
+
8
+
#include <dt-bindings/clock/qcom,apss-ipq.h>
9
+
#include <dt-bindings/clock/qcom,ipq5332-gcc.h>
10
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
11
+
12
+
/ {
13
+
interrupt-parent = <&intc>;
14
+
#address-cells = <2>;
15
+
#size-cells = <2>;
16
+
17
+
clocks {
18
+
sleep_clk: sleep-clk {
19
+
compatible = "fixed-clock";
20
+
#clock-cells = <0>;
21
+
};
22
+
23
+
xo_board: xo-board-clk {
24
+
compatible = "fixed-clock";
25
+
#clock-cells = <0>;
26
+
};
27
+
};
28
+
29
+
cpus {
30
+
#address-cells = <1>;
31
+
#size-cells = <0>;
32
+
33
+
CPU0: cpu@0 {
34
+
device_type = "cpu";
35
+
compatible = "arm,cortex-a53";
36
+
reg = <0x0>;
37
+
enable-method = "psci";
38
+
next-level-cache = <&L2_0>;
39
+
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
40
+
operating-points-v2 = <&cpu_opp_table>;
41
+
};
42
+
43
+
CPU1: cpu@1 {
44
+
device_type = "cpu";
45
+
compatible = "arm,cortex-a53";
46
+
reg = <0x1>;
47
+
enable-method = "psci";
48
+
next-level-cache = <&L2_0>;
49
+
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
50
+
operating-points-v2 = <&cpu_opp_table>;
51
+
};
52
+
53
+
CPU2: cpu@2 {
54
+
device_type = "cpu";
55
+
compatible = "arm,cortex-a53";
56
+
reg = <0x2>;
57
+
enable-method = "psci";
58
+
next-level-cache = <&L2_0>;
59
+
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
60
+
operating-points-v2 = <&cpu_opp_table>;
61
+
};
62
+
63
+
CPU3: cpu@3 {
64
+
device_type = "cpu";
65
+
compatible = "arm,cortex-a53";
66
+
reg = <0x3>;
67
+
enable-method = "psci";
68
+
next-level-cache = <&L2_0>;
69
+
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
70
+
operating-points-v2 = <&cpu_opp_table>;
71
+
};
72
+
73
+
L2_0: l2-cache {
74
+
compatible = "cache";
75
+
cache-level = <2>;
76
+
};
77
+
};
78
+
79
+
firmware {
80
+
scm {
81
+
compatible = "qcom,scm-ipq5332", "qcom,scm";
82
+
qcom,dload-mode = <&tcsr 0x6100>;
83
+
};
84
+
};
85
+
86
+
memory@40000000 {
87
+
device_type = "memory";
88
+
/* We expect the bootloader to fill in the size */
89
+
reg = <0x0 0x40000000 0x0 0x0>;
90
+
};
91
+
92
+
cpu_opp_table: opp-table-cpu {
93
+
compatible = "operating-points-v2";
94
+
opp-shared;
95
+
96
+
opp-1488000000 {
97
+
opp-hz = /bits/ 64 <1488000000>;
98
+
clock-latency-ns = <200000>;
99
+
};
100
+
};
101
+
102
+
pmu {
103
+
compatible = "arm,cortex-a53-pmu";
104
+
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
105
+
};
106
+
107
+
psci {
108
+
compatible = "arm,psci-1.0";
109
+
method = "smc";
110
+
};
111
+
112
+
reserved-memory {
113
+
#address-cells = <2>;
114
+
#size-cells = <2>;
115
+
ranges;
116
+
117
+
tz_mem: tz@4a600000 {
118
+
reg = <0x0 0x4a600000 0x0 0x200000>;
119
+
no-map;
120
+
};
121
+
122
+
smem@4a800000 {
123
+
compatible = "qcom,smem";
124
+
reg = <0x0 0x4a800000 0x0 0x00100000>;
125
+
no-map;
126
+
127
+
hwlocks = <&tcsr_mutex 0>;
128
+
};
129
+
};
130
+
131
+
soc@0 {
132
+
compatible = "simple-bus";
133
+
#address-cells = <1>;
134
+
#size-cells = <1>;
135
+
ranges = <0 0 0 0xffffffff>;
136
+
137
+
tlmm: pinctrl@1000000 {
138
+
compatible = "qcom,ipq5332-tlmm";
139
+
reg = <0x01000000 0x300000>;
140
+
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
141
+
gpio-controller;
142
+
#gpio-cells = <2>;
143
+
gpio-ranges = <&tlmm 0 0 53>;
144
+
interrupt-controller;
145
+
#interrupt-cells = <2>;
146
+
147
+
serial_0_pins: serial0-state {
148
+
pins = "gpio18", "gpio19";
149
+
function = "blsp0_uart0";
150
+
drive-strength = <8>;
151
+
bias-pull-up;
152
+
};
153
+
};
154
+
155
+
gcc: clock-controller@1800000 {
156
+
compatible = "qcom,ipq5332-gcc";
157
+
reg = <0x01800000 0x80000>;
158
+
#clock-cells = <1>;
159
+
#reset-cells = <1>;
160
+
#power-domain-cells = <1>;
161
+
clocks = <&xo_board>,
162
+
<&sleep_clk>,
163
+
<0>,
164
+
<0>,
165
+
<0>;
166
+
};
167
+
168
+
tcsr_mutex: hwlock@1905000 {
169
+
compatible = "qcom,tcsr-mutex";
170
+
reg = <0x01905000 0x20000>;
171
+
#hwlock-cells = <1>;
172
+
};
173
+
174
+
tcsr: syscon@1937000 {
175
+
compatible = "qcom,tcsr-ipq5332", "syscon";
176
+
reg = <0x01937000 0x21000>;
177
+
};
178
+
179
+
sdhc: mmc@7804000 {
180
+
compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5";
181
+
reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
182
+
183
+
interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
184
+
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
185
+
interrupt-names = "hc_irq", "pwr_irq";
186
+
187
+
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
188
+
<&gcc GCC_SDCC1_APPS_CLK>,
189
+
<&xo_board>;
190
+
clock-names = "iface", "core", "xo";
191
+
status = "disabled";
192
+
};
193
+
194
+
blsp1_uart0: serial@78af000 {
195
+
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
196
+
reg = <0x078af000 0x200>;
197
+
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
198
+
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
199
+
<&gcc GCC_BLSP1_AHB_CLK>;
200
+
clock-names = "core", "iface";
201
+
status = "disabled";
202
+
};
203
+
204
+
intc: interrupt-controller@b000000 {
205
+
compatible = "qcom,msm-qgic2";
206
+
reg = <0x0b000000 0x1000>, /* GICD */
207
+
<0x0b002000 0x1000>, /* GICC */
208
+
<0x0b001000 0x1000>, /* GICH */
209
+
<0x0b004000 0x1000>; /* GICV */
210
+
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
211
+
interrupt-controller;
212
+
#interrupt-cells = <3>;
213
+
#address-cells = <1>;
214
+
#size-cells = <1>;
215
+
ranges = <0 0x0b00c000 0x3000>;
216
+
217
+
v2m0: v2m@0 {
218
+
compatible = "arm,gic-v2m-frame";
219
+
reg = <0x00000000 0xffd>;
220
+
msi-controller;
221
+
};
222
+
223
+
v2m1: v2m@1000 {
224
+
compatible = "arm,gic-v2m-frame";
225
+
reg = <0x00001000 0xffd>;
226
+
msi-controller;
227
+
};
228
+
229
+
v2m2: v2m@2000 {
230
+
compatible = "arm,gic-v2m-frame";
231
+
reg = <0x00002000 0xffd>;
232
+
msi-controller;
233
+
};
234
+
};
235
+
236
+
apcs_glb: mailbox@b111000 {
237
+
compatible = "qcom,ipq5332-apcs-apps-global",
238
+
"qcom,ipq6018-apcs-apps-global";
239
+
reg = <0x0b111000 0x1000>;
240
+
#clock-cells = <1>;
241
+
clocks = <&a53pll>, <&xo_board>;
242
+
clock-names = "pll", "xo";
243
+
#mbox-cells = <1>;
244
+
};
245
+
246
+
a53pll: clock@b116000 {
247
+
compatible = "qcom,ipq5332-a53pll";
248
+
reg = <0x0b116000 0x40>;
249
+
#clock-cells = <0>;
250
+
clocks = <&xo_board>;
251
+
clock-names = "xo";
252
+
};
253
+
254
+
timer@b120000 {
255
+
compatible = "arm,armv7-timer-mem";
256
+
reg = <0x0b120000 0x1000>;
257
+
#address-cells = <1>;
258
+
#size-cells = <1>;
259
+
ranges;
260
+
261
+
frame@b120000 {
262
+
reg = <0x0b121000 0x1000>,
263
+
<0x0b122000 0x1000>;
264
+
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
265
+
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
266
+
frame-number = <0>;
267
+
};
268
+
269
+
frame@b123000 {
270
+
reg = <0x0b123000 0x1000>;
271
+
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
272
+
frame-number = <1>;
273
+
status = "disabled";
274
+
};
275
+
276
+
frame@b124000 {
277
+
reg = <0x0b124000 0x1000>;
278
+
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
279
+
frame-number = <2>;
280
+
status = "disabled";
281
+
};
282
+
283
+
frame@b125000 {
284
+
reg = <0x0b125000 0x1000>;
285
+
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
286
+
frame-number = <3>;
287
+
status = "disabled";
288
+
};
289
+
290
+
frame@b126000 {
291
+
reg = <0x0b126000 0x1000>;
292
+
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
293
+
frame-number = <4>;
294
+
status = "disabled";
295
+
};
296
+
297
+
frame@b127000 {
298
+
reg = <0x0b127000 0x1000>;
299
+
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
300
+
frame-number = <5>;
301
+
status = "disabled";
302
+
};
303
+
304
+
frame@b128000 {
305
+
reg = <0x0b128000 0x1000>;
306
+
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
307
+
frame-number = <6>;
308
+
status = "disabled";
309
+
};
310
+
};
311
+
};
312
+
313
+
timer {
314
+
compatible = "arm,armv8-timer";
315
+
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
316
+
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
317
+
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
318
+
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
319
+
};
320
+
};
-1
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
-1
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
+2
-2
arch/arm64/boot/dts/qcom/ipq6018.dtsi
+2
-2
arch/arm64/boot/dts/qcom/ipq6018.dtsi
···
738
738
phys = <&pcie_phy0>;
739
739
phy-names = "pciephy";
740
740
741
-
ranges = <0x81000000 0 0x20200000 0 0x20200000 0 0x10000>,
742
-
<0x82000000 0 0x20220000 0 0x20220000 0 0xfde0000>;
741
+
ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>,
742
+
<0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>;
743
743
744
744
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
745
745
interrupt-names = "msi";
+2
-2
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+2
-2
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+2
-2
arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
+2
-2
arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
+4
-9
arch/arm64/boot/dts/qcom/ipq8074.dtsi
+4
-9
arch/arm64/boot/dts/qcom/ipq8074.dtsi
···
397
397
#size-cells = <0>;
398
398
interrupt-controller;
399
399
#interrupt-cells = <4>;
400
-
cell-index = <0>;
401
400
};
402
401
403
402
sdhc_1: mmc@7824900 {
···
779
780
phys = <&pcie_phy1>;
780
781
phy-names = "pciephy";
781
782
782
-
ranges = <0x81000000 0 0x10200000 0x10200000
783
-
0 0x10000>, /* downstream I/O */
784
-
<0x82000000 0 0x10220000 0x10220000
785
-
0 0xfde0000>; /* non-prefetchable memory */
783
+
ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */
784
+
<0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
786
785
787
786
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
788
787
interrupt-names = "msi";
···
841
844
phys = <&pcie_phy0>;
842
845
phy-names = "pciephy";
843
846
844
-
ranges = <0x81000000 0 0x20200000 0x20200000
845
-
0 0x10000>, /* downstream I/O */
846
-
<0x82000000 0 0x20220000 0x20220000
847
-
0 0xfde0000>; /* non-prefetchable memory */
847
+
ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */
848
+
<0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
848
849
849
850
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
850
851
interrupt-names = "msi";
+8
-4
arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts
+8
-4
arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts
···
118
118
status = "okay";
119
119
};
120
120
121
-
&pronto {
122
-
status = "okay";
123
-
};
124
-
125
121
&sdhc_1 {
126
122
pinctrl-names = "default", "sleep";
127
123
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
···
143
147
144
148
&usb_hs_phy {
145
149
extcon = <&usb_id>;
150
+
};
151
+
152
+
&wcnss {
153
+
status = "okay";
154
+
};
155
+
156
+
&wcnss_iris {
157
+
compatible = "qcom,wcn3620";
146
158
};
147
159
148
160
&smd_rpm_regulators {
+8
-4
arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts
+8
-4
arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts
···
160
160
status = "okay";
161
161
};
162
162
163
-
&pronto {
164
-
status = "okay";
165
-
};
166
-
167
163
&sdhc_1 {
168
164
status = "okay";
169
165
···
185
189
186
190
&usb_hs_phy {
187
191
extcon = <&usb_id>;
192
+
};
193
+
194
+
&wcnss {
195
+
status = "okay";
196
+
};
197
+
198
+
&wcnss_iris {
199
+
compatible = "qcom,wcn3620";
188
200
};
189
201
190
202
&smd_rpm_regulators {
+8
-4
arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts
+8
-4
arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts
···
128
128
status = "okay";
129
129
};
130
130
131
-
&pronto {
132
-
status = "okay";
133
-
};
134
-
135
131
&sdhc_1 {
136
132
status = "okay";
137
133
···
153
157
154
158
&usb_hs_phy {
155
159
extcon = <&usb_id>;
160
+
};
161
+
162
+
&wcnss {
163
+
status = "okay";
164
+
};
165
+
166
+
&wcnss_iris {
167
+
compatible = "qcom,wcn3620";
156
168
};
157
169
158
170
&smd_rpm_regulators {
+8
-4
arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts
+8
-4
arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts
···
118
118
status = "okay";
119
119
};
120
120
121
-
&pronto {
122
-
status = "okay";
123
-
};
124
-
125
121
&sdhc_1 {
126
122
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
127
123
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
···
143
147
144
148
&usb_hs_phy {
145
149
extcon = <&usb_id>;
150
+
};
151
+
152
+
&wcnss {
153
+
status = "okay";
154
+
};
155
+
156
+
&wcnss_iris {
157
+
compatible = "qcom,wcn3620";
146
158
};
147
159
148
160
&smd_rpm_regulators {
+8
-4
arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts
+8
-4
arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts
···
227
227
status = "okay";
228
228
};
229
229
230
-
&pronto {
231
-
status = "okay";
232
-
};
233
-
234
230
&sdhc_1 {
235
231
status = "okay";
236
232
···
306
310
qcom,mbhc-vthreshold-low = <75 150 237 450 500>;
307
311
qcom,mbhc-vthreshold-high = <75 150 237 450 500>;
308
312
qcom,hphl-jack-type-normally-open;
313
+
};
314
+
315
+
&wcnss {
316
+
status = "okay";
317
+
};
318
+
319
+
&wcnss_iris {
320
+
compatible = "qcom,wcn3620";
309
321
};
310
322
311
323
&smd_rpm_regulators {
+8
-4
arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts
+8
-4
arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts
···
231
231
status = "okay";
232
232
};
233
233
234
-
&pronto {
235
-
status = "okay";
236
-
};
237
-
238
234
&sdhc_1 {
239
235
status = "okay";
240
236
···
257
261
258
262
&usb_hs_phy {
259
263
extcon = <&pm8916_usbin>;
264
+
};
265
+
266
+
&wcnss {
267
+
status = "okay";
268
+
};
269
+
270
+
&wcnss_iris {
271
+
compatible = "qcom,wcn3620";
260
272
};
261
273
262
274
&smd_rpm_regulators {
+8
-4
arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts
+8
-4
arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts
···
99
99
status = "okay";
100
100
};
101
101
102
-
&pronto {
103
-
status = "okay";
104
-
};
105
-
106
102
&sdhc_1 {
107
103
status = "okay";
108
104
···
124
128
125
129
&usb_hs_phy {
126
130
extcon = <&usb_id>;
131
+
};
132
+
133
+
&wcnss {
134
+
status = "okay";
135
+
};
136
+
137
+
&wcnss_iris {
138
+
compatible = "qcom,wcn3620";
127
139
};
128
140
129
141
&smd_rpm_regulators {
+11
-11
arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi
+11
-11
arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi
···
20
20
pll-supply = <&pm8916_l7>;
21
21
};
22
22
23
-
&pronto {
24
-
vddpx-supply = <&pm8916_l7>;
25
-
26
-
iris {
27
-
vddxo-supply = <&pm8916_l7>;
28
-
vddrfa-supply = <&pm8916_s3>;
29
-
vddpa-supply = <&pm8916_l9>;
30
-
vdddig-supply = <&pm8916_l5>;
31
-
};
32
-
};
33
-
34
23
&sdhc_1 {
35
24
vmmc-supply = <&pm8916_l8>;
36
25
vqmmc-supply = <&pm8916_l5>;
···
33
44
&usb_hs_phy {
34
45
v1p8-supply = <&pm8916_l7>;
35
46
v3p3-supply = <&pm8916_l13>;
47
+
};
48
+
49
+
&wcnss {
50
+
vddpx-supply = <&pm8916_l7>;
51
+
};
52
+
53
+
&wcnss_iris {
54
+
vddxo-supply = <&pm8916_l7>;
55
+
vddrfa-supply = <&pm8916_s3>;
56
+
vddpa-supply = <&pm8916_l9>;
57
+
vdddig-supply = <&pm8916_l5>;
36
58
};
37
59
38
60
&rpm_requests {
-4
arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
-4
arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
+8
arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts
+8
arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts
+8
-6
arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts
+8
-6
arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts
···
54
54
status = "okay";
55
55
};
56
56
57
-
&pronto {
58
-
iris {
59
-
compatible = "qcom,wcn3660b";
60
-
};
61
-
};
62
-
63
57
&touchkey {
64
58
vcc-supply = <®_touch_key>;
65
59
vdd-supply = <®_touch_key>;
···
61
67
62
68
&vibrator {
63
69
status = "okay";
70
+
};
71
+
72
+
&wcnss {
73
+
status = "okay";
74
+
};
75
+
76
+
&wcnss_iris {
77
+
compatible = "qcom,wcn3660b";
64
78
};
65
79
66
80
&msmgpio {
+8
arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi
+8
arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi
+8
-8
arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi
+8
-8
arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi
···
125
125
status = "okay";
126
126
};
127
127
128
-
&pronto {
129
-
status = "okay";
130
-
131
-
iris {
132
-
compatible = "qcom,wcn3660b";
133
-
};
134
-
};
135
-
136
128
&sdhc_1 {
137
129
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
138
130
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
···
152
160
153
161
&usb_hs_phy {
154
162
extcon = <&pm8916_usbin>;
163
+
};
164
+
165
+
&wcnss {
166
+
status = "okay";
167
+
};
168
+
169
+
&wcnss_iris {
170
+
compatible = "qcom,wcn3660b";
155
171
};
156
172
157
173
&smd_rpm_regulators {
+8
-4
arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi
+8
-4
arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi
···
93
93
linux,code = <KEY_VOLUMEDOWN>;
94
94
};
95
95
96
-
&pronto {
97
-
status = "okay";
98
-
};
99
-
100
96
&sdhc_1 {
101
97
status = "okay";
102
98
···
118
122
119
123
&usb_hs_phy {
120
124
extcon = <&muic>;
125
+
};
126
+
127
+
&wcnss {
128
+
status = "okay";
129
+
};
130
+
131
+
&wcnss_iris {
132
+
compatible = "qcom,wcn3620";
121
133
};
122
134
123
135
&smd_rpm_regulators {
+8
-8
arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts
+8
-8
arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts
···
272
272
status = "okay";
273
273
};
274
274
275
-
&pronto {
276
-
status = "okay";
277
-
278
-
iris {
279
-
compatible = "qcom,wcn3660b";
280
-
};
281
-
};
282
-
283
275
&sdhc_1 {
284
276
status = "okay";
285
277
···
310
318
311
319
&usb_hs_phy {
312
320
extcon = <&muic>;
321
+
};
322
+
323
+
&wcnss {
324
+
status = "okay";
325
+
};
326
+
327
+
&wcnss_iris {
328
+
compatible = "qcom,wcn3660b";
313
329
};
314
330
315
331
&smd_rpm_regulators {
-4
arch/arm64/boot/dts/qcom/msm8916-thwc-uf896.dts
-4
arch/arm64/boot/dts/qcom/msm8916-thwc-uf896.dts
+26
-2
arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts
+26
-2
arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts
···
25
25
gpios = <&msmgpio 20 GPIO_ACTIVE_HIGH>;
26
26
};
27
27
28
+
&mpss {
29
+
pinctrl-0 = <&sim_ctrl_default>;
30
+
pinctrl-names = "default";
31
+
};
32
+
28
33
&button_default {
29
34
pins = "gpio37";
30
35
bias-pull-down;
···
39
34
pins = "gpio20", "gpio21", "gpio22";
40
35
};
41
36
42
-
&sim_ctrl_default {
43
-
pins = "gpio1", "gpio2";
37
+
/* This selects the external SIM card slot by default */
38
+
&msmgpio {
39
+
sim_ctrl_default: sim-ctrl-default-state {
40
+
esim-sel-pins {
41
+
pins = "gpio0", "gpio3";
42
+
bias-disable;
43
+
output-low;
44
+
};
45
+
46
+
sim-en-pins {
47
+
pins = "gpio1";
48
+
bias-disable;
49
+
output-low;
50
+
};
51
+
52
+
sim-sel-pins {
53
+
pins = "gpio2";
54
+
bias-disable;
55
+
output-high;
56
+
};
57
+
};
44
58
};
+8
-14
arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi
+8
-14
arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi
···
92
92
};
93
93
94
94
&mpss {
95
-
pinctrl-0 = <&sim_ctrl_default>;
96
-
pinctrl-names = "default";
97
-
98
95
status = "okay";
99
96
};
100
97
101
98
&pm8916_usbin {
102
-
status = "okay";
103
-
};
104
-
105
-
&pronto {
106
99
status = "okay";
107
100
};
108
101
···
116
123
117
124
&usb_hs_phy {
118
125
extcon = <&pm8916_usbin>;
126
+
};
127
+
128
+
&wcnss {
129
+
status = "okay";
130
+
};
131
+
132
+
&wcnss_iris {
133
+
compatible = "qcom,wcn3620";
119
134
};
120
135
121
136
&smd_rpm_regulators {
···
240
239
function = "gpio";
241
240
drive-strength = <2>;
242
241
bias-disable;
243
-
};
244
-
245
-
sim_ctrl_default: sim-ctrl-default-state {
246
-
function = "gpio";
247
-
drive-strength = <2>;
248
-
bias-disable;
249
-
output-low;
250
242
};
251
243
};
+8
-4
arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts
+8
-4
arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts
···
153
153
status = "okay";
154
154
};
155
155
156
-
&pronto {
157
-
status = "okay";
158
-
};
159
-
160
156
&sdhc_1 {
161
157
status = "okay";
162
158
···
178
182
179
183
&usb_hs_phy {
180
184
extcon = <&usb_id>;
185
+
};
186
+
187
+
&wcnss {
188
+
status = "okay";
189
+
};
190
+
191
+
&wcnss_iris {
192
+
compatible = "qcom,wcn3620";
181
193
};
182
194
183
195
&smd_rpm_regulators {
+35
arch/arm64/boot/dts/qcom/msm8916-yiming-uz801v3.dts
+35
arch/arm64/boot/dts/qcom/msm8916-yiming-uz801v3.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
3
+
/dts-v1/;
4
+
5
+
#include "msm8916-ufi.dtsi"
6
+
7
+
/ {
8
+
model = "uz801 v3.0 4G Modem Stick";
9
+
compatible = "yiming,uz801-v3", "qcom,msm8916";
10
+
};
11
+
12
+
&button_restart {
13
+
gpios = <&msmgpio 23 GPIO_ACTIVE_LOW>;
14
+
};
15
+
16
+
&led_r {
17
+
gpios = <&msmgpio 7 GPIO_ACTIVE_HIGH>;
18
+
};
19
+
20
+
&led_g {
21
+
gpios = <&msmgpio 8 GPIO_ACTIVE_HIGH>;
22
+
};
23
+
24
+
&led_b {
25
+
gpios = <&msmgpio 6 GPIO_ACTIVE_HIGH>;
26
+
};
27
+
28
+
&button_default {
29
+
pins = "gpio23";
30
+
bias-pull-up;
31
+
};
32
+
33
+
&gpio_leds_default {
34
+
pins = "gpio6", "gpio7", "gpio8";
35
+
};
+7
-9
arch/arm64/boot/dts/qcom/msm8916.dtsi
+7
-9
arch/arm64/boot/dts/qcom/msm8916.dtsi
···
503
503
bits = <1 7>;
504
504
};
505
505
506
-
tsens_mode: mode@ec {
506
+
tsens_mode: mode@ef {
507
507
reg = <0xef 0x1>;
508
508
bits = <5 3>;
509
509
};
···
1870
1870
};
1871
1871
};
1872
1872
1873
-
pronto: remoteproc@a21b000 {
1873
+
wcnss: remoteproc@a21b000 {
1874
1874
compatible = "qcom,pronto-v2-pil", "qcom,pronto";
1875
1875
reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
1876
1876
reg-names = "ccu", "dxe", "pmu";
···
1896
1896
1897
1897
status = "disabled";
1898
1898
1899
-
iris {
1900
-
compatible = "qcom,wcn3620";
1901
-
1899
+
wcnss_iris: iris {
1900
+
/* Separate chip, compatible is board-specific */
1902
1901
clocks = <&rpmcc RPM_SMD_RF_CLK2>;
1903
1902
clock-names = "xo";
1904
1903
};
···
1915
1916
compatible = "qcom,wcnss";
1916
1917
qcom,smd-channels = "WCNSS_CTRL";
1917
1918
1918
-
qcom,mmio = <&pronto>;
1919
+
qcom,mmio = <&wcnss>;
1919
1920
1920
-
bluetooth {
1921
+
wcnss_bt: bluetooth {
1921
1922
compatible = "qcom,wcnss-bt";
1922
1923
};
1923
1924
1924
-
wifi {
1925
+
wcnss_wifi: wifi {
1925
1926
compatible = "qcom,wcnss-wlan";
1926
1927
1927
1928
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
···
2179
2180
};
2180
2181
};
2181
2182
};
2182
-
2183
2183
};
2184
2184
2185
2185
timer {
+60
-63
arch/arm64/boot/dts/qcom/msm8953.dtsi
+60
-63
arch/arm64/boot/dts/qcom/msm8953.dtsi
···
2
2
/* Copyright (c) 2022, The Linux Foundation. All rights reserved. */
3
3
4
4
#include <dt-bindings/clock/qcom,gcc-msm8953.h>
5
+
#include <dt-bindings/clock/qcom,rpmcc.h>
5
6
#include <dt-bindings/gpio/gpio.h>
6
7
#include <dt-bindings/interrupt-controller/arm-gic.h>
7
8
#include <dt-bindings/power/qcom-rpmpd.h>
···
270
269
compatible = "qcom,rpm-msm8953";
271
270
qcom,smd-channels = "rpm_requests";
272
271
273
-
rpmcc: rpmcc {
272
+
rpmcc: clock-controller {
274
273
compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc";
275
274
clocks = <&xo_board>;
276
275
clock-names = "xo";
···
281
280
compatible = "qcom,msm8953-rpmpd";
282
281
#power-domain-cells = <1>;
283
282
operating-points-v2 = <&rpmpd_opp_table>;
284
-
285
-
clocks = <&xo_board>;
286
-
clock-names = "ref";
287
283
288
284
rpmpd_opp_table: opp-table {
289
285
compatible = "operating-points-v2";
···
350
352
351
353
rpm_msg_ram: sram@60000 {
352
354
compatible = "qcom,rpm-msg-ram";
353
-
reg = <0x60000 0x8000>;
355
+
reg = <0x00060000 0x8000>;
354
356
};
355
357
356
358
hsusb_phy: phy@79000 {
357
359
compatible = "qcom,msm8953-qusb2-phy";
358
-
reg = <0x79000 0x180>;
360
+
reg = <0x00079000 0x180>;
359
361
#phy-cells = <0>;
360
362
361
363
clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>,
···
378
380
379
381
tsens0: thermal-sensor@4a9000 {
380
382
compatible = "qcom,msm8953-tsens", "qcom,tsens-v2";
381
-
reg = <0x4a9000 0x1000>, /* TM */
382
-
<0x4a8000 0x1000>; /* SROT */
383
+
reg = <0x004a9000 0x1000>, /* TM */
384
+
<0x004a8000 0x1000>; /* SROT */
383
385
#qcom,sensors = <16>;
384
386
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
385
387
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
···
389
391
390
392
restart@4ab000 {
391
393
compatible = "qcom,pshold";
392
-
reg = <0x4ab000 0x4>;
394
+
reg = <0x004ab000 0x4>;
393
395
};
394
396
395
397
tlmm: pinctrl@1000000 {
396
398
compatible = "qcom,msm8953-pinctrl";
397
-
reg = <0x1000000 0x300000>;
399
+
reg = <0x01000000 0x300000>;
398
400
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
399
401
gpio-controller;
400
402
gpio-ranges = <&tlmm 0 0 142>;
···
634
636
635
637
gcc: clock-controller@1800000 {
636
638
compatible = "qcom,gcc-msm8953";
637
-
reg = <0x1800000 0x80000>;
639
+
reg = <0x01800000 0x80000>;
638
640
#clock-cells = <1>;
639
641
#reset-cells = <1>;
640
642
#power-domain-cells = <1>;
641
-
clocks = <&xo_board>,
643
+
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
642
644
<&sleep_clk>,
643
-
<0>,
644
-
<0>,
645
-
<0>,
646
-
<0>;
645
+
<&dsi0_phy 1>,
646
+
<&dsi0_phy 0>,
647
+
<&dsi1_phy 1>,
648
+
<&dsi1_phy 0>;
647
649
clock-names = "xo",
648
650
"sleep",
649
651
"dsi0pll",
···
654
656
655
657
tcsr_mutex: hwlock@1905000 {
656
658
compatible = "qcom,tcsr-mutex";
657
-
reg = <0x1905000 0x20000>;
659
+
reg = <0x01905000 0x20000>;
658
660
#hwlock-cells = <1>;
659
661
};
660
662
661
663
tcsr: syscon@1937000 {
662
664
compatible = "qcom,tcsr-msm8953", "syscon";
663
-
reg = <0x1937000 0x30000>;
665
+
reg = <0x01937000 0x30000>;
664
666
};
665
667
666
668
tcsr_phy_clk_scheme_sel: syscon@193f044 {
667
669
compatible = "qcom,tcsr-msm8953", "syscon";
668
-
reg = <0x193f044 0x4>;
670
+
reg = <0x0193f044 0x4>;
669
671
};
670
672
671
673
mdss: display-subsystem@1a00000 {
672
674
compatible = "qcom,mdss";
673
675
674
-
reg = <0x1a00000 0x1000>,
675
-
<0x1ab0000 0x1040>;
676
+
reg = <0x01a00000 0x1000>,
677
+
<0x01ab0000 0x1040>;
676
678
reg-names = "mdss_phys",
677
679
"vbif_phys";
678
680
···
699
701
700
702
mdp: display-controller@1a01000 {
701
703
compatible = "qcom,msm8953-mdp5", "qcom,mdp5";
702
-
reg = <0x1a01000 0x89000>;
704
+
reg = <0x01a01000 0x89000>;
703
705
reg-names = "mdp_phys";
704
706
705
707
interrupt-parent = <&mdss>;
···
740
742
741
743
dsi0: dsi@1a94000 {
742
744
compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl";
743
-
reg = <0x1a94000 0x400>;
745
+
reg = <0x01a94000 0x400>;
744
746
reg-names = "dsi_ctrl";
745
747
746
748
interrupt-parent = <&mdss>;
···
792
794
793
795
dsi0_phy: phy@1a94400 {
794
796
compatible = "qcom,dsi-phy-14nm-8953";
795
-
reg = <0x1a94400 0x100>,
796
-
<0x1a94500 0x300>,
797
-
<0x1a94800 0x188>;
797
+
reg = <0x01a94400 0x100>,
798
+
<0x01a94500 0x300>,
799
+
<0x01a94800 0x188>;
798
800
reg-names = "dsi_phy",
799
801
"dsi_phy_lane",
800
802
"dsi_pll";
···
802
804
#clock-cells = <1>;
803
805
#phy-cells = <0>;
804
806
805
-
clocks = <&gcc GCC_MDSS_AHB_CLK>, <&xo_board>;
807
+
clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
806
808
clock-names = "iface", "ref";
807
809
808
810
status = "disabled";
···
810
812
811
813
dsi1: dsi@1a96000 {
812
814
compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl";
813
-
reg = <0x1a96000 0x400>;
815
+
reg = <0x01a96000 0x400>;
814
816
reg-names = "dsi_ctrl";
815
817
816
818
interrupt-parent = <&mdss>;
···
859
861
860
862
dsi1_phy: phy@1a96400 {
861
863
compatible = "qcom,dsi-phy-14nm-8953";
862
-
reg = <0x1a96400 0x100>,
863
-
<0x1a96500 0x300>,
864
-
<0x1a96800 0x188>;
864
+
reg = <0x01a96400 0x100>,
865
+
<0x01a96500 0x300>,
866
+
<0x01a96800 0x188>;
865
867
reg-names = "dsi_phy",
866
868
"dsi_phy_lane",
867
869
"dsi_pll";
···
869
871
#clock-cells = <1>;
870
872
#phy-cells = <0>;
871
873
872
-
clocks = <&gcc GCC_MDSS_AHB_CLK>, <&xo_board>;
874
+
clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
873
875
clock-names = "iface", "ref";
874
876
875
877
status = "disabled";
···
878
880
879
881
apps_iommu: iommu@1e00000 {
880
882
compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1";
881
-
ranges = <0 0x1e20000 0x20000>;
883
+
ranges = <0 0x01e20000 0x20000>;
882
884
883
885
clocks = <&gcc GCC_SMMU_CFG_CLK>,
884
886
<&gcc GCC_APSS_TCU_ASYNC_CLK>;
···
914
916
915
917
spmi_bus: spmi@200f000 {
916
918
compatible = "qcom,spmi-pmic-arb";
917
-
reg = <0x200f000 0x1000>,
918
-
<0x2400000 0x800000>,
919
-
<0x2c00000 0x800000>,
920
-
<0x3800000 0x200000>,
921
-
<0x200a000 0x2100>;
919
+
reg = <0x0200f000 0x1000>,
920
+
<0x02400000 0x800000>,
921
+
<0x02c00000 0x800000>,
922
+
<0x03800000 0x200000>,
923
+
<0x0200a000 0x2100>;
922
924
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
923
925
interrupt-names = "periph_irq";
924
926
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
···
933
935
934
936
usb3: usb@70f8800 {
935
937
compatible = "qcom,msm8953-dwc3", "qcom,dwc3";
936
-
reg = <0x70f8800 0x400>;
938
+
reg = <0x070f8800 0x400>;
937
939
#address-cells = <1>;
938
940
#size-cells = <1>;
939
941
ranges;
···
977
979
snps,hird-threshold = /bits/ 8 <0x00>;
978
980
979
981
maximum-speed = "high-speed";
980
-
phy_mode = "utmi";
981
982
};
982
983
};
983
984
984
985
sdhc_1: mmc@7824900 {
985
986
compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";
986
987
987
-
reg = <0x7824900 0x500>, <0x7824000 0x800>;
988
+
reg = <0x07824900 0x500>, <0x07824000 0x800>;
988
989
reg-names = "hc", "core";
989
990
990
991
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
···
992
995
993
996
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
994
997
<&gcc GCC_SDCC1_APPS_CLK>,
995
-
<&xo_board>;
998
+
<&rpmcc RPM_SMD_XO_CLK_SRC>;
996
999
clock-names = "iface", "core", "xo";
997
1000
998
1001
power-domains = <&rpmpd MSM8953_VDDCX>;
···
1043
1046
sdhc_2: mmc@7864900 {
1044
1047
compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";
1045
1048
1046
-
reg = <0x7864900 0x500>, <0x7864000 0x800>;
1049
+
reg = <0x07864900 0x500>, <0x07864000 0x800>;
1047
1050
reg-names = "hc", "core";
1048
1051
1049
1052
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
···
1052
1055
1053
1056
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1054
1057
<&gcc GCC_SDCC2_APPS_CLK>,
1055
-
<&xo_board>;
1058
+
<&rpmcc RPM_SMD_XO_CLK_SRC>;
1056
1059
clock-names = "iface", "core", "xo";
1057
1060
1058
1061
power-domains = <&rpmpd MSM8953_VDDCX>;
···
1098
1101
1099
1102
uart_0: serial@78af000 {
1100
1103
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1101
-
reg = <0x78af000 0x200>;
1104
+
reg = <0x078af000 0x200>;
1102
1105
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1103
1106
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
1104
1107
<&gcc GCC_BLSP1_AHB_CLK>;
···
1109
1112
1110
1113
i2c_1: i2c@78b5000 {
1111
1114
compatible = "qcom,i2c-qup-v2.2.1";
1112
-
reg = <0x78b5000 0x600>;
1115
+
reg = <0x078b5000 0x600>;
1113
1116
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1114
1117
clock-names = "core", "iface";
1115
1118
clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
···
1127
1130
1128
1131
i2c_2: i2c@78b6000 {
1129
1132
compatible = "qcom,i2c-qup-v2.2.1";
1130
-
reg = <0x78b6000 0x600>;
1133
+
reg = <0x078b6000 0x600>;
1131
1134
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1132
1135
clock-names = "core", "iface";
1133
1136
clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
···
1145
1148
1146
1149
i2c_3: i2c@78b7000 {
1147
1150
compatible = "qcom,i2c-qup-v2.2.1";
1148
-
reg = <0x78b7000 0x600>;
1151
+
reg = <0x078b7000 0x600>;
1149
1152
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1150
1153
clock-names = "core", "iface";
1151
1154
clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
···
1162
1165
1163
1166
i2c_4: i2c@78b8000 {
1164
1167
compatible = "qcom,i2c-qup-v2.2.1";
1165
-
reg = <0x78b8000 0x600>;
1168
+
reg = <0x078b8000 0x600>;
1166
1169
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1167
1170
clock-names = "core", "iface";
1168
1171
clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
···
1179
1182
1180
1183
i2c_5: i2c@7af5000 {
1181
1184
compatible = "qcom,i2c-qup-v2.2.1";
1182
-
reg = <0x7af5000 0x600>;
1185
+
reg = <0x07af5000 0x600>;
1183
1186
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1184
1187
clock-names = "core", "iface";
1185
1188
clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
···
1196
1199
1197
1200
i2c_6: i2c@7af6000 {
1198
1201
compatible = "qcom,i2c-qup-v2.2.1";
1199
-
reg = <0x7af6000 0x600>;
1202
+
reg = <0x07af6000 0x600>;
1200
1203
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1201
1204
clock-names = "core", "iface";
1202
1205
clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
···
1213
1216
1214
1217
i2c_7: i2c@7af7000 {
1215
1218
compatible = "qcom,i2c-qup-v2.2.1";
1216
-
reg = <0x7af7000 0x600>;
1219
+
reg = <0x07af7000 0x600>;
1217
1220
interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
1218
1221
clock-names = "core", "iface";
1219
1222
clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
···
1230
1233
1231
1234
i2c_8: i2c@7af8000 {
1232
1235
compatible = "qcom,i2c-qup-v2.2.1";
1233
-
reg = <0x7af8000 0x600>;
1236
+
reg = <0x07af8000 0x600>;
1234
1237
interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
1235
1238
clock-names = "core", "iface";
1236
1239
clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
···
1254
1257
1255
1258
apcs: mailbox@b011000 {
1256
1259
compatible = "qcom,msm8953-apcs-kpss-global", "syscon";
1257
-
reg = <0xb011000 0x1000>;
1260
+
reg = <0x0b011000 0x1000>;
1258
1261
#mbox-cells = <1>;
1259
1262
};
1260
1263
1261
1264
timer@b120000 {
1262
1265
compatible = "arm,armv7-timer-mem";
1263
-
reg = <0xb120000 0x1000>;
1266
+
reg = <0x0b120000 0x1000>;
1264
1267
#address-cells = <0x01>;
1265
1268
#size-cells = <0x01>;
1266
1269
ranges;
···
1269
1272
frame-number = <0>;
1270
1273
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1271
1274
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1272
-
reg = <0xb121000 0x1000>,
1273
-
<0xb122000 0x1000>;
1275
+
reg = <0x0b121000 0x1000>,
1276
+
<0x0b122000 0x1000>;
1274
1277
};
1275
1278
1276
1279
frame@b123000 {
1277
1280
frame-number = <1>;
1278
1281
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1279
-
reg = <0xb123000 0x1000>;
1282
+
reg = <0x0b123000 0x1000>;
1280
1283
status = "disabled";
1281
1284
};
1282
1285
1283
1286
frame@b124000 {
1284
1287
frame-number = <2>;
1285
1288
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1286
-
reg = <0xb124000 0x1000>;
1289
+
reg = <0x0b124000 0x1000>;
1287
1290
status = "disabled";
1288
1291
};
1289
1292
1290
1293
frame@b125000 {
1291
1294
frame-number = <3>;
1292
1295
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1293
-
reg = <0xb125000 0x1000>;
1296
+
reg = <0x0b125000 0x1000>;
1294
1297
status = "disabled";
1295
1298
};
1296
1299
1297
1300
frame@b126000 {
1298
1301
frame-number = <4>;
1299
1302
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1300
-
reg = <0xb126000 0x1000>;
1303
+
reg = <0x0b126000 0x1000>;
1301
1304
status = "disabled";
1302
1305
};
1303
1306
1304
1307
frame@b127000 {
1305
1308
frame-number = <5>;
1306
1309
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1307
-
reg = <0xb127000 0x1000>;
1310
+
reg = <0x0b127000 0x1000>;
1308
1311
status = "disabled";
1309
1312
};
1310
1313
1311
1314
frame@b128000 {
1312
1315
frame-number = <6>;
1313
1316
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1314
-
reg = <0xb128000 0x1000>;
1317
+
reg = <0x0b128000 0x1000>;
1315
1318
status = "disabled";
1316
1319
};
1317
1320
};
+4
arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi
+4
arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi
+9
-1
arch/arm64/boot/dts/qcom/msm8976.dtsi
+9
-1
arch/arm64/boot/dts/qcom/msm8976.dtsi
···
20
20
21
21
chosen { };
22
22
23
+
clocks {
24
+
xo_board: xo-board {
25
+
compatible = "fixed-clock";
26
+
#clock-cells = <0>;
27
+
};
28
+
};
29
+
23
30
cpus {
24
31
#address-cells = <1>;
25
32
#size-cells = <0>;
···
358
351
359
352
rpmcc: clock-controller {
360
353
compatible = "qcom,rpmcc-msm8976", "qcom,rpmcc";
354
+
clocks = <&xo_board>;
355
+
clock-names = "xo";
361
356
#clock-cells = <1>;
362
357
};
363
358
···
818
809
#size-cells = <0>;
819
810
interrupt-controller;
820
811
#interrupt-cells = <4>;
821
-
cell-index = <0>;
822
812
};
823
813
824
814
sdhc_1: mmc@7824000 {
+1
-4
arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi
+1
-4
arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi
···
46
46
};
47
47
48
48
clocks {
49
-
compatible = "simple-bus";
50
-
51
49
divclk4: divclk4 {
52
50
compatible = "fixed-clock";
53
51
#clock-cells = <0>;
···
540
542
};
541
543
542
544
&pmi8994_spmi_regulators {
543
-
vdd_gfx: s2@1700 {
544
-
reg = <0x1700 0x100>;
545
+
vdd_gfx: s2 {
545
546
regulator-min-microvolt = <980000>;
546
547
regulator-max-microvolt = <980000>;
547
548
};
+1
-2
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi
+1
-2
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi
···
173
173
* power domain.. which still isn't enough and forces us to bind
174
174
* OXILI_CX and OXILI_GX together!
175
175
*/
176
-
vdd_gfx: s2@1700 {
177
-
reg = <0x1700 0x100>;
176
+
vdd_gfx: s2 {
178
177
regulator-name = "VDD_GFX";
179
178
regulator-min-microvolt = <980000>;
180
179
regulator-max-microvolt = <980000>;
+1
-1
arch/arm64/boot/dts/qcom/msm8994.dtsi
+1
-1
arch/arm64/boot/dts/qcom/msm8994.dtsi
+41
-26
arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi
+41
-26
arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi
···
85
85
};
86
86
};
87
87
88
-
&adsp_pil {
89
-
status = "okay";
90
-
};
91
-
92
88
&blsp1_i2c3 {
93
89
status = "okay";
94
90
···
179
183
status = "okay";
180
184
};
181
185
182
-
&gpu {
183
-
status = "okay";
184
-
};
185
-
186
186
&hsusb_phy1 {
187
187
vdd-supply = <&vreg_l28a_0p925>;
188
188
vdda-pll-supply = <&vreg_l12a_1p8>;
···
207
215
208
216
&mss_pil {
209
217
pll-supply = <&vreg_l12a_1p8>;
210
-
status = "okay";
211
218
};
212
219
213
220
&pcie0 {
···
495
504
};
496
505
};
497
506
498
-
&slpi_pil {
507
+
&slim_msm {
499
508
status = "okay";
509
+
510
+
slim@1 {
511
+
reg = <1>;
512
+
#address-cells = <2>;
513
+
#size-cells = <0>;
514
+
515
+
tasha_ifd: tas-ifd@0,0 {
516
+
compatible = "slim217,1a0";
517
+
reg = <0 0>;
518
+
};
519
+
520
+
wcd9335: codec@1,0 {
521
+
compatible = "slim217,1a0";
522
+
reg = <1 0>;
523
+
524
+
clock-names = "mclk", "slimbus";
525
+
clocks = <&div1_mclk>,
526
+
<&rpmcc RPM_SMD_BB_CLK1>;
527
+
interrupt-parent = <&tlmm>;
528
+
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
529
+
<53 IRQ_TYPE_LEVEL_HIGH>;
530
+
interrupt-names = "intr1", "intr2";
531
+
interrupt-controller;
532
+
#interrupt-cells = <1>;
533
+
534
+
pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
535
+
pinctrl-names = "default";
536
+
537
+
reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
538
+
slim-ifc-dev = <&tasha_ifd>;
539
+
540
+
#sound-dai-cells = <1>;
541
+
542
+
vdd-buck-supply = <&vreg_s4a_1p8>;
543
+
vdd-buck-sido-supply = <&vreg_s4a_1p8>;
544
+
vdd-tx-supply = <&vreg_s4a_1p8>;
545
+
vdd-rx-supply = <&vreg_s4a_1p8>;
546
+
vdd-io-supply = <&vreg_s4a_1p8>;
547
+
};
548
+
};
500
549
};
501
550
502
551
&sound {
···
798
767
phy-names = "usb2-phy";
799
768
800
769
maximum-speed = "high-speed";
801
-
};
802
-
803
-
&venus {
804
-
status = "okay";
805
-
};
806
-
807
-
&wcd9335 {
808
-
clock-names = "mclk", "slimbus";
809
-
clocks = <&div1_mclk>,
810
-
<&rpmcc RPM_SMD_BB_CLK1>;
811
-
812
-
vdd-buck-supply = <&vreg_s4a_1p8>;
813
-
vdd-buck-sido-supply = <&vreg_s4a_1p8>;
814
-
vdd-tx-supply = <&vreg_s4a_1p8>;
815
-
vdd-rx-supply = <&vreg_s4a_1p8>;
816
-
vdd-io-supply = <&vreg_s4a_1p8>;
817
770
};
+6
arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts
+6
arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts
···
17
17
18
18
&adsp_pil {
19
19
firmware-name = "qcom/msm8996/oneplus3/adsp.mbn";
20
+
status = "okay";
20
21
};
21
22
22
23
&battery {
···
26
25
};
27
26
28
27
&gpu {
28
+
status = "okay";
29
+
29
30
zap-shader {
30
31
firmware-name = "qcom/msm8996/oneplus3/a530_zap.mbn";
31
32
};
···
36
33
&mss_pil {
37
34
firmware-name = "qcom/msm8996/oneplus3/mba.mbn",
38
35
"qcom/msm8996/oneplus3/modem.mbn";
36
+
status = "okay";
39
37
};
40
38
41
39
&slpi_pil {
42
40
firmware-name = "qcom/msm8996/oneplus3/slpi.mbn";
41
+
status = "okay";
43
42
};
44
43
45
44
&venus {
46
45
firmware-name = "qcom/msm8996/oneplus3/venus.mbn";
46
+
status = "okay";
47
47
};
+6
arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts
+6
arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts
···
18
18
19
19
&adsp_pil {
20
20
firmware-name = "qcom/msm8996/oneplus3t/adsp.mbn";
21
+
status = "okay";
21
22
};
22
23
23
24
&battery {
···
27
26
};
28
27
29
28
&gpu {
29
+
status = "okay";
30
+
30
31
zap-shader {
31
32
firmware-name = "qcom/msm8996/oneplus3t/a530_zap.mbn";
32
33
};
···
37
34
&mss_pil {
38
35
firmware-name = "qcom/msm8996/oneplus3t/mba.mbn",
39
36
"qcom/msm8996/oneplus3t/modem.mbn";
37
+
status = "okay";
40
38
};
41
39
42
40
&slpi_pil {
43
41
firmware-name = "qcom/msm8996/oneplus3t/slpi.mbn";
42
+
status = "okay";
44
43
};
45
44
46
45
&venus {
47
46
firmware-name = "qcom/msm8996/oneplus3t/venus.mbn";
47
+
status = "okay";
48
48
};
+46
-16
arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
+46
-16
arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
···
12
12
13
13
/ {
14
14
clocks {
15
-
compatible = "simple-bus";
16
-
17
15
divclk1_cdc: divclk1 {
18
16
compatible = "gpio-gate-clock";
19
17
clocks = <&rpmcc RPM_SMD_DIV_CLK1>;
···
335
337
};
336
338
};
337
339
340
+
&slim_msm {
341
+
status = "okay";
342
+
343
+
slim@1 {
344
+
reg = <1>;
345
+
#address-cells = <2>;
346
+
#size-cells = <0>;
347
+
348
+
tasha_ifd: tas-ifd@0,0 {
349
+
compatible = "slim217,1a0";
350
+
reg = <0 0>;
351
+
};
352
+
353
+
wcd9335: codec@1,0 {
354
+
compatible = "slim217,1a0";
355
+
reg = <1 0>;
356
+
357
+
clock-names = "mclk", "slimbus";
358
+
clocks = <&divclk1_cdc>,
359
+
<&rpmcc RPM_SMD_BB_CLK1>;
360
+
interrupt-parent = <&tlmm>;
361
+
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
362
+
<53 IRQ_TYPE_LEVEL_HIGH>;
363
+
interrupt-names = "intr1", "intr2";
364
+
interrupt-controller;
365
+
#interrupt-cells = <1>;
366
+
367
+
pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
368
+
pinctrl-names = "default";
369
+
370
+
reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
371
+
slim-ifc-dev = <&tasha_ifd>;
372
+
373
+
#sound-dai-cells = <1>;
374
+
375
+
vdd-buck-supply = <&vreg_s4a_1p8>;
376
+
vdd-buck-sido-supply = <&vreg_s4a_1p8>;
377
+
vdd-rx-supply = <&vreg_s4a_1p8>;
378
+
vdd-tx-supply = <&vreg_s4a_1p8>;
379
+
vdd-vbat-supply = <&vph_pwr>;
380
+
vdd-micbias-supply = <&vph_pwr_bbyp>;
381
+
vdd-io-supply = <&vreg_s4a_1p8>;
382
+
};
383
+
};
384
+
};
385
+
338
386
&slpi_pil {
339
387
status = "okay";
340
388
···
437
393
438
394
&venus {
439
395
status = "okay";
440
-
};
441
-
442
-
&wcd9335 {
443
-
clock-names = "mclk", "slimbus";
444
-
clocks = <&divclk1_cdc>,
445
-
<&rpmcc RPM_SMD_BB_CLK1>;
446
-
447
-
vdd-buck-supply = <&vreg_s4a_1p8>;
448
-
vdd-buck-sido-supply = <&vreg_s4a_1p8>;
449
-
vdd-rx-supply = <&vreg_s4a_1p8>;
450
-
vdd-tx-supply = <&vreg_s4a_1p8>;
451
-
vdd-vbat-supply = <&vph_pwr>;
452
-
vdd-micbias-supply = <&vph_pwr_bbyp>;
453
-
vdd-io-supply = <&vreg_s4a_1p8>;
454
396
};
455
397
456
398
&rpm_requests {
+10
-37
arch/arm64/boot/dts/qcom/msm8996.dtsi
+10
-37
arch/arm64/boot/dts/qcom/msm8996.dtsi
···
1851
1851
1852
1852
#address-cells = <3>;
1853
1853
#size-cells = <2>;
1854
-
ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
1855
-
<0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1854
+
ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>,
1855
+
<0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1856
1856
1857
1857
device_type = "pci";
1858
1858
···
1882
1882
"cfg",
1883
1883
"bus_master",
1884
1884
"bus_slave";
1885
-
1886
1885
};
1887
1886
1888
1887
pcie1: pcie@608000 {
···
1904
1905
1905
1906
#address-cells = <3>;
1906
1907
#size-cells = <2>;
1907
-
ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
1908
-
<0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1908
+
ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>,
1909
+
<0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1909
1910
1910
1911
device_type = "pci";
1911
1912
···
1955
1956
1956
1957
#address-cells = <3>;
1957
1958
#size-cells = <2>;
1958
-
ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
1959
-
<0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
1959
+
ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>,
1960
+
<0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
1960
1961
1961
1962
device_type = "pci";
1962
1963
···
3005
3006
interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
3006
3007
phys = <&hsusb_phy1>, <&ssusb_phy_0>;
3007
3008
phy-names = "usb2-phy", "usb3-phy";
3009
+
snps,hird-threshold = /bits/ 8 <0>;
3008
3010
snps,dis_u2_susphy_quirk;
3009
3011
snps,dis_enblslpm_quirk;
3012
+
snps,is-utmi-l1-suspend;
3013
+
tx-fifo-resize;
3010
3014
};
3011
3015
};
3012
3016
···
3385
3383
dma-names = "rx", "tx";
3386
3384
#address-cells = <1>;
3387
3385
#size-cells = <0>;
3388
-
slim@1 {
3389
-
reg = <1>;
3390
-
#address-cells = <2>;
3391
-
#size-cells = <0>;
3392
3386
3393
-
tasha_ifd: tas-ifd@0,0 {
3394
-
compatible = "slim217,1a0";
3395
-
reg = <0 0>;
3396
-
};
3397
-
3398
-
wcd9335: codec@1,0 {
3399
-
pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
3400
-
pinctrl-names = "default";
3401
-
3402
-
compatible = "slim217,1a0";
3403
-
reg = <1 0>;
3404
-
3405
-
interrupt-parent = <&tlmm>;
3406
-
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
3407
-
<53 IRQ_TYPE_LEVEL_HIGH>;
3408
-
interrupt-names = "intr1", "intr2";
3409
-
interrupt-controller;
3410
-
#interrupt-cells = <1>;
3411
-
reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
3412
-
3413
-
slim-ifc-dev = <&tasha_ifd>;
3414
-
3415
-
#sound-dai-cells = <1>;
3416
-
};
3417
-
};
3387
+
status = "disabled";
3418
3388
};
3419
3389
3420
3390
adsp_pil: remoteproc@9300000 {
···
3470
3496
};
3471
3497
};
3472
3498
};
3473
-
3474
3499
};
3475
3500
};
3476
3501
+2
-2
arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts
+2
-2
arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts
···
44
44
label = "Keyboard Hall Sensor";
45
45
gpios = <&tlmm 124 GPIO_ACTIVE_HIGH>;
46
46
debounce-interval = <15>;
47
-
gpio-key,wakeup;
47
+
wakeup-source;
48
48
linux,input-type = <EV_SW>;
49
49
linux,code = <SW_KEYPAD_SLIDE>;
50
50
};
···
116
116
gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>;
117
117
linux,input-type = <EV_KEY>;
118
118
linux,code = <KEY_VOLUMEUP>;
119
-
gpio-key,wakeup;
119
+
wakeup-source;
120
120
debounce-interval = <15>;
121
121
};
122
122
+1
-1
arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts
+1
-1
arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts
+177
-2
arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts
+177
-2
arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts
···
22
22
enable-active-high;
23
23
gpio = <&pmi8998_gpios 10 GPIO_ACTIVE_HIGH>;
24
24
pinctrl-names = "default";
25
-
pinctrl-0 = <&disp_dvdd_en>;
25
+
pinctrl-0 = <&four_k_disp_dcdc_en>;
26
26
};
27
27
};
28
28
···
37
37
qcom,soft-start-us = <200>;
38
38
};
39
39
40
+
&pm8005_gpios {
41
+
gpio-line-names = "EAR_EN", /* GPIO_1 */
42
+
"NC",
43
+
"SLB",
44
+
"OPTION_1_PM8005";
45
+
};
46
+
40
47
&pmi8998_gpios {
41
-
disp_dvdd_en: disp-dvdd-en-active-state {
48
+
gpio-line-names = "MAIN_CAM_PWR_IO_EN", /* GPIO_1 */
49
+
"NC",
50
+
"NC",
51
+
"TYPEC_UUSB_SEL",
52
+
"VIB_LDO_EN",
53
+
"NC",
54
+
"DISPLAY_TYPE_SEL",
55
+
"USB_SWITCH_SEL",
56
+
"NC",
57
+
"4K_DISP_DCDC_EN", /* GPIO_10 */
58
+
"NC",
59
+
"DIV_CLK3",
60
+
"SPMI_I2C_SEL",
61
+
"NC";
62
+
63
+
four_k_disp_dcdc_en: 4k-disp-dcdc-en-state {
42
64
pins = "gpio10";
43
65
function = "normal";
44
66
bias-disable;
···
69
47
power-source = <0>;
70
48
qcom,drive-strength = <1>;
71
49
};
50
+
};
51
+
52
+
&tlmm {
53
+
gpio-line-names = "", /* GPIO_0 */
54
+
"",
55
+
"",
56
+
"",
57
+
"DEBUG_UART_TX",
58
+
"DEBUG_UART_RX",
59
+
"CAMSENSOR_I2C_SDA",
60
+
"CAMSENSOR_I2C_SCL",
61
+
"NC",
62
+
"NC",
63
+
"MDP_VSYNC_P", /* GPIO_10 */
64
+
"RGBC_IR_INT",
65
+
"NFC_VEN",
66
+
"CAM_MCLK0",
67
+
"CAM_MCLK1",
68
+
"NC",
69
+
"NC",
70
+
"CCI_I2C_SDA0",
71
+
"CCI_I2C_SCL0",
72
+
"CCI_I2C_SDA1",
73
+
"CCI_I2C_SCL1", /* GPIO_20 */
74
+
"MAIN_CAM_PWR_EN",
75
+
"TOF_INT_N",
76
+
"NC",
77
+
"NC",
78
+
"CHAT_CAM_PWR_EN",
79
+
"NC",
80
+
"TOF_RESET_N",
81
+
"CAM2_RSTN",
82
+
"NC",
83
+
"CAM1_RSTN", /* GPIO_30 */
84
+
"NC",
85
+
"NC",
86
+
"NC",
87
+
"NC",
88
+
"NC",
89
+
"NC",
90
+
"NC",
91
+
"CC_DIR",
92
+
"UIM2_DETECT_EN",
93
+
"FP_RESET_N", /* GPIO_40 */
94
+
"NC",
95
+
"NC",
96
+
"NC",
97
+
"NC",
98
+
"BT_HCI_UART_TXD",
99
+
"BT_HCI_UART_RXD",
100
+
"BT_HCI_UART_CTS_N",
101
+
"BT_HCI_UART_RFR_N",
102
+
"NC",
103
+
"NC", /* GPIO_50 */
104
+
"NC",
105
+
"NC",
106
+
"CODEC_INT2_N",
107
+
"CODEC_INT1_N",
108
+
"APPS_I2C_SDA",
109
+
"APPS_I2C_SCL",
110
+
"FORCED_USB_BOOT",
111
+
"NC",
112
+
"NC",
113
+
"NC", /* GPIO_60 */
114
+
"NC",
115
+
"NC",
116
+
"TRAY2_DET_DS",
117
+
"CODEC_RST_N",
118
+
"WSA_L_EN",
119
+
"WSA_R_EN",
120
+
"NC",
121
+
"NC",
122
+
"NC",
123
+
"LPASS_SLIMBUS_CLK", /* GPIO_70 */
124
+
"LPASS_SLIMBUS_DATA0",
125
+
"LPASS_SLIMBUS_DATA1",
126
+
"BT_FM_SLIMBUS_DATA",
127
+
"BT_FM_SLIMBUS_CLK",
128
+
"NC",
129
+
"RF_LCD_ID_EN",
130
+
"NC",
131
+
"NC",
132
+
"NC",
133
+
"NC", /* GPIO_80 */
134
+
"SW_SERVICE",
135
+
"TX_GTR_THRES_IN",
136
+
"HW_ID0",
137
+
"HW_ID1",
138
+
"NC",
139
+
"NC",
140
+
"TS_I2C_SDA",
141
+
"TS_I2C_SCL",
142
+
"TS_RESET_N",
143
+
"NC", /* GPIO_90 */
144
+
"NC",
145
+
"NFC_IRQ",
146
+
"NFC_DWLD_EN",
147
+
"DISP_RESET_N",
148
+
"TRAY2_DET",
149
+
"CAM_SOF",
150
+
"RFFE6_CLK",
151
+
"RFFE6_DATA",
152
+
"DEBUG_GPIO0",
153
+
"DEBUG_GPIO1", /* GPIO_100 */
154
+
"GRFC4",
155
+
"NC",
156
+
"NC",
157
+
"RSVD",
158
+
"UIM2_DATA",
159
+
"UIM2_CLK",
160
+
"UIM2_RESET",
161
+
"UIM2_PRESENT",
162
+
"UIM1_DATA",
163
+
"UIM1_CLK", /* GPIO_110 */
164
+
"UIM1_RST",
165
+
"UIM1_PRESENT",
166
+
"UIM_BATT_ALARM",
167
+
"RSVD",
168
+
"NC",
169
+
"NC",
170
+
"ACCEL_INT",
171
+
"GYRO_INT",
172
+
"COMPASS_INT",
173
+
"ALS_PROX_INT_N", /* GPIO_120 */
174
+
"FP_INT_N",
175
+
"NC",
176
+
"BAROMETER_INT",
177
+
"ACC_COVER_OPEN",
178
+
"TS_INT_N",
179
+
"NC",
180
+
"NC",
181
+
"USB_DETECT_EN",
182
+
"NC",
183
+
"QLINK_REQUEST", /* GPIO_130 */
184
+
"QLINK_ENABLE",
185
+
"NC",
186
+
"TS_VDDIO_EN",
187
+
"WMSS_RESET_N",
188
+
"PA_INDICATOR_OR",
189
+
"NC",
190
+
"RFFE3_DATA",
191
+
"RFFE3_CLK",
192
+
"RFFE4_DATA",
193
+
"RFFE4_CLK", /* GPIO_140 */
194
+
"RFFE5_DATA",
195
+
"RFFE5_CLK",
196
+
"GNSS_EN",
197
+
"MSS_LTE_COXM_TXD",
198
+
"MSS_LTE_COXM_RXD",
199
+
"RFFE2_DATA",
200
+
"RFFE2_CLK",
201
+
"RFFE1_DATA",
202
+
"RFFE1_CLK";
72
203
};
73
204
74
205
&vreg_l22a_2p85 {
+231
-33
arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi
+231
-33
arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi
···
21
21
clocks {
22
22
div1_mclk: divclk1 {
23
23
compatible = "gpio-gate-clock";
24
-
pinctrl-0 = <&audio_mclk_pin>;
24
+
pinctrl-0 = <&div_clk1>;
25
25
pinctrl-names = "default";
26
26
clocks = <&rpmcc RPM_SMD_DIV_CLK1>;
27
27
#clock-cells = <0>;
···
46
46
enable-active-high;
47
47
gpio = <&tlmm 21 GPIO_ACTIVE_HIGH>;
48
48
pinctrl-names = "default";
49
-
pinctrl-0 = <&cam0_vdig_default>;
49
+
pinctrl-0 = <&main_cam_pwr_en>;
50
50
};
51
51
52
52
cam1_vdig_vreg: cam1-vdig {
···
56
56
enable-active-high;
57
57
gpio = <&tlmm 25 GPIO_ACTIVE_HIGH>;
58
58
pinctrl-names = "default";
59
-
pinctrl-0 = <&cam1_vdig_default>;
59
+
pinctrl-0 = <&chat_cam_pwr_en>;
60
60
vin-supply = <&vreg_s3a_1p35>;
61
61
};
62
62
···
67
67
enable-active-high;
68
68
gpio = <&pmi8998_gpios 1 GPIO_ACTIVE_HIGH>;
69
69
pinctrl-names = "default";
70
-
pinctrl-0 = <&cam_vio_default>;
70
+
pinctrl-0 = <&main_cam_pwr_io_en>;
71
71
vin-supply = <&vreg_lvs1a_1p8>;
72
72
};
73
73
···
92
92
id-gpio = <&tlmm 38 GPIO_ACTIVE_HIGH>;
93
93
vbus-gpio = <&tlmm 128 GPIO_ACTIVE_HIGH>;
94
94
pinctrl-names = "default";
95
-
pinctrl-0 = <&usb_extcon_active &usb_vbus_active>;
95
+
pinctrl-0 = <&cc_dir_default &usb_detect_en>;
96
96
};
97
97
98
98
gpio-keys {
99
99
compatible = "gpio-keys";
100
100
label = "Side buttons";
101
101
pinctrl-names = "default";
102
-
pinctrl-0 = <&vol_down_pin_a>, <&cam_focus_pin_a>,
103
-
<&cam_snapshot_pin_a>;
102
+
pinctrl-0 = <&vol_down_n &focus_n &snapshot_n>;
104
103
button-vol-down {
105
104
label = "Volume Down";
106
105
gpios = <&pm8998_gpios 5 GPIO_ACTIVE_LOW>;
107
106
linux,input-type = <EV_KEY>;
108
107
linux,code = <KEY_VOLUMEDOWN>;
109
-
gpio-key,wakeup;
108
+
wakeup-source;
110
109
debounce-interval = <15>;
111
110
};
112
111
···
130
131
compatible = "gpio-keys";
131
132
label = "Hall sensors";
132
133
pinctrl-names = "default";
133
-
pinctrl-0 = <&hall_sensor0_default>;
134
+
pinctrl-0 = <&acc_cover_open>;
134
135
135
136
event-hall-sensor0 {
136
137
label = "Cover Hall Sensor";
137
138
gpios = <&tlmm 124 GPIO_ACTIVE_LOW>;
138
139
linux,input-type = <EV_SW>;
139
140
linux,code = <SW_LID>;
140
-
gpio-key,wakeup;
141
+
wakeup-source;
141
142
debounce-interval = <30>;
142
143
};
143
144
};
···
188
189
compatible = "gpio-vibrator";
189
190
enable-gpios = <&pmi8998_gpios 5 GPIO_ACTIVE_HIGH>;
190
191
pinctrl-names = "default";
191
-
pinctrl-0 = <&vib_default>;
192
+
pinctrl-0 = <&vib_ldo_en>;
192
193
};
193
194
};
194
195
···
262
263
vdd-supply = <&cam_vio_vreg>;
263
264
264
265
pinctrl-names = "default";
265
-
pinctrl-0 = <&tof_int &tof_reset>;
266
+
pinctrl-0 = <&tof_int_n &tof_reset>;
266
267
};
267
268
};
268
269
···
291
292
regulator-soft-start;
292
293
};
293
294
295
+
&pm8005_gpios {
296
+
gpio-line-names = "NC", /* GPIO_1 */
297
+
"NC",
298
+
"SLB",
299
+
"OPTION_1_PM8005";
300
+
};
301
+
294
302
&pm8005_regulators {
295
303
/* VDD_GFX supply */
296
304
pm8005_s1: s1 {
···
310
304
};
311
305
312
306
&pm8998_gpios {
313
-
vol_down_pin_a: vol-down-active-state {
307
+
gpio-line-names = "UIM_BATT_ALARM", /* GPIO_1 */
308
+
"NC",
309
+
"WLAN_SW_CTRL (DISALLOWED)",
310
+
"SSC_PWR_EN",
311
+
"VOL_DOWN_N",
312
+
"VOL_UP_N",
313
+
"SNAPSHOT_N",
314
+
"FOCUS_N",
315
+
"FLASH_THERM",
316
+
"", /* GPIO_10 */
317
+
"",
318
+
"",
319
+
"DIV_CLK1",
320
+
"NC",
321
+
"NC (DISALLOWED)",
322
+
"DIV_CLK3",
323
+
"NC",
324
+
"NC",
325
+
"NC",
326
+
"NC (DISALLOWED)", /* GPIO_20 */
327
+
"NFC_CLK_REQ",
328
+
"NC (DISALLOWED)",
329
+
"WCSS_PWR_REQ",
330
+
"OPTION_1 (DISALLOWED)",
331
+
"OPTION_2 (DISALLOWED)",
332
+
"PM_SLB (DISALLOWED)";
333
+
334
+
vol_down_n: vol-down-n-state {
314
335
pins = "gpio5";
315
336
function = PMIC_GPIO_FUNC_NORMAL;
316
337
bias-pull-up;
···
345
312
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
346
313
};
347
314
348
-
cam_focus_pin_a: cam-focus-btn-active-state {
315
+
focus_n: focus-n-state {
349
316
pins = "gpio7";
350
317
function = PMIC_GPIO_FUNC_NORMAL;
351
318
bias-pull-up;
···
353
320
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
354
321
};
355
322
356
-
cam_snapshot_pin_a: cam-snapshot-btn-active-state {
323
+
snapshot_n: snapshot-n-state {
357
324
pins = "gpio8";
358
325
function = PMIC_GPIO_FUNC_NORMAL;
359
326
bias-pull-up;
···
361
328
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
362
329
};
363
330
364
-
audio_mclk_pin: audio-mclk-pin-active-state {
331
+
div_clk1: div-clk1-state {
365
332
pins = "gpio13";
366
333
function = "func2";
367
334
power-source = <0>;
···
369
336
};
370
337
371
338
&pmi8998_gpios {
372
-
cam_vio_default: cam-vio-active-state {
339
+
gpio-line-names = "MAIN_CAM_PWR_IO_EN", /* GPIO_1 */
340
+
"NC",
341
+
"NC",
342
+
"TYPEC_UUSB_SEL",
343
+
"VIB_LDO_EN",
344
+
"NC",
345
+
"DISPLAY_TYPE_SEL",
346
+
"NC",
347
+
"NC",
348
+
"NC", /* GPIO_10 */
349
+
"NC",
350
+
"DIV_CLK3",
351
+
"SPMI_I2C_SEL",
352
+
"NC";
353
+
354
+
main_cam_pwr_io_en: main-cam-pwr-io-en-state {
373
355
pins = "gpio1";
374
356
function = PMIC_GPIO_FUNC_NORMAL;
375
357
bias-disable;
···
394
346
power-source = <1>;
395
347
};
396
348
397
-
vib_default: vib-en-state {
349
+
vib_ldo_en: vib-ldo-en-state {
398
350
pins = "gpio5";
399
351
function = PMIC_GPIO_FUNC_NORMAL;
400
352
bias-disable;
···
638
590
639
591
&tlmm {
640
592
gpio-reserved-ranges = <0 4>, <81 4>;
593
+
gpio-line-names = "", /* GPIO_0 */
594
+
"",
595
+
"",
596
+
"",
597
+
"DEBUG_UART_TX",
598
+
"DEBUG_UART_RX",
599
+
"CAMSENSOR_I2C_SDA",
600
+
"CAMSENSOR_I2C_SCL",
601
+
"NC",
602
+
"NC",
603
+
"MDP_VSYNC_P", /* GPIO_10 */
604
+
"RGBC_IR_INT",
605
+
"NFC_VEN",
606
+
"CAM_MCLK0",
607
+
"CAM_MCLK1",
608
+
"NC",
609
+
"NC",
610
+
"CCI_I2C_SDA0",
611
+
"CCI_I2C_SCL0",
612
+
"CCI_I2C_SDA1",
613
+
"CCI_I2C_SCL1", /* GPIO_20 */
614
+
"MAIN_CAM_PWR_EN",
615
+
"TOF_INT_N",
616
+
"NC",
617
+
"NC",
618
+
"CHAT_CAM_PWR_EN",
619
+
"NC",
620
+
"TOF_RESET_N",
621
+
"CAM2_RSTN",
622
+
"NC",
623
+
"CAM1_RSTN", /* GPIO_30 */
624
+
"NC",
625
+
"NC",
626
+
"NC",
627
+
"NC",
628
+
"NC",
629
+
"NC",
630
+
"NC",
631
+
"CC_DIR",
632
+
"UIM2_DETECT_EN",
633
+
"FP_RESET_N", /* GPIO_40 */
634
+
"NC",
635
+
"NC",
636
+
"NC",
637
+
"NC",
638
+
"BT_HCI_UART_TXD",
639
+
"BT_HCI_UART_RXD",
640
+
"BT_HCI_UART_CTS_N",
641
+
"BT_HCI_UART_RFR_N",
642
+
"NC",
643
+
"NC", /* GPIO_50 */
644
+
"NC",
645
+
"NC",
646
+
"CODEC_INT2_N",
647
+
"CODEC_INT1_N",
648
+
"APPS_I2C_SDA",
649
+
"APPS_I2C_SCL",
650
+
"FORCED_USB_BOOT",
651
+
"NC",
652
+
"NC",
653
+
"NC", /* GPIO_60 */
654
+
"NC",
655
+
"NC",
656
+
"TRAY2_DET_DS",
657
+
"CODEC_RST_N",
658
+
"WSA_L_EN",
659
+
"WSA_R_EN",
660
+
"NC",
661
+
"NC",
662
+
"NC",
663
+
"LPASS_SLIMBUS_CLK", /* GPIO_70 */
664
+
"LPASS_SLIMBUS_DATA0",
665
+
"LPASS_SLIMBUS_DATA1",
666
+
"BT_FM_SLIMBUS_DATA",
667
+
"BT_FM_SLIMBUS_CLK",
668
+
"NC",
669
+
"RF_LCD_ID_EN",
670
+
"NC",
671
+
"NC",
672
+
"NC",
673
+
"NC", /* GPIO_80 */
674
+
"SW_SERVICE",
675
+
"TX_GTR_THRES_IN",
676
+
"HW_ID0",
677
+
"HW_ID1",
678
+
"NC",
679
+
"NC",
680
+
"TS_I2C_SDA",
681
+
"TS_I2C_SCL",
682
+
"TS_RESET_N",
683
+
"NC", /* GPIO_90 */
684
+
"NC",
685
+
"NFC_IRQ",
686
+
"NFC_DWLD_EN",
687
+
"DISP_RESET_N",
688
+
"TRAY2_DET",
689
+
"CAM_SOF",
690
+
"RFFE6_CLK",
691
+
"RFFE6_DATA",
692
+
"DEBUG_GPIO0",
693
+
"DEBUG_GPIO1", /* GPIO_100 */
694
+
"GRFC4",
695
+
"NC",
696
+
"NC",
697
+
"RSVD",
698
+
"UIM2_DATA",
699
+
"UIM2_CLK",
700
+
"UIM2_RESET",
701
+
"UIM2_PRESENT",
702
+
"UIM1_DATA",
703
+
"UIM1_CLK", /* GPIO_110 */
704
+
"UIM1_RST",
705
+
"UIM1_PRESENT",
706
+
"UIM_BATT_ALARM",
707
+
"RSVD",
708
+
"NC",
709
+
"NC",
710
+
"ACCEL_INT",
711
+
"GYRO_INT",
712
+
"COMPASS_INT",
713
+
"ALS_PROX_INT_N", /* GPIO_120 */
714
+
"FP_INT_N",
715
+
"NC",
716
+
"BAROMETER_INT",
717
+
"ACC_COVER_OPEN",
718
+
"TS_INT_N",
719
+
"NC",
720
+
"NC",
721
+
"USB_DETECT_EN",
722
+
"NC",
723
+
"QLINK_REQUEST", /* GPIO_130 */
724
+
"QLINK_ENABLE",
725
+
"NC",
726
+
"NC",
727
+
"WMSS_RESET_N",
728
+
"PA_INDICATOR_OR",
729
+
"NC",
730
+
"RFFE3_DATA",
731
+
"RFFE3_CLK",
732
+
"RFFE4_DATA",
733
+
"RFFE4_CLK", /* GPIO_140 */
734
+
"RFFE5_DATA",
735
+
"RFFE5_CLK",
736
+
"GNSS_EN",
737
+
"MSS_LTE_COXM_TXD",
738
+
"MSS_LTE_COXM_RXD",
739
+
"RFFE2_DATA",
740
+
"RFFE2_CLK",
741
+
"RFFE1_DATA",
742
+
"RFFE1_CLK";
641
743
642
-
mdp_vsync_n: mdp-vsync-n-state {
744
+
mdp_vsync_p: mdp-vsync-p-state {
643
745
pins = "gpio10";
644
746
function = "mdp_vsync_a";
645
747
drive-strength = <2>;
···
804
606
output-low;
805
607
};
806
608
807
-
msm_mclk0_default: msm-mclk0-active-state {
609
+
cam_mclk0_active: cam-mclk0-active-state {
808
610
pins = "gpio13";
809
611
function = "cam_mclk";
810
612
drive-strength = <2>;
811
613
bias-disable;
812
614
};
813
615
814
-
msm_mclk1_default: msm-mclk1-active-state {
616
+
cam_mclk1_active: cam-mclk1-active-state {
815
617
pins = "gpio14";
816
618
function = "cam_mclk";
817
619
drive-strength = <2>;
···
832
634
drive-strength = <2>;
833
635
};
834
636
835
-
cam0_vdig_default: cam0-vdig-default-state {
637
+
main_cam_pwr_en: main-cam-pwr-en-default-state {
836
638
pins = "gpio21";
837
639
function = "gpio";
838
640
bias-disable;
839
641
drive-strength = <2>;
840
642
};
841
643
842
-
tof_int: tof-int-state {
644
+
tof_int_n: tof-int-n-state {
843
645
pins = "gpio22";
844
646
function = "gpio";
845
647
bias-pull-up;
···
847
649
input-enable;
848
650
};
849
651
850
-
cam1_vdig_default: cam1-vdig-default-state {
652
+
chat_cam_pwr_en: chat-cam-pwr-en-default-state {
851
653
pins = "gpio25";
852
654
function = "gpio";
853
655
bias-disable;
854
656
drive-strength = <2>;
855
-
};
856
-
857
-
usb_extcon_active: usb-extcon-active-state {
858
-
pins = "gpio38";
859
-
function = "gpio";
860
-
bias-disable;
861
-
drive-strength = <16>;
862
657
};
863
658
864
659
tof_reset: tof-reset-state {
···
861
670
drive-strength = <2>;
862
671
};
863
672
864
-
hall_sensor0_default: acc-cover-open-state {
673
+
cc_dir_default: cc-dir-active-state {
674
+
pins = "gpio38";
675
+
function = "gpio";
676
+
bias-disable;
677
+
drive-strength = <16>;
678
+
};
679
+
680
+
acc_cover_open: acc-cover-open-state {
865
681
pins = "gpio124";
866
682
function = "gpio";
867
683
bias-disable;
···
883
685
bias-pull-up;
884
686
};
885
687
886
-
usb_vbus_active: usb-vbus-active-state {
688
+
usb_detect_en: usb-detect-en-active-state {
887
689
pins = "gpio128";
888
690
function = "gpio";
889
691
bias-disable;
+2
-3
arch/arm64/boot/dts/qcom/msm8998.dtsi
+2
-3
arch/arm64/boot/dts/qcom/msm8998.dtsi
···
922
922
phy-names = "pciephy";
923
923
status = "disabled";
924
924
925
-
ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>,
925
+
ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>,
926
926
<0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
927
927
928
928
#interrupt-cells = <1>;
···
1524
1524
compatible = "arm,coresight-stm", "arm,primecell";
1525
1525
reg = <0x06002000 0x1000>,
1526
1526
<0x16280000 0x180000>;
1527
-
reg-names = "stm-base", "stm-data-base";
1527
+
reg-names = "stm-base", "stm-stimulus-base";
1528
1528
status = "disabled";
1529
1529
1530
1530
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
···
1993
1993
#size-cells = <0>;
1994
1994
interrupt-controller;
1995
1995
#interrupt-cells = <4>;
1996
-
cell-index = <0>;
1997
1996
};
1998
1997
1999
1998
usb3: usb@a8f8800 {
+1
-1
arch/arm64/boot/dts/qcom/pm660.dtsi
+1
-1
arch/arm64/boot/dts/qcom/pm660.dtsi
+1
-1
arch/arm64/boot/dts/qcom/pm660l.dtsi
+1
-1
arch/arm64/boot/dts/qcom/pm660l.dtsi
+6
arch/arm64/boot/dts/qcom/pm8150l.dtsi
+6
arch/arm64/boot/dts/qcom/pm8150l.dtsi
···
116
116
#address-cells = <1>;
117
117
#size-cells = <0>;
118
118
119
+
pm8150l_flash: led-controller@d300 {
120
+
compatible = "qcom,pm8150l-flash-led", "qcom,spmi-flash-led";
121
+
reg = <0xd300>;
122
+
status = "disabled";
123
+
};
124
+
119
125
pm8150l_lpg: pwm {
120
126
compatible = "qcom,pm8150l-lpg";
121
127
+6
arch/arm64/boot/dts/qcom/pm8550b.dtsi
+6
arch/arm64/boot/dts/qcom/pm8550b.dtsi
+1
-1
arch/arm64/boot/dts/qcom/pm8998.dtsi
+1
-1
arch/arm64/boot/dts/qcom/pm8998.dtsi
-2
arch/arm64/boot/dts/qcom/pmi8994.dtsi
-2
arch/arm64/boot/dts/qcom/pmi8994.dtsi
+2
-2
arch/arm64/boot/dts/qcom/qcs404.dtsi
+2
-2
arch/arm64/boot/dts/qcom/qcs404.dtsi
···
1469
1469
#address-cells = <3>;
1470
1470
#size-cells = <2>;
1471
1471
1472
-
ranges = <0x81000000 0 0 0x10003000 0 0x00010000>, /* I/O */
1473
-
<0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */
1472
+
ranges = <0x81000000 0x0 0x00000000 0x10003000 0x0 0x00010000>, /* I/O */
1473
+
<0x82000000 0x0 0x10013000 0x10013000 0x0 0x007ed000>; /* memory */
1474
1474
1475
1475
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1476
1476
interrupt-names = "msi";
+17
-4
arch/arm64/boot/dts/qcom/qdu1000.dtsi
+17
-4
arch/arm64/boot/dts/qcom/qdu1000.dtsi
···
27
27
device_type = "cpu";
28
28
compatible = "arm,cortex-a55";
29
29
reg = <0x0 0x0>;
30
+
clocks = <&cpufreq_hw 0>;
30
31
enable-method = "psci";
31
32
power-domains = <&CPU_PD0>;
32
33
power-domain-names = "psci";
···
46
45
device_type = "cpu";
47
46
compatible = "arm,cortex-a55";
48
47
reg = <0x0 0x100>;
48
+
clocks = <&cpufreq_hw 0>;
49
49
enable-method = "psci";
50
50
power-domains = <&CPU_PD1>;
51
51
power-domain-names = "psci";
···
62
60
device_type = "cpu";
63
61
compatible = "arm,cortex-a55";
64
62
reg = <0x0 0x200>;
63
+
clocks = <&cpufreq_hw 0>;
65
64
enable-method = "psci";
66
65
power-domains = <&CPU_PD2>;
67
66
power-domain-names = "psci";
···
78
75
device_type = "cpu";
79
76
compatible = "arm,cortex-a55";
80
77
reg = <0x0 0x300>;
78
+
clocks = <&cpufreq_hw 0>;
81
79
enable-method = "psci";
82
80
power-domains = <&CPU_PD3>;
83
81
power-domain-names = "psci";
···
416
412
pinctrl-0 = <&qup_uart0_default>;
417
413
pinctrl-names = "default";
418
414
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
419
-
#address-cells = <1>;
420
-
#size-cells = <0>;
421
415
status = "disabled";
422
416
};
423
417
···
583
581
pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
584
582
pinctrl-names = "default";
585
583
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
586
-
#address-cells = <1>;
587
-
#size-cells = <0>;
588
584
status = "disabled";
589
585
};
590
586
};
···
1312
1312
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
1313
1313
clock-names = "xo", "alternate";
1314
1314
#freq-domain-cells = <1>;
1315
+
#clock-cells = <1>;
1315
1316
};
1316
1317
1317
1318
gem_noc: interconnect@19100000 {
···
1320
1319
reg = <0x0 0x19100000 0x0 0xB8080>;
1321
1320
qcom,bcm-voters = <&apps_bcm_voter>;
1322
1321
#interconnect-cells = <2>;
1322
+
};
1323
+
1324
+
system-cache-controller@19200000 {
1325
+
compatible = "qcom,qdu1000-llcc";
1326
+
reg = <0 0x19200000 0 0xd80000>,
1327
+
<0 0x1a200000 0 0x80000>,
1328
+
<0 0x221c8128 0 0x4>;
1329
+
reg-names = "llcc_base",
1330
+
"llcc_broadcast_base",
1331
+
"multi_channel_register";
1332
+
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1333
+
multi-ch-bit-off = <24 2>;
1323
1334
};
1324
1335
};
1325
1336
+2
-2
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
+2
-2
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
···
1012
1012
left_spkr: speaker@0,3 {
1013
1013
compatible = "sdw10217211000";
1014
1014
reg = <0 3>;
1015
-
powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_HIGH>;
1015
+
powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>;
1016
1016
#thermal-sensor-cells = <0>;
1017
1017
sound-name-prefix = "SpkrLeft";
1018
1018
#sound-dai-cells = <0>;
···
1021
1021
right_spkr: speaker@0,4 {
1022
1022
compatible = "sdw10217211000";
1023
1023
reg = <0 4>;
1024
-
powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_HIGH>;
1024
+
powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>;
1025
1025
#thermal-sensor-cells = <0>;
1026
1026
sound-name-prefix = "SpkrRight";
1027
1027
#sound-dai-cells = <0>;
+5
arch/arm64/boot/dts/qcom/sa8155p-adp.dts
+5
arch/arm64/boot/dts/qcom/sa8155p-adp.dts
+1
-1
arch/arm64/boot/dts/qcom/sa8540p-ride.dts
+1
-1
arch/arm64/boot/dts/qcom/sa8540p-ride.dts
+211
arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi
+211
arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi
···
1
+
// SPDX-License-Identifier: BSD-3-Clause
2
+
/*
3
+
* Copyright (c) 2023, Linaro Limited
4
+
*/
5
+
6
+
#include <dt-bindings/input/input.h>
7
+
#include <dt-bindings/spmi/spmi.h>
8
+
9
+
/ {
10
+
thermal-zones {
11
+
pmm8654au_0_thermal: pm8775-0-thermal {
12
+
polling-delay-passive = <100>;
13
+
polling-delay = <0>;
14
+
thermal-sensors = <&pmm8654au_0_temp_alarm>;
15
+
16
+
trips {
17
+
trip0 {
18
+
temperature = <105000>;
19
+
hysteresis = <0>;
20
+
type = "passive";
21
+
};
22
+
23
+
trip1 {
24
+
temperature = <125000>;
25
+
hysteresis = <0>;
26
+
type = "critical";
27
+
};
28
+
};
29
+
};
30
+
31
+
pmm8654au_1_thermal: pm8775-1-thermal {
32
+
polling-delay-passive = <100>;
33
+
polling-delay = <0>;
34
+
thermal-sensors = <&pmm8654au_1_temp_alarm>;
35
+
36
+
trips {
37
+
trip0 {
38
+
temperature = <105000>;
39
+
hysteresis = <0>;
40
+
type = "passive";
41
+
};
42
+
43
+
trip1 {
44
+
temperature = <125000>;
45
+
hysteresis = <0>;
46
+
type = "critical";
47
+
};
48
+
};
49
+
};
50
+
51
+
pmm8654au_2_thermal: pm8775-2-thermal {
52
+
polling-delay-passive = <100>;
53
+
polling-delay = <0>;
54
+
thermal-sensors = <&pmm8654au_2_temp_alarm>;
55
+
56
+
trips {
57
+
trip0 {
58
+
temperature = <105000>;
59
+
hysteresis = <0>;
60
+
type = "passive";
61
+
};
62
+
63
+
trip1 {
64
+
temperature = <125000>;
65
+
hysteresis = <0>;
66
+
type = "critical";
67
+
};
68
+
};
69
+
};
70
+
71
+
pmm8654au_3_thermal: pm8775-3-thermal {
72
+
polling-delay-passive = <100>;
73
+
polling-delay = <0>;
74
+
thermal-sensors = <&pmm8654au_3_temp_alarm>;
75
+
76
+
trips {
77
+
trip0 {
78
+
temperature = <105000>;
79
+
hysteresis = <0>;
80
+
type = "passive";
81
+
};
82
+
83
+
trip1 {
84
+
temperature = <125000>;
85
+
hysteresis = <0>;
86
+
type = "critical";
87
+
};
88
+
};
89
+
};
90
+
};
91
+
};
92
+
93
+
&spmi_bus {
94
+
pmm8654au_0: pmic@0 {
95
+
compatible = "qcom,pmm8654au", "qcom,spmi-pmic";
96
+
reg = <0x0 SPMI_USID>;
97
+
#address-cells = <1>;
98
+
#size-cells = <0>;
99
+
100
+
pmm8654au_0_temp_alarm: temp-alarm@a00 {
101
+
compatible = "qcom,spmi-temp-alarm";
102
+
reg = <0xa00>;
103
+
interrupts-extended = <&spmi_bus 0x0 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
104
+
#thermal-sensor-cells = <0>;
105
+
};
106
+
107
+
pmm8654au_0_pon: pon@1200 {
108
+
compatible = "qcom,pmk8350-pon";
109
+
reg = <0x1200>, <0x800>;
110
+
reg-names = "hlos", "pbs";
111
+
mode-recovery = <0x1>;
112
+
mode-bootloader = <0x2>;
113
+
114
+
pmm8654au_0_pon_pwrkey: pwrkey {
115
+
compatible = "qcom,pmk8350-pwrkey";
116
+
interrupts-extended = <&spmi_bus 0x0 0x12 0x7 IRQ_TYPE_EDGE_BOTH>;
117
+
linux,code = <KEY_POWER>;
118
+
debounce = <15625>;
119
+
};
120
+
121
+
pmm8654au_0_pon_resin: resin {
122
+
compatible = "qcom,pmk8350-resin";
123
+
interrupts-extended = <&spmi_bus 0x0 0x12 0x6 IRQ_TYPE_EDGE_BOTH>;
124
+
debounce = <15625>;
125
+
status = "disabled";
126
+
};
127
+
};
128
+
129
+
pmm8654au_0_gpios: gpio@8800 {
130
+
compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio";
131
+
reg = <0x8800>;
132
+
gpio-controller;
133
+
gpio-ranges = <&pmm8654au_0_gpios 0 0 12>;
134
+
#gpio-cells = <2>;
135
+
interrupt-controller;
136
+
#interrupt-cells = <2>;
137
+
};
138
+
};
139
+
140
+
pmm8654au_1: pmic@2 {
141
+
compatible = "qcom,pmm8654au", "qcom,spmi-pmic";
142
+
reg = <0x2 SPMI_USID>;
143
+
#address-cells = <1>;
144
+
#size-cells = <0>;
145
+
146
+
pmm8654au_1_temp_alarm: temp-alarm@a00 {
147
+
compatible = "qcom,spmi-temp-alarm";
148
+
reg = <0xa00>;
149
+
interrupts-extended = <&spmi_bus 0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
150
+
#thermal-sensor-cells = <0>;
151
+
};
152
+
153
+
pmm8654au_1_gpios: gpio@8800 {
154
+
compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio";
155
+
reg = <0x8800>;
156
+
gpio-controller;
157
+
gpio-ranges = <&pmm8654au_2_gpios 0 0 12>;
158
+
#gpio-cells = <2>;
159
+
interrupt-controller;
160
+
#interrupt-cells = <2>;
161
+
};
162
+
};
163
+
164
+
pmm8654au_2: pmic@4 {
165
+
compatible = "qcom,pmm8654au", "qcom,spmi-pmic";
166
+
reg = <0x4 SPMI_USID>;
167
+
#address-cells = <1>;
168
+
#size-cells = <0>;
169
+
170
+
pmm8654au_2_temp_alarm: temp-alarm@a00 {
171
+
compatible = "qcom,spmi-temp-alarm";
172
+
reg = <0xa00>;
173
+
interrupts-extended = <&spmi_bus 0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
174
+
#thermal-sensor-cells = <0>;
175
+
};
176
+
177
+
pmm8654au_2_gpios: gpio@8800 {
178
+
compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio";
179
+
reg = <0x8800>;
180
+
gpio-controller;
181
+
gpio-ranges = <&pmm8654au_2_gpios 0 0 12>;
182
+
#gpio-cells = <2>;
183
+
interrupt-controller;
184
+
#interrupt-cells = <2>;
185
+
};
186
+
};
187
+
188
+
pmm8654au_3: pmic@6 {
189
+
compatible = "qcom,pmm8654au", "qcom,spmi-pmic";
190
+
reg = <0x6 SPMI_USID>;
191
+
#address-cells = <1>;
192
+
#size-cells = <0>;
193
+
194
+
pmm8654au_3_temp_alarm: temp-alarm@a00 {
195
+
compatible = "qcom,spmi-temp-alarm";
196
+
reg = <0xa00>;
197
+
interrupts-extended = <&spmi_bus 0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
198
+
#thermal-sensor-cells = <0>;
199
+
};
200
+
201
+
pmm8654au_3_gpios: gpio@8800 {
202
+
compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio";
203
+
reg = <0x8800>;
204
+
gpio-controller;
205
+
gpio-ranges = <&pmm8654au_3_gpios 0 0 12>;
206
+
#gpio-cells = <2>;
207
+
interrupt-controller;
208
+
#interrupt-cells = <2>;
209
+
};
210
+
};
211
+
};
+198
arch/arm64/boot/dts/qcom/sa8775p-ride.dts
+198
arch/arm64/boot/dts/qcom/sa8775p-ride.dts
···
1
+
// SPDX-License-Identifier: BSD-3-Clause
2
+
/*
3
+
* Copyright (c) 2023, Linaro Limited
4
+
*/
5
+
6
+
/dts-v1/;
7
+
8
+
#include "sa8775p.dtsi"
9
+
#include "sa8775p-pmics.dtsi"
10
+
11
+
/ {
12
+
model = "Qualcomm SA8775P Ride";
13
+
compatible = "qcom,sa8775p-ride", "qcom,sa8775p";
14
+
15
+
aliases {
16
+
serial0 = &uart10;
17
+
serial1 = &uart12;
18
+
serial2 = &uart17;
19
+
i2c18 = &i2c18;
20
+
spi16 = &spi16;
21
+
};
22
+
23
+
chosen {
24
+
stdout-path = "serial0:115200n8";
25
+
};
26
+
};
27
+
28
+
&i2c18 {
29
+
clock-frequency = <400000>;
30
+
pinctrl-0 = <&qup_i2c18_default>;
31
+
pinctrl-names = "default";
32
+
status = "okay";
33
+
};
34
+
35
+
&pmm8654au_0_gpios {
36
+
gpio-line-names = "DS_EN",
37
+
"POFF_COMPLETE",
38
+
"UFS0_VER_ID",
39
+
"FAST_POFF",
40
+
"DBU1_PON_DONE",
41
+
"AOSS_SLEEP",
42
+
"CAM_DES0_EN",
43
+
"CAM_DES1_EN",
44
+
"CAM_DES2_EN",
45
+
"CAM_DES3_EN",
46
+
"UEFI",
47
+
"ANALOG_PON_OPT";
48
+
};
49
+
50
+
&pmm8654au_1_gpios {
51
+
gpio-line-names = "PMIC_C_ID0",
52
+
"PMIC_C_ID1",
53
+
"UFS1_VER_ID",
54
+
"IPA_PWR",
55
+
"",
56
+
"WLAN_DBU4_EN",
57
+
"WLAN_EN",
58
+
"BT_EN",
59
+
"USB2_PWR_EN",
60
+
"USB2_FAULT";
61
+
};
62
+
63
+
&pmm8654au_2_gpios {
64
+
gpio-line-names = "PMIC_E_ID0",
65
+
"PMIC_E_ID1",
66
+
"USB0_PWR_EN",
67
+
"USB0_FAULT",
68
+
"SENSOR_IRQ_1",
69
+
"SENSOR_IRQ_2",
70
+
"SENSOR_RST",
71
+
"SGMIIO0_RST",
72
+
"SGMIIO1_RST",
73
+
"USB1_PWR_ENABLE",
74
+
"USB1_FAULT",
75
+
"VMON_SPX8";
76
+
};
77
+
78
+
&pmm8654au_3_gpios {
79
+
gpio-line-names = "PMIC_G_ID0",
80
+
"PMIC_G_ID1",
81
+
"GNSS_RST",
82
+
"GNSS_EN",
83
+
"GNSS_BOOT_MODE";
84
+
};
85
+
86
+
&qupv3_id_1 {
87
+
status = "okay";
88
+
};
89
+
90
+
&qupv3_id_2 {
91
+
status = "okay";
92
+
};
93
+
94
+
&sleep_clk {
95
+
clock-frequency = <32764>;
96
+
};
97
+
98
+
&spi16 {
99
+
pinctrl-0 = <&qup_spi16_default>;
100
+
pinctrl-names = "default";
101
+
status = "okay";
102
+
};
103
+
104
+
&tlmm {
105
+
qup_uart10_default: qup-uart10-state {
106
+
pins = "gpio46", "gpio47";
107
+
function = "qup1_se3";
108
+
};
109
+
110
+
qup_spi16_default: qup-spi16-state {
111
+
pins = "gpio86", "gpio87", "gpio88", "gpio89";
112
+
function = "qup2_se2";
113
+
drive-strength = <6>;
114
+
bias-disable;
115
+
};
116
+
117
+
qup_i2c18_default: qup-i2c18-state {
118
+
pins = "gpio95", "gpio96";
119
+
function = "qup2_se4";
120
+
drive-strength = <2>;
121
+
bias-pull-up;
122
+
};
123
+
124
+
qup_uart12_default: qup-uart12-state {
125
+
qup_uart12_cts: qup-uart12-cts-pins {
126
+
pins = "gpio52";
127
+
function = "qup1_se5";
128
+
bias-disable;
129
+
};
130
+
131
+
qup_uart12_rts: qup-uart12-rts-pins {
132
+
pins = "gpio53";
133
+
function = "qup1_se5";
134
+
bias-pull-down;
135
+
};
136
+
137
+
qup_uart12_tx: qup-uart12-tx-pins {
138
+
pins = "gpio54";
139
+
function = "qup1_se5";
140
+
bias-pull-up;
141
+
};
142
+
143
+
qup_uart12_rx: qup-uart12-rx-pins {
144
+
pins = "gpio55";
145
+
function = "qup1_se5";
146
+
bias-pull-down;
147
+
};
148
+
};
149
+
150
+
qup_uart17_default: qup-uart17-state {
151
+
qup_uart17_cts: qup-uart17-cts-pins {
152
+
pins = "gpio91";
153
+
function = "qup2_se3";
154
+
bias-disable;
155
+
};
156
+
157
+
qup_uart17_rts: qup0-uart17-rts-pins {
158
+
pins = "gpio92";
159
+
function = "qup2_se3";
160
+
bias-pull-down;
161
+
};
162
+
163
+
qup_uart17_tx: qup0-uart17-tx-pins {
164
+
pins = "gpio93";
165
+
function = "qup2_se3";
166
+
bias-pull-up;
167
+
};
168
+
169
+
qup_uart17_rx: qup0-uart17-rx-pins {
170
+
pins = "gpio94";
171
+
function = "qup2_se3";
172
+
bias-pull-down;
173
+
};
174
+
};
175
+
};
176
+
177
+
&uart10 {
178
+
compatible = "qcom,geni-debug-uart";
179
+
pinctrl-0 = <&qup_uart10_default>;
180
+
pinctrl-names = "default";
181
+
status = "okay";
182
+
};
183
+
184
+
&uart12 {
185
+
pinctrl-0 = <&qup_uart12_default>;
186
+
pinctrl-names = "default";
187
+
status = "okay";
188
+
};
189
+
190
+
&uart17 {
191
+
pinctrl-0 = <&qup_uart17_default>;
192
+
pinctrl-names = "default";
193
+
status = "okay";
194
+
};
195
+
196
+
&xo_board_clk {
197
+
clock-frequency = <38400000>;
198
+
};
+981
arch/arm64/boot/dts/qcom/sa8775p.dtsi
+981
arch/arm64/boot/dts/qcom/sa8775p.dtsi
···
1
+
// SPDX-License-Identifier: BSD-3-Clause
2
+
/*
3
+
* Copyright (c) 2023, Linaro Limited
4
+
*/
5
+
6
+
#include <dt-bindings/interconnect/qcom,icc.h>
7
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
8
+
#include <dt-bindings/clock/qcom,rpmh.h>
9
+
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
10
+
#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
11
+
#include <dt-bindings/power/qcom-rpmpd.h>
12
+
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
13
+
14
+
/ {
15
+
interrupt-parent = <&intc>;
16
+
17
+
#address-cells = <2>;
18
+
#size-cells = <2>;
19
+
20
+
clocks {
21
+
xo_board_clk: xo-board-clk {
22
+
compatible = "fixed-clock";
23
+
#clock-cells = <0>;
24
+
};
25
+
26
+
sleep_clk: sleep-clk {
27
+
compatible = "fixed-clock";
28
+
#clock-cells = <0>;
29
+
};
30
+
};
31
+
32
+
cpus {
33
+
#address-cells = <2>;
34
+
#size-cells = <0>;
35
+
36
+
CPU0: cpu@0 {
37
+
device_type = "cpu";
38
+
compatible = "qcom,kryo";
39
+
reg = <0x0 0x0>;
40
+
enable-method = "psci";
41
+
qcom,freq-domain = <&cpufreq_hw 0>;
42
+
next-level-cache = <&L2_0>;
43
+
L2_0: l2-cache {
44
+
compatible = "cache";
45
+
next-level-cache = <&L3_0>;
46
+
L3_0: l3-cache {
47
+
compatible = "cache";
48
+
};
49
+
};
50
+
};
51
+
52
+
CPU1: cpu@100 {
53
+
device_type = "cpu";
54
+
compatible = "qcom,kryo";
55
+
reg = <0x0 0x100>;
56
+
enable-method = "psci";
57
+
qcom,freq-domain = <&cpufreq_hw 0>;
58
+
next-level-cache = <&L2_1>;
59
+
L2_1: l2-cache {
60
+
compatible = "cache";
61
+
next-level-cache = <&L3_0>;
62
+
};
63
+
};
64
+
65
+
CPU2: cpu@200 {
66
+
device_type = "cpu";
67
+
compatible = "qcom,kryo";
68
+
reg = <0x0 0x200>;
69
+
enable-method = "psci";
70
+
qcom,freq-domain = <&cpufreq_hw 0>;
71
+
next-level-cache = <&L2_2>;
72
+
L2_2: l2-cache {
73
+
compatible = "cache";
74
+
next-level-cache = <&L3_0>;
75
+
};
76
+
};
77
+
78
+
CPU3: cpu@300 {
79
+
device_type = "cpu";
80
+
compatible = "qcom,kryo";
81
+
reg = <0x0 0x300>;
82
+
enable-method = "psci";
83
+
qcom,freq-domain = <&cpufreq_hw 0>;
84
+
next-level-cache = <&L2_3>;
85
+
L2_3: l2-cache {
86
+
compatible = "cache";
87
+
next-level-cache = <&L3_0>;
88
+
};
89
+
};
90
+
91
+
CPU4: cpu@10000 {
92
+
device_type = "cpu";
93
+
compatible = "qcom,kryo";
94
+
reg = <0x0 0x10000>;
95
+
enable-method = "psci";
96
+
qcom,freq-domain = <&cpufreq_hw 1>;
97
+
next-level-cache = <&L2_4>;
98
+
L2_4: l2-cache {
99
+
compatible = "cache";
100
+
next-level-cache = <&L3_1>;
101
+
L3_1: l3-cache {
102
+
compatible = "cache";
103
+
};
104
+
105
+
};
106
+
};
107
+
108
+
CPU5: cpu@10100 {
109
+
device_type = "cpu";
110
+
compatible = "qcom,kryo";
111
+
reg = <0x0 0x10100>;
112
+
enable-method = "psci";
113
+
qcom,freq-domain = <&cpufreq_hw 1>;
114
+
next-level-cache = <&L2_5>;
115
+
L2_5: l2-cache {
116
+
compatible = "cache";
117
+
next-level-cache = <&L3_1>;
118
+
};
119
+
};
120
+
121
+
CPU6: cpu@10200 {
122
+
device_type = "cpu";
123
+
compatible = "qcom,kryo";
124
+
reg = <0x0 0x10200>;
125
+
enable-method = "psci";
126
+
qcom,freq-domain = <&cpufreq_hw 1>;
127
+
next-level-cache = <&L2_6>;
128
+
L2_6: l2-cache {
129
+
compatible = "cache";
130
+
next-level-cache = <&L3_1>;
131
+
};
132
+
};
133
+
134
+
CPU7: cpu@10300 {
135
+
device_type = "cpu";
136
+
compatible = "qcom,kryo";
137
+
reg = <0x0 0x10300>;
138
+
enable-method = "psci";
139
+
qcom,freq-domain = <&cpufreq_hw 1>;
140
+
next-level-cache = <&L2_7>;
141
+
L2_7: l2-cache {
142
+
compatible = "cache";
143
+
next-level-cache = <&L3_1>;
144
+
};
145
+
};
146
+
147
+
cpu-map {
148
+
cluster0 {
149
+
core0 {
150
+
cpu = <&CPU0>;
151
+
};
152
+
153
+
core1 {
154
+
cpu = <&CPU1>;
155
+
};
156
+
157
+
core2 {
158
+
cpu = <&CPU2>;
159
+
};
160
+
161
+
core3 {
162
+
cpu = <&CPU3>;
163
+
};
164
+
};
165
+
166
+
cluster1 {
167
+
core0 {
168
+
cpu = <&CPU4>;
169
+
};
170
+
171
+
core1 {
172
+
cpu = <&CPU5>;
173
+
};
174
+
175
+
core2 {
176
+
cpu = <&CPU6>;
177
+
};
178
+
179
+
core3 {
180
+
cpu = <&CPU7>;
181
+
};
182
+
};
183
+
};
184
+
};
185
+
186
+
firmware {
187
+
scm {
188
+
compatible = "qcom,scm-sa8775p", "qcom,scm";
189
+
};
190
+
};
191
+
192
+
aggre1_noc: interconnect-aggre1-noc {
193
+
compatible = "qcom,sa8775p-aggre1-noc";
194
+
#interconnect-cells = <2>;
195
+
qcom,bcm-voters = <&apps_bcm_voter>;
196
+
};
197
+
198
+
aggre2_noc: interconnect-aggre2-noc {
199
+
compatible = "qcom,sa8775p-aggre2-noc";
200
+
#interconnect-cells = <2>;
201
+
qcom,bcm-voters = <&apps_bcm_voter>;
202
+
};
203
+
204
+
clk_virt: interconnect-clk-virt {
205
+
compatible = "qcom,sa8775p-clk-virt";
206
+
#interconnect-cells = <2>;
207
+
qcom,bcm-voters = <&apps_bcm_voter>;
208
+
};
209
+
210
+
config_noc: interconnect-config-noc {
211
+
compatible = "qcom,sa8775p-config-noc";
212
+
#interconnect-cells = <2>;
213
+
qcom,bcm-voters = <&apps_bcm_voter>;
214
+
};
215
+
216
+
dc_noc: interconnect-dc-noc {
217
+
compatible = "qcom,sa8775p-dc-noc";
218
+
#interconnect-cells = <2>;
219
+
qcom,bcm-voters = <&apps_bcm_voter>;
220
+
};
221
+
222
+
gem_noc: interconnect-gem-noc {
223
+
compatible = "qcom,sa8775p-gem-noc";
224
+
#interconnect-cells = <2>;
225
+
qcom,bcm-voters = <&apps_bcm_voter>;
226
+
};
227
+
228
+
gpdsp_anoc: interconnect-gpdsp-anoc {
229
+
compatible = "qcom,sa8775p-gpdsp-anoc";
230
+
#interconnect-cells = <2>;
231
+
qcom,bcm-voters = <&apps_bcm_voter>;
232
+
};
233
+
234
+
lpass_ag_noc: interconnect-lpass-ag-noc {
235
+
compatible = "qcom,sa8775p-lpass-ag-noc";
236
+
#interconnect-cells = <2>;
237
+
qcom,bcm-voters = <&apps_bcm_voter>;
238
+
};
239
+
240
+
mc_virt: interconnect-mc-virt {
241
+
compatible = "qcom,sa8775p-mc-virt";
242
+
#interconnect-cells = <2>;
243
+
qcom,bcm-voters = <&apps_bcm_voter>;
244
+
};
245
+
246
+
mmss_noc: interconnect-mmss-noc {
247
+
compatible = "qcom,sa8775p-mmss-noc";
248
+
#interconnect-cells = <2>;
249
+
qcom,bcm-voters = <&apps_bcm_voter>;
250
+
};
251
+
252
+
nspa_noc: interconnect-nspa-noc {
253
+
compatible = "qcom,sa8775p-nspa-noc";
254
+
#interconnect-cells = <2>;
255
+
qcom,bcm-voters = <&apps_bcm_voter>;
256
+
};
257
+
258
+
nspb_noc: interconnect-nspb-noc {
259
+
compatible = "qcom,sa8775p-nspb-noc";
260
+
#interconnect-cells = <2>;
261
+
qcom,bcm-voters = <&apps_bcm_voter>;
262
+
};
263
+
264
+
pcie_anoc: interconnect-pcie-anoc {
265
+
compatible = "qcom,sa8775p-pcie-anoc";
266
+
#interconnect-cells = <2>;
267
+
qcom,bcm-voters = <&apps_bcm_voter>;
268
+
};
269
+
270
+
system_noc: interconnect-system-noc {
271
+
compatible = "qcom,sa8775p-system-noc";
272
+
#interconnect-cells = <2>;
273
+
qcom,bcm-voters = <&apps_bcm_voter>;
274
+
};
275
+
276
+
/* Will be updated by the bootloader. */
277
+
memory@80000000 {
278
+
device_type = "memory";
279
+
reg = <0x0 0x80000000 0x0 0x0>;
280
+
};
281
+
282
+
qup_opp_table_100mhz: opp-table-qup100mhz {
283
+
compatible = "operating-points-v2";
284
+
285
+
opp-100000000 {
286
+
opp-hz = /bits/ 64 <100000000>;
287
+
required-opps = <&rpmhpd_opp_svs_l1>;
288
+
};
289
+
};
290
+
291
+
psci {
292
+
compatible = "arm,psci-1.0";
293
+
method = "smc";
294
+
};
295
+
296
+
reserved-memory {
297
+
#address-cells = <2>;
298
+
#size-cells = <2>;
299
+
ranges;
300
+
301
+
sail_ss_mem: sail-ss@80000000 {
302
+
reg = <0x0 0x80000000 0x0 0x10000000>;
303
+
no-map;
304
+
};
305
+
306
+
hyp_mem: hyp@90000000 {
307
+
reg = <0x0 0x90000000 0x0 0x600000>;
308
+
no-map;
309
+
};
310
+
311
+
xbl_boot_mem: xbl-boot@90600000 {
312
+
reg = <0x0 0x90600000 0x0 0x200000>;
313
+
no-map;
314
+
};
315
+
316
+
aop_image_mem: aop-image@90800000 {
317
+
reg = <0x0 0x90800000 0x0 0x60000>;
318
+
no-map;
319
+
};
320
+
321
+
aop_cmd_db_mem: aop-cmd-db@90860000 {
322
+
compatible = "qcom,cmd-db";
323
+
reg = <0x0 0x90860000 0x0 0x20000>;
324
+
no-map;
325
+
};
326
+
327
+
uefi_log: uefi-log@908b0000 {
328
+
reg = <0x0 0x908b0000 0x0 0x10000>;
329
+
no-map;
330
+
};
331
+
332
+
reserved_mem: reserved@908f0000 {
333
+
reg = <0x0 0x908f0000 0x0 0xf000>;
334
+
no-map;
335
+
};
336
+
337
+
secdata_apss_mem: secdata-apss@908ff000 {
338
+
reg = <0x0 0x908ff000 0x0 0x1000>;
339
+
no-map;
340
+
};
341
+
342
+
smem_mem: smem@90900000 {
343
+
compatible = "qcom,smem";
344
+
reg = <0x0 0x90900000 0x0 0x200000>;
345
+
no-map;
346
+
hwlocks = <&tcsr_mutex 3>;
347
+
};
348
+
349
+
cpucp_fw_mem: cpucp-fw@90b00000 {
350
+
reg = <0x0 0x90b00000 0x0 0x100000>;
351
+
no-map;
352
+
};
353
+
354
+
lpass_machine_learning_mem: lpass-machine-learning@93b00000 {
355
+
reg = <0x0 0x93b00000 0x0 0xf00000>;
356
+
no-map;
357
+
};
358
+
359
+
adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 {
360
+
reg = <0x0 0x94a00000 0x0 0x800000>;
361
+
no-map;
362
+
};
363
+
364
+
pil_camera_mem: pil-camera@95200000 {
365
+
reg = <0x0 0x95200000 0x0 0x500000>;
366
+
no-map;
367
+
};
368
+
369
+
pil_adsp_mem: pil-adsp@95c00000 {
370
+
reg = <0x0 0x95c00000 0x0 0x1e00000>;
371
+
no-map;
372
+
};
373
+
374
+
pil_gdsp0_mem: pil-gdsp0@97b00000 {
375
+
reg = <0x0 0x97b00000 0x0 0x1e00000>;
376
+
no-map;
377
+
};
378
+
379
+
pil_gdsp1_mem: pil-gdsp1@99900000 {
380
+
reg = <0x0 0x99900000 0x0 0x1e00000>;
381
+
no-map;
382
+
};
383
+
384
+
pil_cdsp0_mem: pil-cdsp0@9b800000 {
385
+
reg = <0x0 0x9b800000 0x0 0x1e00000>;
386
+
no-map;
387
+
};
388
+
389
+
pil_gpu_mem: pil-gpu@9d600000 {
390
+
reg = <0x0 0x9d600000 0x0 0x2000>;
391
+
no-map;
392
+
};
393
+
394
+
pil_cdsp1_mem: pil-cdsp1@9d700000 {
395
+
reg = <0x0 0x9d700000 0x0 0x1e00000>;
396
+
no-map;
397
+
};
398
+
399
+
pil_cvp_mem: pil-cvp@9f500000 {
400
+
reg = <0x0 0x9f500000 0x0 0x700000>;
401
+
no-map;
402
+
};
403
+
404
+
pil_video_mem: pil-video@9fc00000 {
405
+
reg = <0x0 0x9fc00000 0x0 0x700000>;
406
+
no-map;
407
+
};
408
+
409
+
hyptz_reserved_mem: hyptz-reserved@beb00000 {
410
+
reg = <0x0 0xbeb00000 0x0 0x11500000>;
411
+
no-map;
412
+
};
413
+
414
+
tz_stat_mem: tz-stat@d0000000 {
415
+
reg = <0x0 0xd0000000 0x0 0x100000>;
416
+
no-map;
417
+
};
418
+
419
+
tags_mem: tags@d0100000 {
420
+
reg = <0x0 0xd0100000 0x0 0x1200000>;
421
+
no-map;
422
+
};
423
+
424
+
qtee_mem: qtee@d1300000 {
425
+
reg = <0x0 0xd1300000 0x0 0x500000>;
426
+
no-map;
427
+
};
428
+
429
+
trusted_apps_mem: trusted-apps@d1800000 {
430
+
reg = <0x0 0xd1800000 0x0 0x3900000>;
431
+
no-map;
432
+
};
433
+
};
434
+
435
+
soc: soc@0 {
436
+
compatible = "simple-bus";
437
+
#address-cells = <2>;
438
+
#size-cells = <2>;
439
+
ranges = <0 0 0 0 0x10 0>;
440
+
441
+
gcc: clock-controller@100000 {
442
+
compatible = "qcom,sa8775p-gcc";
443
+
reg = <0x0 0x00100000 0x0 0xc7018>;
444
+
#clock-cells = <1>;
445
+
#reset-cells = <1>;
446
+
#power-domain-cells = <1>;
447
+
clocks = <&rpmhcc RPMH_CXO_CLK>,
448
+
<&sleep_clk>,
449
+
<0>,
450
+
<0>,
451
+
<0>,
452
+
<0>,
453
+
<0>,
454
+
<0>,
455
+
<0>,
456
+
<0>,
457
+
<0>,
458
+
<0>,
459
+
<0>,
460
+
<0>,
461
+
<0>;
462
+
power-domains = <&rpmhpd SA8775P_CX>;
463
+
};
464
+
465
+
ipcc: mailbox@408000 {
466
+
compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";
467
+
reg = <0x0 0x00408000 0x0 0x1000>;
468
+
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
469
+
interrupt-controller;
470
+
#interrupt-cells = <3>;
471
+
#mbox-cells = <2>;
472
+
};
473
+
474
+
qupv3_id_2: geniqup@8c0000 {
475
+
compatible = "qcom,geni-se-qup";
476
+
reg = <0x0 0x008c0000 0x0 0x6000>;
477
+
ranges;
478
+
clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
479
+
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
480
+
clock-names = "m-ahb", "s-ahb";
481
+
iommus = <&apps_smmu 0x5a3 0x0>;
482
+
#address-cells = <2>;
483
+
#size-cells = <2>;
484
+
status = "disabled";
485
+
486
+
spi16: spi@888000 {
487
+
compatible = "qcom,geni-spi";
488
+
reg = <0x0 0x00888000 0x0 0x4000>;
489
+
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
490
+
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
491
+
clock-names = "se";
492
+
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
493
+
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
494
+
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
495
+
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
496
+
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
497
+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
498
+
interconnect-names = "qup-core",
499
+
"qup-config",
500
+
"qup-memory";
501
+
power-domains = <&rpmhpd SA8775P_CX>;
502
+
#address-cells = <1>;
503
+
#size-cells = <0>;
504
+
status = "disabled";
505
+
};
506
+
507
+
uart17: serial@88c000 {
508
+
compatible = "qcom,geni-uart";
509
+
reg = <0x0 0x0088c000 0x0 0x4000>;
510
+
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
511
+
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
512
+
clock-names = "se";
513
+
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
514
+
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
515
+
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
516
+
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
517
+
interconnect-names = "qup-core", "qup-config";
518
+
power-domains = <&rpmhpd SA8775P_CX>;
519
+
status = "disabled";
520
+
};
521
+
522
+
i2c18: i2c@890000 {
523
+
compatible = "qcom,geni-i2c";
524
+
reg = <0x0 0x00890000 0x0 0x4000>;
525
+
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
526
+
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
527
+
clock-names = "se";
528
+
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
529
+
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
530
+
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
531
+
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
532
+
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
533
+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
534
+
interconnect-names = "qup-core",
535
+
"qup-config",
536
+
"qup-memory";
537
+
power-domains = <&rpmhpd SA8775P_CX>;
538
+
#address-cells = <1>;
539
+
#size-cells = <0>;
540
+
status = "disabled";
541
+
};
542
+
};
543
+
544
+
qupv3_id_1: geniqup@ac0000 {
545
+
compatible = "qcom,geni-se-qup";
546
+
reg = <0x0 0x00ac0000 0x0 0x6000>;
547
+
#address-cells = <2>;
548
+
#size-cells = <2>;
549
+
ranges;
550
+
clock-names = "m-ahb", "s-ahb";
551
+
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
552
+
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
553
+
iommus = <&apps_smmu 0x443 0x0>;
554
+
status = "disabled";
555
+
556
+
uart10: serial@a8c000 {
557
+
compatible = "qcom,geni-uart";
558
+
reg = <0x0 0x00a8c000 0x0 0x4000>;
559
+
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
560
+
clock-names = "se";
561
+
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
562
+
interconnect-names = "qup-core", "qup-config";
563
+
interconnects = <&clk_virt MASTER_QUP_CORE_1 0
564
+
&clk_virt SLAVE_QUP_CORE_1 0>,
565
+
<&gem_noc MASTER_APPSS_PROC 0
566
+
&config_noc SLAVE_QUP_1 0>;
567
+
power-domains = <&rpmhpd SA8775P_CX>;
568
+
operating-points-v2 = <&qup_opp_table_100mhz>;
569
+
status = "disabled";
570
+
};
571
+
572
+
uart12: serial@a94000 {
573
+
compatible = "qcom,geni-uart";
574
+
reg = <0x0 0x00a94000 0x0 0x4000>;
575
+
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
576
+
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
577
+
clock-names = "se";
578
+
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
579
+
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
580
+
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
581
+
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
582
+
interconnect-names = "qup-core", "qup-config";
583
+
power-domains = <&rpmhpd SA8775P_CX>;
584
+
status = "disabled";
585
+
};
586
+
};
587
+
588
+
tcsr_mutex: hwlock@1f40000 {
589
+
compatible = "qcom,tcsr-mutex";
590
+
reg = <0x0 0x01f40000 0x0 0x20000>;
591
+
#hwlock-cells = <1>;
592
+
};
593
+
594
+
pdc: interrupt-controller@b220000 {
595
+
compatible = "qcom,sa8775p-pdc", "qcom,pdc";
596
+
reg = <0x0 0x0b220000 0x0 0x30000>,
597
+
<0x0 0x17c000f0 0x0 0x64>;
598
+
qcom,pdc-ranges = <0 480 40>,
599
+
<40 140 14>,
600
+
<54 263 1>,
601
+
<55 306 4>,
602
+
<59 312 3>,
603
+
<62 374 2>,
604
+
<64 434 2>,
605
+
<66 438 2>,
606
+
<70 520 1>,
607
+
<73 523 1>,
608
+
<118 568 6>,
609
+
<124 609 3>,
610
+
<159 638 1>,
611
+
<160 720 3>,
612
+
<169 728 30>,
613
+
<199 416 2>,
614
+
<201 449 1>,
615
+
<202 89 1>,
616
+
<203 451 1>,
617
+
<204 462 1>,
618
+
<205 264 1>,
619
+
<206 579 1>,
620
+
<207 653 1>,
621
+
<208 656 1>,
622
+
<209 659 1>,
623
+
<210 122 1>,
624
+
<211 699 1>,
625
+
<212 705 1>,
626
+
<213 450 1>,
627
+
<214 643 2>,
628
+
<216 646 5>,
629
+
<221 390 5>,
630
+
<226 700 2>,
631
+
<228 440 1>,
632
+
<229 663 1>,
633
+
<230 524 2>,
634
+
<232 612 3>,
635
+
<235 723 5>;
636
+
#interrupt-cells = <2>;
637
+
interrupt-parent = <&intc>;
638
+
interrupt-controller;
639
+
};
640
+
641
+
spmi_bus: spmi@c440000 {
642
+
compatible = "qcom,spmi-pmic-arb";
643
+
reg = <0x0 0x0c440000 0x0 0x1100>,
644
+
<0x0 0x0c600000 0x0 0x2000000>,
645
+
<0x0 0x0e600000 0x0 0x100000>,
646
+
<0x0 0x0e700000 0x0 0xa0000>,
647
+
<0x0 0x0c40a000 0x0 0x26000>;
648
+
reg-names = "core",
649
+
"chnls",
650
+
"obsrvr",
651
+
"intr",
652
+
"cnfg";
653
+
qcom,channel = <0>;
654
+
qcom,ee = <0>;
655
+
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
656
+
interrupt-names = "periph_irq";
657
+
interrupt-controller;
658
+
#interrupt-cells = <4>;
659
+
#address-cells = <2>;
660
+
#size-cells = <0>;
661
+
};
662
+
663
+
tlmm: pinctrl@f000000 {
664
+
compatible = "qcom,sa8775p-tlmm";
665
+
reg = <0x0 0x0f000000 0x0 0x1000000>;
666
+
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
667
+
gpio-controller;
668
+
#gpio-cells = <2>;
669
+
interrupt-controller;
670
+
#interrupt-cells = <2>;
671
+
gpio-ranges = <&tlmm 0 0 149>;
672
+
};
673
+
674
+
apps_smmu: iommu@15000000 {
675
+
compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
676
+
reg = <0x0 0x15000000 0x0 0x100000>;
677
+
#iommu-cells = <2>;
678
+
#global-interrupts = <2>;
679
+
680
+
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
681
+
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
682
+
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
683
+
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
684
+
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
685
+
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
686
+
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
687
+
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
688
+
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
689
+
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
690
+
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
691
+
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
692
+
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
693
+
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
694
+
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
695
+
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
696
+
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
697
+
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
698
+
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
699
+
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
700
+
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
701
+
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
702
+
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
703
+
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
704
+
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
705
+
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
706
+
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
707
+
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
708
+
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
709
+
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
710
+
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
711
+
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
712
+
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
713
+
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
714
+
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
715
+
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
716
+
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
717
+
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
718
+
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
719
+
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
720
+
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
721
+
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
722
+
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
723
+
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
724
+
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
725
+
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
726
+
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
727
+
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
728
+
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
729
+
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
730
+
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
731
+
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
732
+
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
733
+
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
734
+
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
735
+
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
736
+
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
737
+
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
738
+
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
739
+
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
740
+
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
741
+
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
742
+
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
743
+
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
744
+
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
745
+
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
746
+
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
747
+
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
748
+
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
749
+
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
750
+
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
751
+
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
752
+
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
753
+
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
754
+
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
755
+
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
756
+
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
757
+
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
758
+
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
759
+
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
760
+
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
761
+
<GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
762
+
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
763
+
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
764
+
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
765
+
<GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
766
+
<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
767
+
<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
768
+
<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
769
+
<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
770
+
<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
771
+
<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
772
+
<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
773
+
<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
774
+
<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
775
+
<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
776
+
<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
777
+
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
778
+
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
779
+
<GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
780
+
<GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
781
+
<GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
782
+
<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
783
+
<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
784
+
<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
785
+
<GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
786
+
<GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
787
+
<GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
788
+
<GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
789
+
<GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
790
+
<GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
791
+
<GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
792
+
<GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
793
+
<GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
794
+
<GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
795
+
<GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
796
+
<GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
797
+
<GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
798
+
<GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
799
+
<GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
800
+
<GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
801
+
<GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
802
+
<GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
803
+
<GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
804
+
<GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
805
+
<GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
806
+
<GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
807
+
<GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
808
+
<GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
809
+
<GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
810
+
};
811
+
812
+
intc: interrupt-controller@17a00000 {
813
+
compatible = "arm,gic-v3";
814
+
reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
815
+
<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
816
+
interrupt-controller;
817
+
#interrupt-cells = <3>;
818
+
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
819
+
#redistributor-regions = <1>;
820
+
redistributor-stride = <0x0 0x20000>;
821
+
};
822
+
823
+
memtimer: timer@17c20000 {
824
+
compatible = "arm,armv7-timer-mem";
825
+
reg = <0x0 0x17c20000 0x0 0x1000>;
826
+
ranges = <0x0 0x0 0x0 0x20000000>;
827
+
#address-cells = <1>;
828
+
#size-cells = <1>;
829
+
830
+
frame@17c21000 {
831
+
reg = <0x17c21000 0x1000>,
832
+
<0x17c22000 0x1000>;
833
+
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
834
+
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
835
+
frame-number = <0>;
836
+
};
837
+
838
+
frame@17c23000 {
839
+
reg = <0x17c23000 0x1000>;
840
+
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
841
+
frame-number = <1>;
842
+
status = "disabled";
843
+
};
844
+
845
+
frame@17c25000 {
846
+
reg = <0x17c25000 0x1000>;
847
+
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
848
+
frame-number = <2>;
849
+
status = "disabled";
850
+
};
851
+
852
+
frame@17c27000 {
853
+
reg = <0x17c27000 0x1000>;
854
+
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
855
+
frame-number = <3>;
856
+
status = "disabled";
857
+
};
858
+
859
+
frame@17c29000 {
860
+
reg = <0x17c29000 0x1000>;
861
+
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
862
+
frame-number = <4>;
863
+
status = "disabled";
864
+
};
865
+
866
+
frame@17c2b000 {
867
+
reg = <0x17c2b000 0x1000>;
868
+
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
869
+
frame-number = <5>;
870
+
status = "disabled";
871
+
};
872
+
873
+
frame@17c2d000 {
874
+
reg = <0x17c2d000 0x1000>;
875
+
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
876
+
frame-number = <6>;
877
+
status = "disabled";
878
+
};
879
+
};
880
+
881
+
apps_rsc: rsc@18200000 {
882
+
compatible = "qcom,rpmh-rsc";
883
+
reg = <0x0 0x18200000 0x0 0x10000>,
884
+
<0x0 0x18210000 0x0 0x10000>,
885
+
<0x0 0x18220000 0x0 0x10000>;
886
+
reg-names = "drv-0", "drv-1", "drv-2";
887
+
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
888
+
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
889
+
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
890
+
qcom,tcs-offset = <0xd00>;
891
+
qcom,drv-id = <2>;
892
+
qcom,tcs-config = <ACTIVE_TCS 2>,
893
+
<SLEEP_TCS 3>,
894
+
<WAKE_TCS 3>,
895
+
<CONTROL_TCS 0>;
896
+
label = "apps_rsc";
897
+
898
+
apps_bcm_voter: bcm-voter {
899
+
compatible = "qcom,bcm-voter";
900
+
};
901
+
902
+
rpmhcc: clock-controller {
903
+
compatible = "qcom,sa8775p-rpmh-clk";
904
+
#clock-cells = <1>;
905
+
clock-names = "xo";
906
+
clocks = <&xo_board_clk>;
907
+
};
908
+
909
+
rpmhpd: power-controller {
910
+
compatible = "qcom,sa8775p-rpmhpd";
911
+
#power-domain-cells = <1>;
912
+
operating-points-v2 = <&rpmhpd_opp_table>;
913
+
914
+
rpmhpd_opp_table: opp-table {
915
+
compatible = "operating-points-v2";
916
+
917
+
rpmhpd_opp_ret: opp-0 {
918
+
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
919
+
};
920
+
921
+
rpmhpd_opp_min_svs: opp-1 {
922
+
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
923
+
};
924
+
925
+
rpmhpd_opp_low_svs: opp2 {
926
+
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
927
+
};
928
+
929
+
rpmhpd_opp_svs: opp3 {
930
+
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
931
+
};
932
+
933
+
rpmhpd_opp_svs_l1: opp-4 {
934
+
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
935
+
};
936
+
937
+
rpmhpd_opp_nom: opp-5 {
938
+
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
939
+
};
940
+
941
+
rpmhpd_opp_nom_l1: opp-6 {
942
+
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
943
+
};
944
+
945
+
rpmhpd_opp_nom_l2: opp-7 {
946
+
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
947
+
};
948
+
949
+
rpmhpd_opp_turbo: opp-8 {
950
+
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
951
+
};
952
+
953
+
rpmhpd_opp_turbo_l1: opp-9 {
954
+
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
955
+
};
956
+
};
957
+
};
958
+
};
959
+
960
+
cpufreq_hw: cpufreq@18591000 {
961
+
compatible = "qcom,sa8775p-cpufreq-epss",
962
+
"qcom,cpufreq-epss";
963
+
reg = <0x0 0x18591000 0x0 0x1000>,
964
+
<0x0 0x18593000 0x0 0x1000>;
965
+
reg-names = "freq-domain0", "freq-domain1";
966
+
967
+
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
968
+
clock-names = "xo", "alternate";
969
+
970
+
#freq-domain-cells = <1>;
971
+
};
972
+
};
973
+
974
+
arch_timer: timer {
975
+
compatible = "arm,armv8-timer";
976
+
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
977
+
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
978
+
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
979
+
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
980
+
};
981
+
};
+3
-8
arch/arm64/boot/dts/qcom/sc7180-idp.dts
+3
-8
arch/arm64/boot/dts/qcom/sc7180-idp.dts
···
312
312
313
313
reset-gpios = <&pm6150l_gpios 3 GPIO_ACTIVE_HIGH>;
314
314
315
-
ports {
316
-
#address-cells = <1>;
317
-
#size-cells = <0>;
318
-
port@0 {
319
-
reg = <0>;
320
-
panel0_in: endpoint {
321
-
remote-endpoint = <&dsi0_out>;
322
-
};
315
+
port {
316
+
panel0_in: endpoint {
317
+
remote-endpoint = <&dsi0_out>;
323
318
};
324
319
};
325
320
};
-38
arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts
-38
arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts
···
1
-
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
-
/*
3
-
* Google Kingoftown board device tree source
4
-
*
5
-
* Copyright 2021 Google LLC.
6
-
*/
7
-
8
-
/dts-v1/;
9
-
10
-
#include "sc7180-trogdor.dtsi"
11
-
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
12
-
#include "sc7180-trogdor-kingoftown.dtsi"
13
-
14
-
/ {
15
-
model = "Google Kingoftown (rev0)";
16
-
compatible = "google,kingoftown-rev0", "qcom,sc7180";
17
-
};
18
-
19
-
/*
20
-
* In rev1+, the enable pin of pp3300_fp_tp will be tied to pp1800_l10a
21
-
* power rail instead, since kingoftown does not have FP.
22
-
*/
23
-
&pp3300_fp_tp {
24
-
gpio = <&tlmm 74 GPIO_ACTIVE_HIGH>;
25
-
enable-active-high;
26
-
27
-
pinctrl-names = "default";
28
-
pinctrl-0 = <&en_fp_rails>;
29
-
};
30
-
31
-
&tlmm {
32
-
en_fp_rails: en-fp-rails-state {
33
-
pins = "gpio74";
34
-
function = "gpio";
35
-
drive-strength = <2>;
36
-
bias-disable;
37
-
};
38
-
};
-17
arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r1.dts
-17
arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r1.dts
···
1
-
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
-
/*
3
-
* Google Kingoftown board device tree source
4
-
*
5
-
* Copyright 2021 Google LLC.
6
-
*/
7
-
8
-
/dts-v1/;
9
-
10
-
#include "sc7180-trogdor.dtsi"
11
-
#include "sc7180-trogdor-parade-ps8640.dtsi"
12
-
#include "sc7180-trogdor-kingoftown.dtsi"
13
-
14
-
/ {
15
-
model = "Google Kingoftown (rev1+)";
16
-
compatible = "google,kingoftown", "qcom,sc7180";
17
-
};
+9
-1
arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi
arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts
+9
-1
arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi
arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts
···
5
5
* Copyright 2021 Google LLC.
6
6
*/
7
7
8
-
/* This file must be included after sc7180-trogdor.dtsi */
8
+
/dts-v1/;
9
+
10
+
#include "sc7180-trogdor.dtsi"
11
+
#include "sc7180-trogdor-parade-ps8640.dtsi"
9
12
#include <arm/cros-ec-keyboard.dtsi>
10
13
#include "sc7180-trogdor-lte-sku.dtsi"
14
+
15
+
/ {
16
+
model = "Google Kingoftown";
17
+
compatible = "google,kingoftown", "qcom,sc7180";
18
+
};
11
19
12
20
&alc5682 {
13
21
compatible = "realtek,rt5682s";
+1
-1
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dts
+1
-1
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dts
+1
-1
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts
+1
-1
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts
-34
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts
-34
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts
···
1
-
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
-
/*
3
-
* Google Lazor board device tree source
4
-
*
5
-
* Copyright 2020 Google LLC.
6
-
*/
7
-
8
-
/dts-v1/;
9
-
10
-
#include "sc7180-trogdor.dtsi"
11
-
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
12
-
#include "sc7180-trogdor-lazor.dtsi"
13
-
14
-
/ {
15
-
model = "Google Lazor (rev0)";
16
-
compatible = "google,lazor-rev0", "qcom,sc7180";
17
-
};
18
-
19
-
&sn65dsi86_out {
20
-
/*
21
-
* Lane 0 was incorrectly mapped on the cable, but we've now decided
22
-
* that the cable is canon and in -rev1+ we'll make a board change
23
-
* that means we no longer need the swizzle.
24
-
*/
25
-
lane-polarities = <1 0>;
26
-
};
27
-
28
-
&usb_hub_2_x {
29
-
vdd-supply = <&pp3300_l7c>;
30
-
};
31
-
32
-
&usb_hub_3_x {
33
-
vdd-supply = <&pp3300_l7c>;
34
-
};
-22
arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-auo.dts
-22
arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-auo.dts
···
1
-
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
-
/*
3
-
* Google Mrbland board device tree source
4
-
*
5
-
* Copyright 2021 Google LLC.
6
-
*
7
-
* SKU: 0x0 => 0
8
-
* - bits 7..4: Panel ID: 0x0 (AUO)
9
-
*/
10
-
11
-
/dts-v1/;
12
-
13
-
#include "sc7180-trogdor-mrbland-rev0.dtsi"
14
-
15
-
/ {
16
-
model = "Google Mrbland rev0 AUO panel board";
17
-
compatible = "google,mrbland-rev0-sku0", "qcom,sc7180";
18
-
};
19
-
20
-
&panel {
21
-
compatible = "auo,b101uan08.3";
22
-
};
-22
arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-boe.dts
-22
arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-boe.dts
···
1
-
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
-
/*
3
-
* Google Mrbland board device tree source
4
-
*
5
-
* Copyright 2021 Google LLC.
6
-
*
7
-
* SKU: 0x10 => 16
8
-
* - bits 7..4: Panel ID: 0x1 (BOE)
9
-
*/
10
-
11
-
/dts-v1/;
12
-
13
-
#include "sc7180-trogdor-mrbland-rev0.dtsi"
14
-
15
-
/ {
16
-
model = "Google Mrbland rev0 BOE panel board";
17
-
compatible = "google,mrbland-rev0-sku16", "qcom,sc7180";
18
-
};
19
-
20
-
&panel {
21
-
compatible = "boe,tv101wum-n53";
22
-
};
-36
arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi
-36
arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi
···
1
-
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
-
/*
3
-
* Google Mrbland board device tree source
4
-
*
5
-
* Copyright 2021 Google LLC.
6
-
*
7
-
*/
8
-
9
-
/dts-v1/;
10
-
11
-
#include "sc7180-trogdor-mrbland.dtsi"
12
-
13
-
&avdd_lcd {
14
-
gpio = <&tlmm 80 GPIO_ACTIVE_HIGH>;
15
-
};
16
-
17
-
&panel {
18
-
enable-gpios = <&tlmm 76 GPIO_ACTIVE_HIGH>;
19
-
};
20
-
21
-
&v1p8_mipi {
22
-
gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>;
23
-
};
24
-
25
-
/* PINCTRL - modifications to sc7180-trogdor-mrbland.dtsi */
26
-
&avdd_lcd_en {
27
-
pins = "gpio80";
28
-
};
29
-
30
-
&mipi_1800_en {
31
-
pins = "gpio81";
32
-
};
33
-
34
-
&vdd_reset_1800 {
35
-
pins = "gpio76";
36
-
};
-22
arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-auo.dts
-22
arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-auo.dts
···
1
-
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
-
/*
3
-
* Google Mrbland board device tree source
4
-
*
5
-
* Copyright 2021 Google LLC.
6
-
*
7
-
* SKU: 0x600 => 1536
8
-
* - bits 11..8: Panel ID: 0x6 (AUO)
9
-
*/
10
-
11
-
/dts-v1/;
12
-
13
-
#include "sc7180-trogdor-mrbland.dtsi"
14
-
15
-
/ {
16
-
model = "Google Mrbland rev1+ AUO panel board";
17
-
compatible = "google,mrbland-sku1536", "qcom,sc7180";
18
-
};
19
-
20
-
&panel {
21
-
compatible = "auo,b101uan08.3";
22
-
};
-24
arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-boe.dts
-24
arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-boe.dts
···
1
-
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
-
/*
3
-
* Google Mrbland board device tree source
4
-
*
5
-
* Copyright 2021 Google LLC.
6
-
*
7
-
* SKU: 0x300 => 768
8
-
* - bits 11..8: Panel ID: 0x3 (BOE)
9
-
*/
10
-
11
-
/dts-v1/;
12
-
13
-
#include "sc7180-trogdor-mrbland.dtsi"
14
-
15
-
/ {
16
-
model = "Google Mrbland (rev1 - 2) BOE panel board";
17
-
/* Uses ID 768 on rev1 and 1024 on rev2+ */
18
-
compatible = "google,mrbland-sku1024", "google,mrbland-sku768",
19
-
"qcom,sc7180";
20
-
};
21
-
22
-
&panel {
23
-
compatible = "boe,tv101wum-n53";
24
-
};
-320
arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi
-320
arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi
···
1
-
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
-
/*
3
-
* Google Mrbland board device tree source
4
-
*
5
-
* Copyright 2021 Google LLC.
6
-
*/
7
-
8
-
/dts-v1/;
9
-
10
-
#include "sc7180-trogdor.dtsi"
11
-
12
-
/* This board only has 1 USB Type-C port. */
13
-
/delete-node/ &usb_c1;
14
-
15
-
/ {
16
-
avdd_lcd: avdd-lcd-regulator {
17
-
compatible = "regulator-fixed";
18
-
regulator-name = "avdd_lcd";
19
-
20
-
gpio = <&tlmm 88 GPIO_ACTIVE_HIGH>;
21
-
enable-active-high;
22
-
pinctrl-names = "default";
23
-
pinctrl-0 = <&avdd_lcd_en>;
24
-
25
-
vin-supply = <&pp5000_a>;
26
-
};
27
-
28
-
avee_lcd: avee-lcd-regulator {
29
-
compatible = "regulator-fixed";
30
-
regulator-name = "avee_lcd";
31
-
32
-
gpio = <&tlmm 21 GPIO_ACTIVE_HIGH>;
33
-
enable-active-high;
34
-
pinctrl-names = "default";
35
-
pinctrl-0 = <&avee_lcd_en>;
36
-
37
-
vin-supply = <&pp5000_a>;
38
-
};
39
-
40
-
v1p8_mipi: v1p8-mipi-regulator {
41
-
compatible = "regulator-fixed";
42
-
regulator-name = "v1p8_mipi";
43
-
44
-
gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>;
45
-
enable-active-high;
46
-
pinctrl-names = "default";
47
-
pinctrl-0 = <&mipi_1800_en>;
48
-
49
-
vin-supply = <&pp3300_a>;
50
-
};
51
-
};
52
-
53
-
&backlight {
54
-
pwms = <&cros_ec_pwm 0>;
55
-
};
56
-
57
-
&camcc {
58
-
status = "okay";
59
-
};
60
-
61
-
&cros_ec {
62
-
keyboard-controller {
63
-
compatible = "google,cros-ec-keyb-switches";
64
-
};
65
-
};
66
-
67
-
&dsi0 {
68
-
69
-
panel: panel@0 {
70
-
/* Compatible will be filled in per-board */
71
-
reg = <0>;
72
-
enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
73
-
pinctrl-names = "default";
74
-
pinctrl-0 = <&vdd_reset_1800>;
75
-
avdd-supply = <&avdd_lcd>;
76
-
avee-supply = <&avee_lcd>;
77
-
pp1800-supply = <&v1p8_mipi>;
78
-
pp3300-supply = <&pp3300_dx_edp>;
79
-
backlight = <&backlight>;
80
-
rotation = <270>;
81
-
82
-
ports {
83
-
#address-cells = <1>;
84
-
#size-cells = <0>;
85
-
port@0 {
86
-
reg = <0>;
87
-
panel_in: endpoint {
88
-
remote-endpoint = <&dsi0_out>;
89
-
};
90
-
};
91
-
};
92
-
};
93
-
94
-
ports {
95
-
port@1 {
96
-
endpoint {
97
-
remote-endpoint = <&panel_in>;
98
-
data-lanes = <0 1 2 3>;
99
-
};
100
-
};
101
-
};
102
-
};
103
-
104
-
&gpio_keys {
105
-
status = "okay";
106
-
};
107
-
108
-
&i2c4 {
109
-
status = "okay";
110
-
clock-frequency = <400000>;
111
-
112
-
ap_ts: touchscreen@5d {
113
-
compatible = "goodix,gt7375p";
114
-
reg = <0x5d>;
115
-
pinctrl-names = "default";
116
-
pinctrl-0 = <&ts_int_l>, <&ts_reset_l>;
117
-
118
-
interrupt-parent = <&tlmm>;
119
-
interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
120
-
121
-
reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>;
122
-
123
-
vdd-supply = <&pp3300_ts>;
124
-
};
125
-
};
126
-
127
-
&pp1800_uf_cam {
128
-
status = "okay";
129
-
};
130
-
131
-
&pp1800_wf_cam {
132
-
status = "okay";
133
-
};
134
-
135
-
&pp2800_uf_cam {
136
-
status = "okay";
137
-
};
138
-
139
-
&pp2800_wf_cam {
140
-
status = "okay";
141
-
};
142
-
143
-
&wifi {
144
-
qcom,ath10k-calibration-variant = "GO_MRBLAND";
145
-
};
146
-
147
-
/*
148
-
* No eDP on this board but it's logically the same signal so just give it
149
-
* a new name and assign the proper GPIO.
150
-
*/
151
-
pp3300_disp_on: &pp3300_dx_edp {
152
-
gpio = <&tlmm 85 GPIO_ACTIVE_HIGH>;
153
-
};
154
-
155
-
/* PINCTRL - modifications to sc7180-trogdor.dtsi */
156
-
157
-
/*
158
-
* No eDP on this board but it's logically the same signal so just give it
159
-
* a new name and assign the proper GPIO.
160
-
*/
161
-
162
-
tp_en: &en_pp3300_dx_edp {
163
-
pins = "gpio85";
164
-
};
165
-
166
-
/* PINCTRL - board-specific pinctrl */
167
-
168
-
&tlmm {
169
-
gpio-line-names = "HUB_RST_L",
170
-
"AP_RAM_ID0",
171
-
"AP_SKU_ID2",
172
-
"AP_RAM_ID1",
173
-
"",
174
-
"AP_RAM_ID2",
175
-
"UF_CAM_EN",
176
-
"WF_CAM_EN",
177
-
"TS_RESET_L",
178
-
"TS_INT_L",
179
-
"",
180
-
"",
181
-
"AP_EDP_BKLTEN",
182
-
"UF_CAM_MCLK",
183
-
"WF_CAM_CLK",
184
-
"",
185
-
"",
186
-
"UF_CAM_SDA",
187
-
"UF_CAM_SCL",
188
-
"WF_CAM_SDA",
189
-
"WF_CAM_SCL",
190
-
"AVEE_LCD_EN",
191
-
"",
192
-
"AMP_EN",
193
-
"",
194
-
"",
195
-
"",
196
-
"",
197
-
"HP_IRQ",
198
-
"WF_CAM_RST_L",
199
-
"UF_CAM_RST_L",
200
-
"AP_BRD_ID2",
201
-
"",
202
-
"AP_BRD_ID0",
203
-
"AP_H1_SPI_MISO",
204
-
"AP_H1_SPI_MOSI",
205
-
"AP_H1_SPI_CLK",
206
-
"AP_H1_SPI_CS_L",
207
-
"BT_UART_CTS",
208
-
"BT_UART_RTS",
209
-
"BT_UART_TXD",
210
-
"BT_UART_RXD",
211
-
"H1_AP_INT_ODL",
212
-
"",
213
-
"UART_AP_TX_DBG_RX",
214
-
"UART_DBG_TX_AP_RX",
215
-
"HP_I2C_SDA",
216
-
"HP_I2C_SCL",
217
-
"FORCED_USB_BOOT",
218
-
"AMP_BCLK",
219
-
"AMP_LRCLK",
220
-
"AMP_DIN",
221
-
"PEN_DET_ODL",
222
-
"HP_BCLK",
223
-
"HP_LRCLK",
224
-
"HP_DOUT",
225
-
"HP_DIN",
226
-
"HP_MCLK",
227
-
"AP_SKU_ID0",
228
-
"AP_EC_SPI_MISO",
229
-
"AP_EC_SPI_MOSI",
230
-
"AP_EC_SPI_CLK",
231
-
"AP_EC_SPI_CS_L",
232
-
"AP_SPI_CLK",
233
-
"AP_SPI_MOSI",
234
-
"AP_SPI_MISO",
235
-
/*
236
-
* AP_FLASH_WP_L is crossystem ABI. Schematics
237
-
* call it BIOS_FLASH_WP_L.
238
-
*/
239
-
"AP_FLASH_WP_L",
240
-
"",
241
-
"AP_SPI_CS0_L",
242
-
"",
243
-
"",
244
-
"",
245
-
"",
246
-
"WLAN_SW_CTRL",
247
-
"",
248
-
"REPORT_E",
249
-
"",
250
-
"ID0",
251
-
"",
252
-
"ID1",
253
-
"",
254
-
"",
255
-
"",
256
-
"CODEC_PWR_EN",
257
-
"HUB_EN",
258
-
"TP_EN",
259
-
"MIPI_1.8V_EN",
260
-
"VDD_RESET_1.8V",
261
-
"AVDD_LCD_EN",
262
-
"",
263
-
"AP_SKU_ID1",
264
-
"AP_RST_REQ",
265
-
"",
266
-
"AP_BRD_ID1",
267
-
"AP_EC_INT_L",
268
-
"SDM_GRFC_3",
269
-
"",
270
-
"",
271
-
"BOOT_CONFIG_4",
272
-
"BOOT_CONFIG_2",
273
-
"",
274
-
"",
275
-
"",
276
-
"",
277
-
"",
278
-
"",
279
-
"",
280
-
"BOOT_CONFIG_3",
281
-
"WCI2_LTE_COEX_TXD",
282
-
"WCI2_LTE_COEX_RXD",
283
-
"",
284
-
"",
285
-
"",
286
-
"",
287
-
"FORCED_USB_BOOT_POL",
288
-
"AP_TS_PEN_I2C_SDA",
289
-
"AP_TS_PEN_I2C_SCL",
290
-
"DP_HOT_PLUG_DET",
291
-
"EC_IN_RW_ODL";
292
-
293
-
avdd_lcd_en: avdd-lcd-en-state {
294
-
pins = "gpio88";
295
-
function = "gpio";
296
-
drive-strength = <2>;
297
-
bias-disable;
298
-
};
299
-
300
-
avee_lcd_en: avee-lcd-en-state {
301
-
pins = "gpio21";
302
-
function = "gpio";
303
-
drive-strength = <2>;
304
-
bias-disable;
305
-
};
306
-
307
-
mipi_1800_en: mipi-1800-en-state {
308
-
pins = "gpio86";
309
-
function = "gpio";
310
-
drive-strength = <2>;
311
-
bias-disable;
312
-
};
313
-
314
-
vdd_reset_1800: vdd-reset-1800-state {
315
-
pins = "gpio87";
316
-
function = "gpio";
317
-
drive-strength = <2>;
318
-
bias-disable;
319
-
};
320
-
};
+1
-1
arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi
+1
-1
arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi
+1
arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi
+1
arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi
+3
-8
arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi
+3
-8
arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi
···
65
65
backlight = <&backlight>;
66
66
rotation = <270>;
67
67
68
-
ports {
69
-
#address-cells = <1>;
70
-
#size-cells = <0>;
71
-
port@0 {
72
-
reg = <0>;
73
-
panel_in: endpoint {
74
-
remote-endpoint = <&dsi0_out>;
75
-
};
68
+
port {
69
+
panel_in: endpoint {
70
+
remote-endpoint = <&dsi0_out>;
76
71
};
77
72
};
78
73
};
-22
arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-boe.dts
-22
arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-boe.dts
···
1
-
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
-
/*
3
-
* Google Wormdingler board device tree source
4
-
*
5
-
* Copyright 2021 Google LLC.
6
-
*
7
-
* SKU: 0x10 => 16
8
-
* - bits 7..4: Panel ID: 0x1 (BOE)
9
-
*/
10
-
11
-
/dts-v1/;
12
-
13
-
#include "sc7180-trogdor-wormdingler-rev0.dtsi"
14
-
15
-
/ {
16
-
model = "Google Wormdingler rev0 BOE panel board";
17
-
compatible = "google,wormdingler-rev0-sku16", "qcom,sc7180";
18
-
};
19
-
20
-
&panel {
21
-
compatible = "boe,tv110c9m-ll3";
22
-
};
-22
arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-inx.dts
-22
arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-inx.dts
···
1
-
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
-
/*
3
-
* Google Wormdingler board device tree source
4
-
*
5
-
* Copyright 2021 Google LLC.
6
-
*
7
-
* SKU: 0x0 => 0
8
-
* - bits 7..4: Panel ID: 0x0 (INX)
9
-
*/
10
-
11
-
/dts-v1/;
12
-
13
-
#include "sc7180-trogdor-wormdingler-rev0.dtsi"
14
-
15
-
/ {
16
-
model = "Google Wormdingler rev0 INX panel board";
17
-
compatible = "google,wormdingler-rev0-sku0", "qcom,sc7180";
18
-
};
19
-
20
-
&panel {
21
-
compatible = "innolux,hj110iz-01a";
22
-
};
-36
arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi
-36
arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi
···
1
-
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
-
/*
3
-
* Google Wormdingler board device tree source
4
-
*
5
-
* Copyright 2021 Google LLC.
6
-
*
7
-
*/
8
-
9
-
/dts-v1/;
10
-
11
-
#include "sc7180-trogdor-wormdingler.dtsi"
12
-
13
-
&avdd_lcd {
14
-
gpio = <&tlmm 80 GPIO_ACTIVE_HIGH>;
15
-
};
16
-
17
-
&panel {
18
-
enable-gpios = <&tlmm 76 GPIO_ACTIVE_HIGH>;
19
-
};
20
-
21
-
&v1p8_mipi {
22
-
gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>;
23
-
};
24
-
25
-
/* PINCTRL - modifications to sc7180-trogdor-wormdingler.dtsi */
26
-
&avdd_lcd_en {
27
-
pins = "gpio80";
28
-
};
29
-
30
-
&mipi_1800_en {
31
-
pins = "gpio81";
32
-
};
33
-
34
-
&vdd_reset_1800 {
35
-
pins = "gpio76";
36
-
};
+3
-8
arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi
+3
-8
arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi
···
124
124
backlight = <&backlight>;
125
125
rotation = <270>;
126
126
127
-
ports {
128
-
#address-cells = <1>;
129
-
#size-cells = <0>;
130
-
port@0 {
131
-
reg = <0>;
132
-
panel_in: endpoint {
133
-
remote-endpoint = <&dsi0_out>;
134
-
};
127
+
port {
128
+
panel_in: endpoint {
129
+
remote-endpoint = <&dsi0_out>;
135
130
};
136
131
};
137
132
};
+11
-4
arch/arm64/boot/dts/qcom/sc7180.dtsi
+11
-4
arch/arm64/boot/dts/qcom/sc7180.dtsi
···
76
76
device_type = "cpu";
77
77
compatible = "qcom,kryo468";
78
78
reg = <0x0 0x0>;
79
+
clocks = <&cpufreq_hw 0>;
79
80
enable-method = "psci";
80
81
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
81
82
&LITTLE_CPU_SLEEP_1
···
104
103
device_type = "cpu";
105
104
compatible = "qcom,kryo468";
106
105
reg = <0x0 0x100>;
106
+
clocks = <&cpufreq_hw 0>;
107
107
enable-method = "psci";
108
108
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
109
109
&LITTLE_CPU_SLEEP_1
···
128
126
device_type = "cpu";
129
127
compatible = "qcom,kryo468";
130
128
reg = <0x0 0x200>;
129
+
clocks = <&cpufreq_hw 0>;
131
130
enable-method = "psci";
132
131
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
133
132
&LITTLE_CPU_SLEEP_1
···
152
149
device_type = "cpu";
153
150
compatible = "qcom,kryo468";
154
151
reg = <0x0 0x300>;
152
+
clocks = <&cpufreq_hw 0>;
155
153
enable-method = "psci";
156
154
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
157
155
&LITTLE_CPU_SLEEP_1
···
176
172
device_type = "cpu";
177
173
compatible = "qcom,kryo468";
178
174
reg = <0x0 0x400>;
175
+
clocks = <&cpufreq_hw 0>;
179
176
enable-method = "psci";
180
177
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
181
178
&LITTLE_CPU_SLEEP_1
···
200
195
device_type = "cpu";
201
196
compatible = "qcom,kryo468";
202
197
reg = <0x0 0x500>;
198
+
clocks = <&cpufreq_hw 0>;
203
199
enable-method = "psci";
204
200
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
205
201
&LITTLE_CPU_SLEEP_1
···
224
218
device_type = "cpu";
225
219
compatible = "qcom,kryo468";
226
220
reg = <0x0 0x600>;
221
+
clocks = <&cpufreq_hw 1>;
227
222
enable-method = "psci";
228
223
cpu-idle-states = <&BIG_CPU_SLEEP_0
229
224
&BIG_CPU_SLEEP_1
···
248
241
device_type = "cpu";
249
242
compatible = "qcom,kryo468";
250
243
reg = <0x0 0x700>;
244
+
clocks = <&cpufreq_hw 1>;
251
245
enable-method = "psci";
252
246
cpu-idle-states = <&BIG_CPU_SLEEP_0
253
247
&BIG_CPU_SLEEP_1
···
2768
2760
system-cache-controller@9200000 {
2769
2761
compatible = "qcom,sc7180-llcc";
2770
2762
reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2771
-
reg-names = "llcc_base", "llcc_broadcast_base";
2763
+
reg-names = "llcc0_base", "llcc_broadcast_base";
2772
2764
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2773
2765
};
2774
2766
···
3027
3019
required-opps = <&rpmhpd_opp_nom>;
3028
3020
};
3029
3021
};
3030
-
3031
3022
};
3032
3023
3033
3024
dsi0: dsi@ae94000 {
···
3287
3280
#size-cells = <0>;
3288
3281
interrupt-controller;
3289
3282
#interrupt-cells = <4>;
3290
-
cell-index = <0>;
3291
3283
};
3292
3284
3293
3285
sram@146aa000 {
···
3576
3570
};
3577
3571
3578
3572
cpufreq_hw: cpufreq@18323000 {
3579
-
compatible = "qcom,cpufreq-hw";
3573
+
compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
3580
3574
reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3581
3575
reg-names = "freq-domain0", "freq-domain1";
3582
3576
···
3584
3578
clock-names = "xo", "alternate";
3585
3579
3586
3580
#freq-domain-cells = <1>;
3581
+
#clock-cells = <1>;
3587
3582
};
3588
3583
3589
3584
wifi: wifi@18800000 {
+1
-1
arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts
+1
-1
arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts
+2
arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi
+2
arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi
+2
arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi
+2
arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi
+1
-1
arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
+1
-1
arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
+1
-1
arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi
+1
-1
arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi
+1
-1
arch/arm64/boot/dts/qcom/sc7280-idp.dts
+1
-1
arch/arm64/boot/dts/qcom/sc7280-idp.dts
+3
-3
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+3
-3
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
···
70
70
gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>;
71
71
linux,input-type = <1>;
72
72
linux,code = <KEY_VOLUMEUP>;
73
-
gpio-key,wakeup;
73
+
wakeup-source;
74
74
debounce-interval = <15>;
75
75
linux,can-disable;
76
76
};
···
184
184
};
185
185
186
186
&apps_rsc {
187
-
pm7325-regulators {
187
+
regulators-0 {
188
188
compatible = "qcom,pm7325-rpmh-regulators";
189
189
qcom,pmic-id = "b";
190
190
···
279
279
};
280
280
};
281
281
282
-
pm8350c-regulators {
282
+
regulators-1 {
283
283
compatible = "qcom,pm8350c-rpmh-regulators";
284
284
qcom,pmic-id = "c";
285
285
+5
-10
arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
+5
-10
arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
···
87
87
* are left out of here since they are managed elsewhere.
88
88
*/
89
89
90
-
pm7325-regulators {
90
+
regulators-0 {
91
91
compatible = "qcom,pm7325-rpmh-regulators";
92
92
qcom,pmic-id = "b";
93
93
···
188
188
};
189
189
};
190
190
191
-
pm8350c-regulators {
191
+
regulators-1 {
192
192
compatible = "qcom,pm8350c-rpmh-regulators";
193
193
qcom,pmic-id = "c";
194
194
···
354
354
355
355
backlight = <&pm8350c_pwm_backlight>;
356
356
357
-
ports {
358
-
#address-cells = <1>;
359
-
#size-cells = <0>;
360
-
port@0 {
361
-
reg = <0>;
362
-
edp_panel_in: endpoint {
363
-
remote-endpoint = <&mdss_edp_out>;
364
-
};
357
+
port {
358
+
edp_panel_in: endpoint {
359
+
remote-endpoint = <&mdss_edp_out>;
365
360
};
366
361
};
367
362
};
+27
-8
arch/arm64/boot/dts/qcom/sc7280.dtsi
+27
-8
arch/arm64/boot/dts/qcom/sc7280.dtsi
···
168
168
device_type = "cpu";
169
169
compatible = "qcom,kryo";
170
170
reg = <0x0 0x0>;
171
+
clocks = <&cpufreq_hw 0>;
171
172
enable-method = "psci";
172
173
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
173
174
&LITTLE_CPU_SLEEP_1
···
194
193
device_type = "cpu";
195
194
compatible = "qcom,kryo";
196
195
reg = <0x0 0x100>;
196
+
clocks = <&cpufreq_hw 0>;
197
197
enable-method = "psci";
198
198
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
199
199
&LITTLE_CPU_SLEEP_1
···
216
214
device_type = "cpu";
217
215
compatible = "qcom,kryo";
218
216
reg = <0x0 0x200>;
217
+
clocks = <&cpufreq_hw 0>;
219
218
enable-method = "psci";
220
219
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
221
220
&LITTLE_CPU_SLEEP_1
···
238
235
device_type = "cpu";
239
236
compatible = "qcom,kryo";
240
237
reg = <0x0 0x300>;
238
+
clocks = <&cpufreq_hw 0>;
241
239
enable-method = "psci";
242
240
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
243
241
&LITTLE_CPU_SLEEP_1
···
260
256
device_type = "cpu";
261
257
compatible = "qcom,kryo";
262
258
reg = <0x0 0x400>;
259
+
clocks = <&cpufreq_hw 1>;
263
260
enable-method = "psci";
264
261
cpu-idle-states = <&BIG_CPU_SLEEP_0
265
262
&BIG_CPU_SLEEP_1
···
282
277
device_type = "cpu";
283
278
compatible = "qcom,kryo";
284
279
reg = <0x0 0x500>;
280
+
clocks = <&cpufreq_hw 1>;
285
281
enable-method = "psci";
286
282
cpu-idle-states = <&BIG_CPU_SLEEP_0
287
283
&BIG_CPU_SLEEP_1
···
304
298
device_type = "cpu";
305
299
compatible = "qcom,kryo";
306
300
reg = <0x0 0x600>;
301
+
clocks = <&cpufreq_hw 1>;
307
302
enable-method = "psci";
308
303
cpu-idle-states = <&BIG_CPU_SLEEP_0
309
304
&BIG_CPU_SLEEP_1
···
326
319
device_type = "cpu";
327
320
compatible = "qcom,kryo";
328
321
reg = <0x0 0x700>;
322
+
clocks = <&cpufreq_hw 2>;
329
323
enable-method = "psci";
330
324
cpu-idle-states = <&BIG_CPU_SLEEP_0
331
325
&BIG_CPU_SLEEP_1
···
943
935
opp-avg-kBps = <390000 0>;
944
936
};
945
937
};
946
-
947
938
};
948
939
949
940
gpi_dma0: dma-controller@900000 {
···
2084
2077
#address-cells = <3>;
2085
2078
#size-cells = <2>;
2086
2079
2087
-
ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
2080
+
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2088
2081
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2089
2082
2090
2083
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
···
2137
2130
2138
2131
pinctrl-names = "default";
2139
2132
pinctrl-0 = <&pcie1_clkreq_n>;
2133
+
2134
+
dma-coherent;
2140
2135
2141
2136
iommus = <&apps_smmu 0x1c80 0x1>;
2142
2137
···
2686
2677
};
2687
2678
2688
2679
adreno_smmu: iommu@3da0000 {
2689
-
compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
2680
+
compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu",
2681
+
"qcom,smmu-500", "arm,mmu-500";
2690
2682
reg = <0 0x03da0000 0 0x20000>;
2691
2683
#iommu-cells = <2>;
2692
2684
#global-interrupts = <2>;
···
3299
3289
opp-avg-kBps = <200000 0>;
3300
3290
};
3301
3291
};
3302
-
3303
3292
};
3304
3293
3305
3294
usb_1_hsphy: phy@88e3000 {
···
3540
3531
};
3541
3532
3542
3533
pmu@90b6400 {
3543
-
compatible = "qcom,sc7280-cpu-bwmon", "qcom,msm8998-bwmon";
3534
+
compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon";
3544
3535
reg = <0 0x090b6400 0 0x600>;
3545
3536
3546
3537
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
···
3591
3582
3592
3583
system-cache-controller@9200000 {
3593
3584
compatible = "qcom,sc7280-llcc";
3594
-
reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>;
3595
-
reg-names = "llcc_base", "llcc_broadcast_base";
3585
+
reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
3586
+
<0 0x09600000 0 0x58000>;
3587
+
reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base";
3596
3588
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
3597
3589
};
3598
3590
···
3603
3593
<0 0x088e2000 0 0x1000>;
3604
3594
interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>;
3605
3595
ports {
3596
+
#address-cells = <1>;
3597
+
#size-cells = <0>;
3598
+
3606
3599
port@0 {
3600
+
reg = <0>;
3607
3601
eud_ep: endpoint {
3608
3602
remote-endpoint = <&usb2_role_switch>;
3609
3603
};
3610
3604
};
3611
3605
port@1 {
3606
+
reg = <1>;
3612
3607
eud_con: endpoint {
3613
3608
remote-endpoint = <&con_eud>;
3614
3609
};
···
3624
3609
eud_typec: connector {
3625
3610
compatible = "usb-c-connector";
3626
3611
ports {
3612
+
#address-cells = <1>;
3613
+
#size-cells = <0>;
3614
+
3627
3615
port@0 {
3616
+
reg = <0>;
3628
3617
con_eud: endpoint {
3629
3618
remote-endpoint = <&eud_con>;
3630
3619
};
···
3767
3748
required-opps = <&rpmhpd_opp_turbo>;
3768
3749
};
3769
3750
};
3770
-
3771
3751
};
3772
3752
3773
3753
videocc: clock-controller@aaf0000 {
···
5355
5337
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5356
5338
clock-names = "xo", "alternate";
5357
5339
#freq-domain-cells = <1>;
5340
+
#clock-cells = <1>;
5358
5341
};
5359
5342
};
5360
5343
+18
-5
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
+18
-5
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
···
413
413
414
414
backlight = <&backlight>;
415
415
416
-
ports {
417
-
port {
418
-
edp_panel_in: endpoint {
419
-
remote-endpoint = <&mdss0_dp3_out>;
420
-
};
416
+
port {
417
+
edp_panel_in: endpoint {
418
+
remote-endpoint = <&mdss0_dp3_out>;
421
419
};
422
420
};
423
421
};
···
559
561
560
562
&pmk8280_pon_pwrkey {
561
563
status = "okay";
564
+
};
565
+
566
+
&pmk8280_rtc {
567
+
nvmem-cells = <&rtc_offset>;
568
+
nvmem-cell-names = "offset";
569
+
570
+
status = "okay";
571
+
};
572
+
573
+
&pmk8280_sdam_6 {
574
+
status = "okay";
575
+
576
+
rtc_offset: rtc-offset@bc {
577
+
reg = <0xbc 0x4>;
578
+
};
562
579
};
563
580
564
581
&qup0 {
+154
-20
arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
+154
-20
arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
···
24
24
aliases {
25
25
i2c4 = &i2c4;
26
26
i2c21 = &i2c21;
27
+
serial1 = &uart2;
27
28
};
28
29
29
30
wcd938x: audio-codec {
···
364
363
compatible = "qcom,pm8350-rpmh-regulators";
365
364
qcom,pmic-id = "b";
366
365
366
+
vdd-l1-l4-supply = <&vreg_s12b>;
367
+
vdd-l2-l7-supply = <&vreg_bob>;
367
368
vdd-l3-l5-supply = <&vreg_s11b>;
369
+
vdd-l6-l9-l10-supply = <&vreg_s12b>;
370
+
vdd-l8-supply = <&vreg_s12b>;
368
371
369
372
vreg_s10b: smps10 {
370
373
regulator-name = "vreg_s10b";
371
374
regulator-min-microvolt = <1800000>;
372
375
regulator-max-microvolt = <1800000>;
373
376
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
377
+
regulator-always-on;
374
378
};
375
379
376
380
vreg_s11b: smps11 {
···
383
377
regulator-min-microvolt = <1272000>;
384
378
regulator-max-microvolt = <1272000>;
385
379
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
380
+
regulator-always-on;
386
381
};
387
382
388
383
vreg_s12b: smps12 {
···
391
384
regulator-min-microvolt = <984000>;
392
385
regulator-max-microvolt = <984000>;
393
386
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
387
+
regulator-always-on;
394
388
};
395
389
396
390
vreg_l3b: ldo3 {
···
421
413
regulators-1 {
422
414
compatible = "qcom,pm8350c-rpmh-regulators";
423
415
qcom,pmic-id = "c";
416
+
424
417
vdd-bob-supply = <&vreg_vph_pwr>;
418
+
vdd-l1-l12-supply = <&vreg_s1c>;
419
+
vdd-l2-l8-supply = <&vreg_s1c>;
420
+
vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>;
421
+
vdd-l6-l9-l11-supply = <&vreg_bob>;
422
+
vdd-l10-supply = <&vreg_s11b>;
423
+
424
+
vreg_s1c: smps1 {
425
+
regulator-name = "vreg_s1c";
426
+
regulator-min-microvolt = <1880000>;
427
+
regulator-max-microvolt = <1900000>;
428
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
429
+
regulator-always-on;
430
+
};
425
431
426
432
vreg_l1c: ldo1 {
427
433
regulator-name = "vreg_l1c";
···
463
441
regulator-min-microvolt = <3008000>;
464
442
regulator-max-microvolt = <3960000>;
465
443
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
444
+
regulator-always-on;
466
445
};
467
446
};
468
447
···
472
449
qcom,pmic-id = "d";
473
450
474
451
vdd-l1-l4-supply = <&vreg_s11b>;
452
+
vdd-l2-l7-supply = <&vreg_bob>;
453
+
vdd-l3-l5-supply = <&vreg_s11b>;
454
+
vdd-l6-l9-l10-supply = <&vreg_s12b>;
455
+
vdd-l8-supply = <&vreg_s12b>;
475
456
476
457
vreg_l3d: ldo3 {
477
458
regulator-name = "vreg_l3d";
···
554
527
backlight = <&backlight>;
555
528
power-supply = <&vreg_edp_3p3>;
556
529
557
-
ports {
558
-
port {
559
-
edp_panel_in: endpoint {
560
-
remote-endpoint = <&mdss0_dp3_out>;
561
-
};
530
+
port {
531
+
edp_panel_in: endpoint {
532
+
remote-endpoint = <&mdss0_dp3_out>;
562
533
};
563
534
};
564
535
};
···
595
570
hid-descr-addr = <0x1>;
596
571
interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>;
597
572
vdd-supply = <&vreg_misc_3p3>;
573
+
vddl-supply = <&vreg_s10b>;
598
574
599
575
pinctrl-names = "default";
600
576
pinctrl-0 = <&ts0_default>;
···
606
580
clock-frequency = <400000>;
607
581
608
582
pinctrl-names = "default";
609
-
pinctrl-0 = <&i2c21_default>;
583
+
pinctrl-0 = <&i2c21_default>, <&tpad_default>;
610
584
611
585
status = "okay";
612
586
···
617
591
hid-descr-addr = <0x1>;
618
592
interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>;
619
593
vdd-supply = <&vreg_misc_3p3>;
620
-
621
-
pinctrl-names = "default";
622
-
pinctrl-0 = <&tpad_default>;
594
+
vddl-supply = <&vreg_s10b>;
623
595
624
596
wakeup-source;
625
-
626
-
status = "disabled";
627
597
};
628
598
629
599
touchpad@2c {
···
629
607
hid-descr-addr = <0x20>;
630
608
interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>;
631
609
vdd-supply = <&vreg_misc_3p3>;
632
-
633
-
pinctrl-names = "default";
634
-
pinctrl-0 = <&tpad_default>;
610
+
vddl-supply = <&vreg_s10b>;
635
611
636
612
wakeup-source;
637
613
};
···
641
621
hid-descr-addr = <0x1>;
642
622
interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>;
643
623
vdd-supply = <&vreg_misc_3p3>;
624
+
vddl-supply = <&vreg_s10b>;
644
625
645
626
pinctrl-names = "default";
646
627
pinctrl-0 = <&kybd_default>;
···
698
677
pinctrl-0 = <&pcie4_default>;
699
678
700
679
status = "okay";
680
+
681
+
pcie@0 {
682
+
device_type = "pci";
683
+
reg = <0x0 0x0 0x0 0x0 0x0>;
684
+
#address-cells = <3>;
685
+
#size-cells = <2>;
686
+
ranges;
687
+
688
+
bus-range = <0x01 0xff>;
689
+
690
+
wifi@0 {
691
+
compatible = "pci17cb,1103";
692
+
reg = <0x10000 0x0 0x0 0x0 0x0>;
693
+
694
+
qcom,ath11k-calibration-variant = "LE_X13S";
695
+
};
696
+
};
701
697
};
702
698
703
699
&pcie4_phy {
···
804
766
status = "okay";
805
767
};
806
768
769
+
&pmk8280_rtc {
770
+
nvmem-cells = <&rtc_offset>;
771
+
nvmem-cell-names = "offset";
772
+
773
+
status = "okay";
774
+
};
775
+
776
+
&pmk8280_sdam_6 {
777
+
status = "okay";
778
+
779
+
rtc_offset: rtc-offset@bc {
780
+
reg = <0xbc 0x4>;
781
+
};
782
+
};
783
+
807
784
&pmk8280_vadc {
808
785
status = "okay";
809
786
810
787
pmic-die-temp@3 {
811
788
reg = <PMK8350_ADC7_DIE_TEMP>;
812
789
qcom,pre-scaling = <1 1>;
790
+
label = "pmk8350_die_temp";
813
791
};
814
792
815
793
xo-therm@44 {
816
794
reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
817
795
qcom,hw-settle-time = <200>;
818
796
qcom,ratiometric;
797
+
label = "pmk8350_xo_therm";
819
798
};
820
799
821
800
pmic-die-temp@103 {
822
801
reg = <PM8350_ADC7_DIE_TEMP(1)>;
823
802
qcom,pre-scaling = <1 1>;
803
+
label = "pmc8280_1_die_temp";
824
804
};
825
805
826
806
sys-therm@144 {
827
807
reg = <PM8350_ADC7_AMUX_THM1_100K_PU(1)>;
828
808
qcom,hw-settle-time = <200>;
829
809
qcom,ratiometric;
810
+
label = "sys_therm1";
830
811
};
831
812
832
813
sys-therm@145 {
833
814
reg = <PM8350_ADC7_AMUX_THM2_100K_PU(1)>;
834
815
qcom,hw-settle-time = <200>;
835
816
qcom,ratiometric;
817
+
label = "sys_therm2";
836
818
};
837
819
838
820
sys-therm@146 {
839
821
reg = <PM8350_ADC7_AMUX_THM3_100K_PU(1)>;
840
822
qcom,hw-settle-time = <200>;
841
823
qcom,ratiometric;
824
+
label = "sys_therm3";
842
825
};
843
826
844
827
sys-therm@147 {
845
828
reg = <PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
846
829
qcom,hw-settle-time = <200>;
847
830
qcom,ratiometric;
831
+
label = "sys_therm4";
848
832
};
849
833
850
834
pmic-die-temp@303 {
851
835
reg = <PM8350_ADC7_DIE_TEMP(3)>;
852
836
qcom,pre-scaling = <1 1>;
837
+
label = "pmc8280_2_die_temp";
853
838
};
854
839
855
840
sys-therm@344 {
856
841
reg = <PM8350_ADC7_AMUX_THM1_100K_PU(3)>;
857
842
qcom,hw-settle-time = <200>;
858
843
qcom,ratiometric;
844
+
label = "sys_therm5";
859
845
};
860
846
861
847
sys-therm@345 {
862
848
reg = <PM8350_ADC7_AMUX_THM2_100K_PU(3)>;
863
849
qcom,hw-settle-time = <200>;
864
850
qcom,ratiometric;
851
+
label = "sys_therm6";
865
852
};
866
853
867
854
sys-therm@346 {
868
855
reg = <PM8350_ADC7_AMUX_THM3_100K_PU(3)>;
869
856
qcom,hw-settle-time = <200>;
870
857
qcom,ratiometric;
858
+
label = "sys_therm7";
871
859
};
872
860
873
861
sys-therm@347 {
874
862
reg = <PM8350_ADC7_AMUX_THM4_100K_PU(3)>;
875
863
qcom,hw-settle-time = <200>;
876
864
qcom,ratiometric;
865
+
label = "sys_therm8";
877
866
};
878
867
879
868
pmic-die-temp@403 {
880
869
reg = <PMR735A_ADC7_DIE_TEMP>;
881
870
qcom,pre-scaling = <1 1>;
871
+
label = "pmr735a_die_temp";
882
872
};
883
873
};
884
874
···
950
884
"VA DMIC0", "MIC BIAS1",
951
885
"VA DMIC1", "MIC BIAS1",
952
886
"VA DMIC2", "MIC BIAS3",
953
-
"TX DMIC0", "MIC BIAS1",
954
-
"TX DMIC1", "MIC BIAS2",
955
-
"TX DMIC2", "MIC BIAS3",
887
+
"VA DMIC0", "VA MIC BIAS1",
888
+
"VA DMIC1", "VA MIC BIAS1",
889
+
"VA DMIC2", "VA MIC BIAS3",
956
890
"TX SWR_ADC1", "ADC2_OUTPUT";
957
891
958
892
wcd-playback-dai-link {
···
1003
937
va-dai-link {
1004
938
link-name = "VA Capture";
1005
939
cpu {
1006
-
sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
940
+
sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
1007
941
};
1008
942
1009
943
platform {
···
1068
1002
status = "okay";
1069
1003
};
1070
1004
1005
+
&uart2 {
1006
+
pinctrl-0 = <&uart2_default>;
1007
+
pinctrl-names = "default";
1008
+
1009
+
status = "okay";
1010
+
1011
+
bluetooth {
1012
+
compatible = "qcom,wcn6855-bt";
1013
+
1014
+
vddio-supply = <&vreg_s10b>;
1015
+
vddbtcxmx-supply = <&vreg_s12b>;
1016
+
vddrfacmn-supply = <&vreg_s12b>;
1017
+
vddrfa0p8-supply = <&vreg_s12b>;
1018
+
vddrfa1p2-supply = <&vreg_s11b>;
1019
+
vddrfa1p7-supply = <&vreg_s1c>;
1020
+
1021
+
max-speed = <3200000>;
1022
+
1023
+
enable-gpios = <&tlmm 133 GPIO_ACTIVE_HIGH>;
1024
+
swctrl-gpios = <&tlmm 132 GPIO_ACTIVE_HIGH>;
1025
+
1026
+
pinctrl-0 = <&bt_default>;
1027
+
pinctrl-names = "default";
1028
+
};
1029
+
};
1030
+
1071
1031
&usb_0 {
1072
1032
status = "okay";
1073
1033
};
···
1154
1062
1155
1063
vdd-micb-supply = <&vreg_s10b>;
1156
1064
1157
-
qcom,dmic-sample-rate = <600000>;
1065
+
qcom,dmic-sample-rate = <4800000>;
1158
1066
1159
1067
status = "okay";
1160
1068
};
···
1214
1122
&tlmm {
1215
1123
gpio-reserved-ranges = <70 2>, <74 6>, <83 4>, <125 2>, <128 2>, <154 7>;
1216
1124
1125
+
bt_default: bt-default-state {
1126
+
hstp-bt-en-pins {
1127
+
pins = "gpio133";
1128
+
function = "gpio";
1129
+
drive-strength = <16>;
1130
+
bias-disable;
1131
+
};
1132
+
1133
+
hstp-sw-ctrl-pins {
1134
+
pins = "gpio132";
1135
+
function = "gpio";
1136
+
bias-pull-down;
1137
+
};
1138
+
};
1139
+
1217
1140
edp_reg_en: edp-reg-en-state {
1218
1141
pins = "gpio25";
1219
1142
function = "gpio";
···
1239
1132
hall_int_n_default: hall-int-n-state {
1240
1133
pins = "gpio107";
1241
1134
function = "gpio";
1242
-
input-enable;
1243
1135
bias-disable;
1244
1136
};
1245
1137
···
1392
1286
function = "gpio";
1393
1287
output-high;
1394
1288
drive-strength = <16>;
1289
+
};
1290
+
};
1291
+
1292
+
uart2_default: uart2-default-state {
1293
+
cts-pins {
1294
+
pins = "gpio121";
1295
+
function = "qup2";
1296
+
bias-bus-hold;
1297
+
};
1298
+
1299
+
rts-pins {
1300
+
pins = "gpio122";
1301
+
function = "qup2";
1302
+
drive-strength = <2>;
1303
+
bias-disable;
1304
+
};
1305
+
1306
+
rx-pins {
1307
+
pins = "gpio124";
1308
+
function = "qup2";
1309
+
bias-pull-up;
1310
+
};
1311
+
1312
+
tx-pins {
1313
+
pins = "gpio123";
1314
+
function = "qup2";
1315
+
drive-strength = <2>;
1316
+
bias-disable;
1395
1317
};
1396
1318
};
1397
1319
+21
-2
arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi
+21
-2
arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi
···
59
59
#size-cells = <0>;
60
60
61
61
pmk8280_pon: pon@1300 {
62
-
compatible = "qcom,pm8998-pon";
63
-
reg = <0x1300>;
62
+
compatible = "qcom,pmk8350-pon";
63
+
reg = <0x1300>, <0x800>;
64
+
reg-names = "hlos", "pbs";
64
65
65
66
pmk8280_pon_pwrkey: pwrkey {
66
67
compatible = "qcom,pmk8350-pwrkey";
···
94
93
#address-cells = <1>;
95
94
#size-cells = <0>;
96
95
#thermal-sensor-cells = <1>;
96
+
status = "disabled";
97
+
};
98
+
99
+
pmk8280_rtc: rtc@6100 {
100
+
compatible = "qcom,pmk8350-rtc";
101
+
reg = <0x6100>, <0x6200>;
102
+
reg-names = "rtc", "alarm";
103
+
interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
104
+
wakeup-source;
105
+
status = "disabled";
106
+
};
107
+
108
+
pmk8280_sdam_6: nvram@8500 {
109
+
compatible = "qcom,spmi-sdam";
110
+
reg = <0x8500>;
111
+
#address-cells = <1>;
112
+
#size-cells = <1>;
113
+
ranges = <0 0x8500 0x100>;
97
114
status = "disabled";
98
115
};
99
116
};
+72
-41
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+72
-41
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
···
43
43
44
44
CPU0: cpu@0 {
45
45
device_type = "cpu";
46
-
compatible = "qcom,kryo";
46
+
compatible = "arm,cortex-a78c";
47
47
reg = <0x0 0x0>;
48
+
clocks = <&cpufreq_hw 0>;
48
49
enable-method = "psci";
49
50
capacity-dmips-mhz = <602>;
50
51
next-level-cache = <&L2_0>;
···
68
67
69
68
CPU1: cpu@100 {
70
69
device_type = "cpu";
71
-
compatible = "qcom,kryo";
70
+
compatible = "arm,cortex-a78c";
72
71
reg = <0x0 0x100>;
72
+
clocks = <&cpufreq_hw 0>;
73
73
enable-method = "psci";
74
74
capacity-dmips-mhz = <602>;
75
75
next-level-cache = <&L2_100>;
···
89
87
90
88
CPU2: cpu@200 {
91
89
device_type = "cpu";
92
-
compatible = "qcom,kryo";
90
+
compatible = "arm,cortex-a78c";
93
91
reg = <0x0 0x200>;
92
+
clocks = <&cpufreq_hw 0>;
94
93
enable-method = "psci";
95
94
capacity-dmips-mhz = <602>;
96
95
next-level-cache = <&L2_200>;
···
110
107
111
108
CPU3: cpu@300 {
112
109
device_type = "cpu";
113
-
compatible = "qcom,kryo";
110
+
compatible = "arm,cortex-a78c";
114
111
reg = <0x0 0x300>;
112
+
clocks = <&cpufreq_hw 0>;
115
113
enable-method = "psci";
116
114
capacity-dmips-mhz = <602>;
117
115
next-level-cache = <&L2_300>;
···
131
127
132
128
CPU4: cpu@400 {
133
129
device_type = "cpu";
134
-
compatible = "qcom,kryo";
130
+
compatible = "arm,cortex-x1c";
135
131
reg = <0x0 0x400>;
132
+
clocks = <&cpufreq_hw 1>;
136
133
enable-method = "psci";
137
134
capacity-dmips-mhz = <1024>;
138
135
next-level-cache = <&L2_400>;
···
152
147
153
148
CPU5: cpu@500 {
154
149
device_type = "cpu";
155
-
compatible = "qcom,kryo";
150
+
compatible = "arm,cortex-x1c";
156
151
reg = <0x0 0x500>;
152
+
clocks = <&cpufreq_hw 1>;
157
153
enable-method = "psci";
158
154
capacity-dmips-mhz = <1024>;
159
155
next-level-cache = <&L2_500>;
···
173
167
174
168
CPU6: cpu@600 {
175
169
device_type = "cpu";
176
-
compatible = "qcom,kryo";
170
+
compatible = "arm,cortex-x1c";
177
171
reg = <0x0 0x600>;
172
+
clocks = <&cpufreq_hw 1>;
178
173
enable-method = "psci";
179
174
capacity-dmips-mhz = <1024>;
180
175
next-level-cache = <&L2_600>;
···
194
187
195
188
CPU7: cpu@700 {
196
189
device_type = "cpu";
197
-
compatible = "qcom,kryo";
190
+
compatible = "arm,cortex-x1c";
198
191
reg = <0x0 0x700>;
192
+
clocks = <&cpufreq_hw 1>;
199
193
enable-method = "psci";
200
194
capacity-dmips-mhz = <1024>;
201
195
next-level-cache = <&L2_700>;
···
276
268
domain-idle-states {
277
269
CLUSTER_SLEEP_0: cluster-sleep-0 {
278
270
compatible = "domain-idle-state";
279
-
idle-state-name = "cluster-power-collapse";
280
271
arm,psci-suspend-param = <0x4100c344>;
281
272
entry-latency-us = <3263>;
282
273
exit-latency-us = <6562>;
···
1214
1207
status = "disabled";
1215
1208
};
1216
1209
1210
+
uart2: serial@988000 {
1211
+
compatible = "qcom,geni-uart";
1212
+
reg = <0 0x00988000 0 0x4000>;
1213
+
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1214
+
clock-names = "se";
1215
+
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1216
+
operating-points-v2 = <&qup_opp_table_100mhz>;
1217
+
power-domains = <&rpmhpd SC8280XP_CX>;
1218
+
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1219
+
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1220
+
interconnect-names = "qup-core", "qup-config";
1221
+
status = "disabled";
1222
+
};
1223
+
1217
1224
i2c3: i2c@98c000 {
1218
1225
compatible = "qcom,geni-i2c";
1219
1226
reg = <0 0x0098c000 0 0x4000>;
···
1674
1653
<0x0 0x30000000 0x0 0xf1d>,
1675
1654
<0x0 0x30000f20 0x0 0xa8>,
1676
1655
<0x0 0x30001000 0x0 0x1000>,
1677
-
<0x0 0x30100000 0x0 0x100000>;
1678
-
reg-names = "parf", "dbi", "elbi", "atu", "config";
1656
+
<0x0 0x30100000 0x0 0x100000>,
1657
+
<0x0 0x01c03000 0x0 0x1000>;
1658
+
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1679
1659
#address-cells = <3>;
1680
1660
#size-cells = <2>;
1681
-
ranges = <0x01000000 0x0 0x30200000 0x0 0x30200000 0x0 0x100000>,
1661
+
ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>,
1682
1662
<0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>;
1683
1663
bus-range = <0x00 0xff>;
1684
1664
···
1774
1752
<0x0 0x32000000 0x0 0xf1d>,
1775
1753
<0x0 0x32000f20 0x0 0xa8>,
1776
1754
<0x0 0x32001000 0x0 0x1000>,
1777
-
<0x0 0x32100000 0x0 0x100000>;
1778
-
reg-names = "parf", "dbi", "elbi", "atu", "config";
1755
+
<0x0 0x32100000 0x0 0x100000>,
1756
+
<0x0 0x01c0b000 0x0 0x1000>;
1757
+
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1779
1758
#address-cells = <3>;
1780
1759
#size-cells = <2>;
1781
-
ranges = <0x01000000 0x0 0x32200000 0x0 0x32200000 0x0 0x100000>,
1760
+
ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>,
1782
1761
<0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>;
1783
1762
bus-range = <0x00 0xff>;
1784
1763
···
1872
1849
<0x0 0x34000000 0x0 0xf1d>,
1873
1850
<0x0 0x34000f20 0x0 0xa8>,
1874
1851
<0x0 0x34001000 0x0 0x1000>,
1875
-
<0x0 0x34100000 0x0 0x100000>;
1876
-
reg-names = "parf", "dbi", "elbi", "atu", "config";
1852
+
<0x0 0x34100000 0x0 0x100000>,
1853
+
<0x0 0x01c13000 0x0 0x1000>;
1854
+
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1877
1855
#address-cells = <3>;
1878
1856
#size-cells = <2>;
1879
-
ranges = <0x01000000 0x0 0x34200000 0x0 0x34200000 0x0 0x100000>,
1857
+
ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>,
1880
1858
<0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>;
1881
1859
bus-range = <0x00 0xff>;
1882
1860
···
1973
1949
<0x0 0x38000000 0x0 0xf1d>,
1974
1950
<0x0 0x38000f20 0x0 0xa8>,
1975
1951
<0x0 0x38001000 0x0 0x1000>,
1976
-
<0x0 0x38100000 0x0 0x100000>;
1977
-
reg-names = "parf", "dbi", "elbi", "atu", "config";
1952
+
<0x0 0x38100000 0x0 0x100000>,
1953
+
<0x0 0x01c1b000 0x0 0x1000>;
1954
+
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1978
1955
#address-cells = <3>;
1979
1956
#size-cells = <2>;
1980
-
ranges = <0x01000000 0x0 0x38200000 0x0 0x38200000 0x0 0x100000>,
1957
+
ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>,
1981
1958
<0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>;
1982
1959
bus-range = <0x00 0xff>;
1983
1960
···
2071
2046
<0x0 0x3c000000 0x0 0xf1d>,
2072
2047
<0x0 0x3c000f20 0x0 0xa8>,
2073
2048
<0x0 0x3c001000 0x0 0x1000>,
2074
-
<0x0 0x3c100000 0x0 0x100000>;
2075
-
reg-names = "parf", "dbi", "elbi", "atu", "config";
2049
+
<0x0 0x3c100000 0x0 0x100000>,
2050
+
<0x0 0x01c23000 0x0 0x1000>;
2051
+
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2076
2052
#address-cells = <3>;
2077
2053
#size-cells = <2>;
2078
-
ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>,
2054
+
ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>,
2079
2055
<0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>;
2080
2056
bus-range = <0x00 0xff>;
2081
2057
···
2530
2504
qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2531
2505
qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2532
2506
qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2533
-
qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2534
-
qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2507
+
qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>;
2508
+
qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>;
2535
2509
qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2536
-
qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2510
+
qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>;
2537
2511
qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2538
-
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2512
+
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2539
2513
2540
2514
#sound-dai-cells = <1>;
2541
2515
#address-cells = <2>;
···
2624
2598
reg = <0 0x03330000 0 0x2000>;
2625
2599
interrupts-extended = <&intc GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>,
2626
2600
<&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
2627
-
interrupt-names = "core", "wake";
2601
+
interrupt-names = "core", "wakeup";
2628
2602
2629
-
clocks = <&vamacro>;
2603
+
clocks = <&txmacro>;
2630
2604
clock-names = "iface";
2631
2605
label = "TX";
2632
2606
#sound-dai-cells = <1>;
···
2635
2609
2636
2610
qcom,din-ports = <4>;
2637
2611
qcom,dout-ports = <0>;
2638
-
qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03 0x03>;
2639
-
qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x01>;
2612
+
qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2613
+
qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>;
2640
2614
qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2641
2615
qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2642
2616
qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2643
2617
qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2644
-
qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff 0xff>;
2618
+
qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2645
2619
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2646
-
qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x00>;
2620
+
qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>;
2647
2621
2648
2622
status = "disabled";
2649
2623
};
···
2799
2773
drive-strength = <2>;
2800
2774
slew-rate = <1>;
2801
2775
bias-bus-hold;
2802
-
2803
2776
};
2804
2777
};
2805
2778
···
2971
2946
};
2972
2947
2973
2948
pmu@90b6400 {
2974
-
compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,msm8998-bwmon";
2949
+
compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon";
2975
2950
reg = <0 0x090b6400 0 0x600>;
2976
2951
2977
2952
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
···
3008
2983
3009
2984
system-cache-controller@9200000 {
3010
2985
compatible = "qcom,sc8280xp-llcc";
3011
-
reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>;
3012
-
reg-names = "llcc_base", "llcc_broadcast_base";
2986
+
reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
2987
+
<0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
2988
+
<0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>,
2989
+
<0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>,
2990
+
<0 0x09600000 0 0x58000>;
2991
+
reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2992
+
"llcc3_base", "llcc4_base", "llcc5_base",
2993
+
"llcc6_base", "llcc7_base", "llcc_broadcast_base";
3013
2994
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
3014
2995
};
3015
2996
···
3284
3253
#sound-dai-cells = <0>;
3285
3254
3286
3255
operating-points-v2 = <&mdss0_dp0_opp_table>;
3287
-
power-domains = <&rpmhpd SC8280XP_CX>;
3256
+
power-domains = <&rpmhpd SC8280XP_MMCX>;
3288
3257
3289
3258
status = "disabled";
3290
3259
···
3362
3331
#sound-dai-cells = <0>;
3363
3332
3364
3333
operating-points-v2 = <&mdss0_dp1_opp_table>;
3365
-
power-domains = <&rpmhpd SC8280XP_CX>;
3334
+
power-domains = <&rpmhpd SC8280XP_MMCX>;
3366
3335
3367
3336
status = "disabled";
3368
3337
···
4071
4040
clock-names = "xo", "alternate";
4072
4041
4073
4042
#freq-domain-cells = <1>;
4043
+
#clock-cells = <1>;
4074
4044
};
4075
4045
4076
4046
remoteproc_nsp0: remoteproc@1b300000 {
···
4430
4398
required-opps = <&rpmhpd_opp_nom>;
4431
4399
};
4432
4400
};
4433
-
4434
4401
};
4435
4402
4436
4403
mdss1_dp1: displayport-controller@22098000 {
+1
-1
arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts
+1
-1
arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts
+1
-1
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi
+1
-1
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi
+19
-20
arch/arm64/boot/dts/qcom/sdm630.dtsi
+19
-20
arch/arm64/boot/dts/qcom/sdm630.dtsi
···
1189
1189
#size-cells = <0>;
1190
1190
interrupt-controller;
1191
1191
#interrupt-cells = <4>;
1192
-
cell-index = <0>;
1193
1192
};
1194
1193
1195
1194
usb3: usb@a8f8800 {
···
1450
1451
<0>;
1451
1452
};
1452
1453
1453
-
dsi_opp_table: opp-table-dsi {
1454
-
compatible = "operating-points-v2";
1455
-
1456
-
opp-131250000 {
1457
-
opp-hz = /bits/ 64 <131250000>;
1458
-
required-opps = <&rpmpd_opp_svs>;
1459
-
};
1460
-
1461
-
opp-210000000 {
1462
-
opp-hz = /bits/ 64 <210000000>;
1463
-
required-opps = <&rpmpd_opp_svs_plus>;
1464
-
};
1465
-
1466
-
opp-262500000 {
1467
-
opp-hz = /bits/ 64 <262500000>;
1468
-
required-opps = <&rpmpd_opp_nom>;
1469
-
};
1470
-
};
1471
-
1472
1454
mdss: display-subsystem@c900000 {
1473
1455
compatible = "qcom,mdss";
1474
1456
reg = <0x0c900000 0x1000>,
···
1590
1610
phys = <&dsi0_phy>;
1591
1611
1592
1612
status = "disabled";
1613
+
1614
+
dsi_opp_table: opp-table {
1615
+
compatible = "operating-points-v2";
1616
+
1617
+
opp-131250000 {
1618
+
opp-hz = /bits/ 64 <131250000>;
1619
+
required-opps = <&rpmpd_opp_svs>;
1620
+
};
1621
+
1622
+
opp-210000000 {
1623
+
opp-hz = /bits/ 64 <210000000>;
1624
+
required-opps = <&rpmpd_opp_svs_plus>;
1625
+
};
1626
+
1627
+
opp-262500000 {
1628
+
opp-hz = /bits/ 64 <262500000>;
1629
+
required-opps = <&rpmpd_opp_nom>;
1630
+
};
1631
+
};
1593
1632
1594
1633
ports {
1595
1634
#address-cells = <1>;
-1
arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
-1
arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
+109
arch/arm64/boot/dts/qcom/sdm670.dtsi
+109
arch/arm64/boot/dts/qcom/sdm670.dtsi
···
10
10
#include <dt-bindings/clock/qcom,rpmh.h>
11
11
#include <dt-bindings/dma/qcom-gpi.h>
12
12
#include <dt-bindings/gpio/gpio.h>
13
+
#include <dt-bindings/interconnect/qcom,sdm670-rpmh.h>
13
14
#include <dt-bindings/interrupt-controller/arm-gic.h>
14
15
#include <dt-bindings/phy/phy-qcom-qusb2.h>
15
16
#include <dt-bindings/power/qcom-rpmpd.h>
···
431
430
<&gcc GCC_SDCC1_ICE_CORE_CLK>,
432
431
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;
433
432
clock-names = "iface", "core", "xo", "ice", "bus";
433
+
interconnects = <&aggre1_noc MASTER_EMMC 0 &aggre1_noc SLAVE_A1NOC_SNOC 0>,
434
+
<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_EMMC_CFG 0>;
435
+
interconnect-names = "sdhc-ddr", "cpu-sdhc";
436
+
operating-points-v2 = <&sdhc1_opp_table>;
434
437
435
438
iommus = <&apps_smmu 0x140 0xf>;
436
439
···
447
442
non-removable;
448
443
449
444
status = "disabled";
445
+
446
+
sdhc1_opp_table: opp-table {
447
+
compatible = "operating-points-v2";
448
+
449
+
opp-20000000 {
450
+
opp-hz = /bits/ 64 <20000000>;
451
+
required-opps = <&rpmhpd_opp_min_svs>;
452
+
opp-peak-kBps = <80000 80000>;
453
+
opp-avg-kBps = <52286 80000>;
454
+
};
455
+
456
+
opp-50000000 {
457
+
opp-hz = /bits/ 64 <50000000>;
458
+
required-opps = <&rpmhpd_opp_low_svs>;
459
+
opp-peak-kBps = <200000 100000>;
460
+
opp-avg-kBps = <130718 100000>;
461
+
};
462
+
463
+
opp-100000000 {
464
+
opp-hz = /bits/ 64 <100000000>;
465
+
required-opps = <&rpmhpd_opp_svs>;
466
+
opp-peak-kBps = <200000 130000>;
467
+
opp-avg-kBps = <130718 130000>;
468
+
};
469
+
470
+
opp-384000000 {
471
+
opp-hz = /bits/ 64 <384000000>;
472
+
required-opps = <&rpmhpd_opp_nom>;
473
+
opp-peak-kBps = <4096000 4096000>;
474
+
opp-avg-kBps = <1338562 1338562>;
475
+
};
476
+
};
450
477
};
451
478
452
479
gpi_dma0: dma-controller@800000 {
···
514
477
#address-cells = <2>;
515
478
#size-cells = <2>;
516
479
ranges;
480
+
interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>;
481
+
interconnect-names = "qup-core";
517
482
status = "disabled";
518
483
519
484
i2c0: i2c@880000 {
···
529
490
#address-cells = <1>;
530
491
#size-cells = <0>;
531
492
power-domains = <&rpmhpd SDM670_CX>;
493
+
interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
494
+
<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
495
+
<&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
496
+
interconnect-names = "qup-core", "qup-config", "qup-memory";
532
497
dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
533
498
<&gpi_dma0 1 0 QCOM_GPI_I2C>;
534
499
dma-names = "tx", "rx";
···
550
507
#address-cells = <1>;
551
508
#size-cells = <0>;
552
509
power-domains = <&rpmhpd SDM670_CX>;
510
+
interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
511
+
<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
512
+
<&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
513
+
interconnect-names = "qup-core", "qup-config", "qup-memory";
553
514
dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
554
515
<&gpi_dma0 1 1 QCOM_GPI_I2C>;
555
516
dma-names = "tx", "rx";
···
571
524
#address-cells = <1>;
572
525
#size-cells = <0>;
573
526
power-domains = <&rpmhpd SDM670_CX>;
527
+
interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
528
+
<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
529
+
<&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
530
+
interconnect-names = "qup-core", "qup-config", "qup-memory";
574
531
dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
575
532
<&gpi_dma0 1 2 QCOM_GPI_I2C>;
576
533
dma-names = "tx", "rx";
···
592
541
#address-cells = <1>;
593
542
#size-cells = <0>;
594
543
power-domains = <&rpmhpd SDM670_CX>;
544
+
interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
545
+
<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
546
+
<&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
547
+
interconnect-names = "qup-core", "qup-config", "qup-memory";
595
548
dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
596
549
<&gpi_dma0 1 3 QCOM_GPI_I2C>;
597
550
dma-names = "tx", "rx";
···
613
558
#address-cells = <1>;
614
559
#size-cells = <0>;
615
560
power-domains = <&rpmhpd SDM670_CX>;
561
+
interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
562
+
<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
563
+
<&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
564
+
interconnect-names = "qup-core", "qup-config", "qup-memory";
616
565
dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
617
566
<&gpi_dma0 1 4 QCOM_GPI_I2C>;
618
567
dma-names = "tx", "rx";
···
634
575
#address-cells = <1>;
635
576
#size-cells = <0>;
636
577
power-domains = <&rpmhpd SDM670_CX>;
578
+
interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
579
+
<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
580
+
<&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
581
+
interconnect-names = "qup-core", "qup-config", "qup-memory";
637
582
dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
638
583
<&gpi_dma0 1 5 QCOM_GPI_I2C>;
639
584
dma-names = "tx", "rx";
···
655
592
#address-cells = <1>;
656
593
#size-cells = <0>;
657
594
power-domains = <&rpmhpd SDM670_CX>;
595
+
interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
596
+
<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
597
+
<&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
598
+
interconnect-names = "qup-core", "qup-config", "qup-memory";
658
599
dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
659
600
<&gpi_dma0 1 6 QCOM_GPI_I2C>;
660
601
dma-names = "tx", "rx";
···
676
609
#address-cells = <1>;
677
610
#size-cells = <0>;
678
611
power-domains = <&rpmhpd SDM670_CX>;
612
+
interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
613
+
<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
614
+
<&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
615
+
interconnect-names = "qup-core", "qup-config", "qup-memory";
679
616
dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
680
617
<&gpi_dma0 1 7 QCOM_GPI_I2C>;
681
618
dma-names = "tx", "rx";
···
720
649
#address-cells = <2>;
721
650
#size-cells = <2>;
722
651
ranges;
652
+
interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>;
653
+
interconnect-names = "qup-core";
723
654
status = "disabled";
724
655
725
656
i2c8: i2c@a80000 {
···
735
662
#address-cells = <1>;
736
663
#size-cells = <0>;
737
664
power-domains = <&rpmhpd SDM670_CX>;
665
+
interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
666
+
<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
667
+
<&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
668
+
interconnect-names = "qup-core", "qup-config", "qup-memory";
738
669
dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
739
670
<&gpi_dma1 1 0 QCOM_GPI_I2C>;
740
671
dma-names = "tx", "rx";
···
756
679
#address-cells = <1>;
757
680
#size-cells = <0>;
758
681
power-domains = <&rpmhpd SDM670_CX>;
682
+
interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
683
+
<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
684
+
<&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
685
+
interconnect-names = "qup-core", "qup-config", "qup-memory";
759
686
dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
760
687
<&gpi_dma1 1 1 QCOM_GPI_I2C>;
761
688
dma-names = "tx", "rx";
···
777
696
#address-cells = <1>;
778
697
#size-cells = <0>;
779
698
power-domains = <&rpmhpd SDM670_CX>;
699
+
interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
700
+
<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
701
+
<&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
702
+
interconnect-names = "qup-core", "qup-config", "qup-memory";
780
703
dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
781
704
<&gpi_dma1 1 2 QCOM_GPI_I2C>;
782
705
dma-names = "tx", "rx";
···
798
713
#address-cells = <1>;
799
714
#size-cells = <0>;
800
715
power-domains = <&rpmhpd SDM670_CX>;
716
+
interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
717
+
<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
718
+
<&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
719
+
interconnect-names = "qup-core", "qup-config", "qup-memory";
801
720
dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
802
721
<&gpi_dma1 1 3 QCOM_GPI_I2C>;
803
722
dma-names = "tx", "rx";
···
819
730
#address-cells = <1>;
820
731
#size-cells = <0>;
821
732
power-domains = <&rpmhpd SDM670_CX>;
733
+
interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
734
+
<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
735
+
<&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
736
+
interconnect-names = "qup-core", "qup-config", "qup-memory";
822
737
dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
823
738
<&gpi_dma1 1 4 QCOM_GPI_I2C>;
824
739
dma-names = "tx", "rx";
···
840
747
#address-cells = <1>;
841
748
#size-cells = <0>;
842
749
power-domains = <&rpmhpd SDM670_CX>;
750
+
interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
751
+
<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
752
+
<&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
753
+
interconnect-names = "qup-core", "qup-config", "qup-memory";
843
754
dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
844
755
<&gpi_dma1 1 5 QCOM_GPI_I2C>;
845
756
dma-names = "tx", "rx";
···
861
764
#address-cells = <1>;
862
765
#size-cells = <0>;
863
766
power-domains = <&rpmhpd SDM670_CX>;
767
+
interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
768
+
<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
769
+
<&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
770
+
interconnect-names = "qup-core", "qup-config", "qup-memory";
864
771
dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
865
772
<&gpi_dma1 1 6 QCOM_GPI_I2C>;
866
773
dma-names = "tx", "rx";
···
882
781
#address-cells = <1>;
883
782
#size-cells = <0>;
884
783
power-domains = <&rpmhpd SDM670_CX>;
784
+
interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
785
+
<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
786
+
<&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
787
+
interconnect-names = "qup-core", "qup-config", "qup-memory";
885
788
dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
886
789
<&gpi_dma1 1 7 QCOM_GPI_I2C>;
887
790
dma-names = "tx", "rx";
···
1132
1027
power-domains = <&gcc USB30_PRIM_GDSC>;
1133
1028
1134
1029
resets = <&gcc GCC_USB30_PRIM_BCR>;
1030
+
1031
+
interconnects = <&aggre2_noc MASTER_USB3 0 &mem_noc SLAVE_EBI_CH0 0>,
1032
+
<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
1033
+
interconnect-names = "usb-ddr", "apps-usb";
1135
1034
1136
1035
status = "disabled";
1137
1036
+3
-5
arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
+3
-5
arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
···
135
135
backlight = <&backlight>;
136
136
no-hpd;
137
137
138
-
ports {
139
-
panel_in: port {
140
-
panel_in_edp: endpoint {
141
-
remote-endpoint = <&sn65dsi86_out>;
142
-
};
138
+
panel_in: port {
139
+
panel_in_edp: endpoint {
140
+
remote-endpoint = <&sn65dsi86_out>;
143
141
};
144
142
};
145
143
};
-5
arch/arm64/boot/dts/qcom/sdm845-db845c.dts
-5
arch/arm64/boot/dts/qcom/sdm845-db845c.dts
···
819
819
820
820
&spi2 {
821
821
/* On Low speed expansion */
822
-
label = "LS-SPI0";
823
822
status = "okay";
824
823
};
825
824
···
1133
1134
&qup_uart9_tx {
1134
1135
drive-strength = <2>;
1135
1136
bias-disable;
1136
-
};
1137
-
1138
-
&pm8998_gpios {
1139
-
1140
1137
};
1141
1138
1142
1139
/* PINCTRL - additions to nodes defined in sdm845.dtsi */
+25
-2
arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi
+25
-2
arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi
···
29
29
stdout-path = "serial0:115200n8";
30
30
};
31
31
32
+
gpio-hall-sensor {
33
+
compatible = "gpio-keys";
34
+
label = "Hall effect sensor";
35
+
36
+
pinctrl-0 = <&hall_sensor_default>;
37
+
pinctrl-names = "default";
38
+
39
+
event-hall-sensor {
40
+
gpios = <&tlmm 124 GPIO_ACTIVE_LOW>;
41
+
label = "Hall Effect Sensor";
42
+
linux,input-type = <EV_SW>;
43
+
linux,code = <SW_LID>;
44
+
linux,can-disable;
45
+
wakeup-source;
46
+
};
47
+
};
48
+
32
49
gpio-keys {
33
50
compatible = "gpio-keys";
34
51
label = "Volume keys";
···
347
330
display_panel: panel@0 {
348
331
status = "disabled";
349
332
350
-
#address-cells = <1>;
351
-
#size-cells = <0>;
352
333
reg = <0>;
353
334
354
335
vddio-supply = <&vreg_l14a_1p88>;
···
767
752
768
753
&tlmm {
769
754
gpio-reserved-ranges = <0 4>, <81 4>;
755
+
756
+
hall_sensor_default: hall-sensor-default-state {
757
+
pins = "gpio124";
758
+
function = "gpio";
759
+
drive-strength = <2>;
760
+
bias-disable;
761
+
input-enable;
762
+
};
770
763
771
764
tri_state_key_default: tri-state-key-default-state {
772
765
pins = "gpio40", "gpio42", "gpio26";
-1
arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts
-1
arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts
+4
arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akari.dts
+4
arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akari.dts
+46
-1
arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts
+46
-1
arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts
···
7
7
8
8
#include "sdm845-sony-xperia-tama.dtsi"
9
9
10
+
/* XZ3 uses an Atmel touchscreen instead. */
11
+
/delete-node/ &touchscreen;
12
+
10
13
/ {
11
14
model = "Sony Xperia XZ3";
12
15
compatible = "sony,akatsuki-row", "qcom,sdm845";
16
+
17
+
/* Fixed DCDC for the OLED panel */
18
+
ts_vddio_supply: ts-vddio-regulator {
19
+
compatible = "regulator-fixed";
20
+
regulator-name = "ts_vddio";
21
+
22
+
regulator-min-microvolt = <1840000>;
23
+
regulator-max-microvolt = <1840000>;
24
+
25
+
gpio = <&tlmm 133 GPIO_ACTIVE_HIGH>;
26
+
enable-active-high;
27
+
regulator-boot-on;
28
+
};
13
29
};
14
30
15
-
/* For the future: WLED + LAB/IBB/OLEDB are not used on Akatsuki */
31
+
&ibb {
32
+
status = "disabled";
33
+
};
34
+
35
+
&lab {
36
+
status = "disabled";
37
+
};
38
+
39
+
&panel {
40
+
/* Akatsuki uses an OLED panel. */
41
+
/delete-property/ backlight;
42
+
/delete-property/ vsp-supply;
43
+
/delete-property/ vsn-supply;
44
+
/delete-property/ touch-reset-gpios;
45
+
};
46
+
47
+
&pmi8998_wled {
48
+
status = "disabled";
49
+
};
50
+
51
+
&tlmm {
52
+
ts_vddio_en: ts-vddio-en-state {
53
+
pins = "gpio133";
54
+
function = "gpio";
55
+
drive-strength = <2>;
56
+
bias-disable;
57
+
output-high;
58
+
};
59
+
};
60
+
16
61
&vreg_l14a_1p8 {
17
62
regulator-min-microvolt = <1840000>;
18
63
regulator-max-microvolt = <1840000>;
+6
arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-apollo.dts
+6
arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-apollo.dts
+198
-3
arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi
+198
-3
arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi
···
98
98
};
99
99
};
100
100
101
+
&adsp_pas {
102
+
firmware-name = "qcom/sdm845/Sony/tama/adsp.mbn";
103
+
status = "okay";
104
+
};
105
+
101
106
&apps_rsc {
102
107
regulators-0 {
103
108
compatible = "qcom,pm8998-rpmh-regulators";
···
233
228
regulator-min-microvolt = <1800000>;
234
229
regulator-max-microvolt = <1800000>;
235
230
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
231
+
regulator-system-load = <62000>;
236
232
};
237
233
238
234
vreg_l15a_1p8: ldo15 {
···
320
314
regulator-min-microvolt = <2856000>;
321
315
regulator-max-microvolt = <3008000>;
322
316
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
317
+
regulator-system-load = <100000>;
323
318
};
324
319
325
320
vreg_lvs1a_1p8: lvs1 {
···
363
356
};
364
357
};
365
358
359
+
&cdsp_pas {
360
+
firmware-name = "qcom/sdm845/Sony/tama/cdsp.mbn";
361
+
status = "okay";
362
+
};
363
+
364
+
&dsi0 {
365
+
vdda-supply = <&vreg_l26a_1p2>;
366
+
status = "okay";
367
+
368
+
panel: panel@0 {
369
+
/* The compatible is assigned in device DTs. */
370
+
reg = <0>;
371
+
372
+
backlight = <&pmi8998_wled>;
373
+
vddio-supply = <&vreg_l14a_1p8>;
374
+
vsp-supply = <&lab>;
375
+
vsn-supply = <&ibb>;
376
+
panel-reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
377
+
touch-reset-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
378
+
379
+
pinctrl-0 = <&sde_dsi_active &sde_te_active_sleep>;
380
+
pinctrl-1 = <&sde_dsi_sleep &sde_te_active_sleep>;
381
+
pinctrl-names = "default", "sleep";
382
+
383
+
port {
384
+
panel_in: endpoint {
385
+
remote-endpoint = <&dsi0_out>;
386
+
};
387
+
};
388
+
};
389
+
};
390
+
391
+
&dsi0_out {
392
+
remote-endpoint = <&panel_in>;
393
+
data-lanes = <0 1 2 3>;
394
+
};
395
+
396
+
&dsi0_phy {
397
+
vdds-supply = <&vreg_l1a_0p9>;
398
+
status = "okay";
399
+
};
400
+
366
401
&gcc {
367
402
protected-clocks = <GCC_QSPI_CORE_CLK>,
368
403
<GCC_QSPI_CORE_CLK_SRC>,
···
413
364
<GCC_LPASS_SWAY_CLK>;
414
365
};
415
366
416
-
&i2c5 {
367
+
&gmu {
417
368
status = "okay";
418
-
clock-frequency = <400000>;
369
+
};
419
370
420
-
/* Synaptics touchscreen @ 2c, 3c */
371
+
&gpi_dma0 {
372
+
status = "okay";
373
+
};
374
+
375
+
&gpi_dma1 {
376
+
status = "okay";
377
+
};
378
+
379
+
&gpu {
380
+
status = "okay";
381
+
382
+
zap-shader {
383
+
memory-region = <&gpu_mem>;
384
+
firmware-name = "qcom/sdm845/Sony/tama/a630_zap.mbn";
385
+
};
386
+
};
387
+
388
+
&i2c5 {
389
+
clock-frequency = <400000>;
390
+
status = "okay";
391
+
392
+
touchscreen: touchscreen@2c {
393
+
compatible = "syna,rmi4-i2c";
394
+
reg = <0x2c>;
395
+
396
+
interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>;
397
+
vdd-supply = <&vreg_l14a_1p8>;
398
+
/*
399
+
* This is a blatant abuse of OF, but the panel driver *needs*
400
+
* to probe first, as the power/gpio switching needs to be precisely
401
+
* timed in order for both the display and touch panel to function properly.
402
+
*/
403
+
incell-supply = <&panel>;
404
+
405
+
syna,reset-delay-ms = <220>;
406
+
syna,startup-delay-ms = <1000>;
407
+
408
+
pinctrl-0 = <&ts_default>;
409
+
pinctrl-1 = <&ts_sleep>;
410
+
pinctrl-names = "default", "sleep";
411
+
412
+
#address-cells = <1>;
413
+
#size-cells = <0>;
414
+
415
+
rmi4-f01@1 {
416
+
reg = <0x01>;
417
+
syna,nosleep-mode = <1>;
418
+
};
419
+
420
+
rmi4-f12@12 {
421
+
reg = <0x12>;
422
+
syna,sensor-type = <1>;
423
+
};
424
+
};
421
425
};
422
426
423
427
&i2c10 {
···
488
386
489
387
/* SONY ToF sensor @ 52 */
490
388
/* AMS TCS3490 RGB+IR color sensor @ 72 */
389
+
};
390
+
391
+
&ibb {
392
+
qcom,discharge-resistor-kohms = <300>;
393
+
regulator-min-microvolt = <5500000>;
394
+
regulator-max-microvolt = <5700000>;
395
+
regulator-min-microamp = <0>;
396
+
regulator-max-microamp = <800000>;
397
+
regulator-over-current-protection;
398
+
regulator-soft-start;
399
+
regulator-pull-down;
400
+
};
401
+
402
+
&lab {
403
+
regulator-min-microvolt = <5500000>;
404
+
regulator-max-microvolt = <5700000>;
405
+
regulator-min-microamp = <200000>;
406
+
regulator-max-microamp = <200000>;
407
+
regulator-over-current-protection;
408
+
regulator-soft-start;
409
+
regulator-pull-down;
410
+
};
411
+
412
+
&mdss {
413
+
status = "okay";
491
414
};
492
415
493
416
&pm8998_gpios {
···
547
420
bias-pull-up;
548
421
input-enable;
549
422
};
423
+
};
424
+
425
+
&pmi8998_wled {
426
+
default-brightness = <800>;
427
+
qcom,switching-freq = <800>;
428
+
qcom,ovp-millivolt = <29600>;
429
+
qcom,current-boost-limit = <970>;
430
+
qcom,current-limit-microamp = <20000>;
431
+
qcom,enabled-strings = <0 1 2 3>;
432
+
status = "okay";
550
433
};
551
434
552
435
&qupv3_id_0 {
···
602
465
bias-pull-up;
603
466
};
604
467
};
468
+
469
+
sde_dsi_active: sde-dsi-active-state {
470
+
pins = "gpio6";
471
+
function = "gpio";
472
+
drive-strength = <8>;
473
+
bias-disable;
474
+
};
475
+
476
+
sde_dsi_sleep: sde-dsi-sleep-state {
477
+
pins = "gpio6";
478
+
function = "gpio";
479
+
drive-strength = <2>;
480
+
bias-pull-down;
481
+
};
482
+
483
+
sde_te_active_sleep: sde-te-active-sleep-state {
484
+
pins = "gpio10";
485
+
function = "mdp_vsync";
486
+
drive-strength = <2>;
487
+
bias-pull-down;
488
+
};
489
+
490
+
ts_default: ts-default-state {
491
+
reset-pins {
492
+
pins = "gpio99";
493
+
function = "gpio";
494
+
drive-strength = <2>;
495
+
bias-pull-up;
496
+
};
497
+
498
+
int-pins {
499
+
pins = "gpio125";
500
+
function = "gpio";
501
+
drive-strength = <2>;
502
+
bias-pull-up;
503
+
};
504
+
};
505
+
506
+
ts_sleep: ts-sleep-state {
507
+
reset-pins {
508
+
pins = "gpio99";
509
+
function = "gpio";
510
+
drive-strength = <2>;
511
+
bias-pull-down;
512
+
};
513
+
514
+
int-pins {
515
+
pins = "gpio125";
516
+
function = "gpio";
517
+
drive-strength = <2>;
518
+
bias-pull-down;
519
+
};
520
+
};
605
521
};
606
522
607
523
&uart6 {
···
689
499
vdd-supply = <&vreg_l1a_0p9>;
690
500
vdda-pll-supply = <&vreg_l12a_1p8>;
691
501
vdda-phy-dpdm-supply = <&vreg_l24a_3p1>;
502
+
};
503
+
504
+
&venus {
505
+
firmware-name = "qcom/sdm845/Sony/tama/venus.mbn";
506
+
status = "okay";
692
507
};
+11
-3
arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi
+11
-3
arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi
···
2
2
3
3
/dts-v1/;
4
4
5
+
#include <dt-bindings/leds/common.h>
5
6
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
6
7
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
7
8
#include <dt-bindings/sound/qcom,q6afe.h>
···
233
232
vddpos-supply = <&lab>;
234
233
vddneg-supply = <&ibb>;
235
234
236
-
#address-cells = <1>;
237
-
#size-cells = <0>;
238
-
239
235
backlight = <&pmi8998_wled>;
240
236
reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
241
237
···
317
319
input-enable;
318
320
bias-pull-up;
319
321
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
322
+
};
323
+
};
324
+
325
+
&pmi8998_lpg {
326
+
status = "okay";
327
+
328
+
led@5 {
329
+
reg = <5>;
330
+
color = <LED_COLOR_ID_WHITE>;
331
+
function = LED_FUNCTION_STATUS;
320
332
};
321
333
};
322
334
+1
-1
arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts
+1
-1
arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts
+30
-19
arch/arm64/boot/dts/qcom/sdm845.dtsi
+30
-19
arch/arm64/boot/dts/qcom/sdm845.dtsi
···
92
92
device_type = "cpu";
93
93
compatible = "qcom,kryo385";
94
94
reg = <0x0 0x0>;
95
+
clocks = <&cpufreq_hw 0>;
95
96
enable-method = "psci";
96
97
capacity-dmips-mhz = <611>;
97
-
dynamic-power-coefficient = <290>;
98
+
dynamic-power-coefficient = <154>;
98
99
qcom,freq-domain = <&cpufreq_hw 0>;
99
100
operating-points-v2 = <&cpu0_opp_table>;
100
101
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
···
119
118
device_type = "cpu";
120
119
compatible = "qcom,kryo385";
121
120
reg = <0x0 0x100>;
121
+
clocks = <&cpufreq_hw 0>;
122
122
enable-method = "psci";
123
123
capacity-dmips-mhz = <611>;
124
-
dynamic-power-coefficient = <290>;
124
+
dynamic-power-coefficient = <154>;
125
125
qcom,freq-domain = <&cpufreq_hw 0>;
126
126
operating-points-v2 = <&cpu0_opp_table>;
127
127
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
···
142
140
device_type = "cpu";
143
141
compatible = "qcom,kryo385";
144
142
reg = <0x0 0x200>;
143
+
clocks = <&cpufreq_hw 0>;
145
144
enable-method = "psci";
146
145
capacity-dmips-mhz = <611>;
147
-
dynamic-power-coefficient = <290>;
146
+
dynamic-power-coefficient = <154>;
148
147
qcom,freq-domain = <&cpufreq_hw 0>;
149
148
operating-points-v2 = <&cpu0_opp_table>;
150
149
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
···
165
162
device_type = "cpu";
166
163
compatible = "qcom,kryo385";
167
164
reg = <0x0 0x300>;
165
+
clocks = <&cpufreq_hw 0>;
168
166
enable-method = "psci";
169
167
capacity-dmips-mhz = <611>;
170
-
dynamic-power-coefficient = <290>;
168
+
dynamic-power-coefficient = <154>;
171
169
qcom,freq-domain = <&cpufreq_hw 0>;
172
170
operating-points-v2 = <&cpu0_opp_table>;
173
171
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
···
188
184
device_type = "cpu";
189
185
compatible = "qcom,kryo385";
190
186
reg = <0x0 0x400>;
187
+
clocks = <&cpufreq_hw 1>;
191
188
enable-method = "psci";
192
189
capacity-dmips-mhz = <1024>;
193
190
dynamic-power-coefficient = <442>;
···
211
206
device_type = "cpu";
212
207
compatible = "qcom,kryo385";
213
208
reg = <0x0 0x500>;
209
+
clocks = <&cpufreq_hw 1>;
214
210
enable-method = "psci";
215
211
capacity-dmips-mhz = <1024>;
216
212
dynamic-power-coefficient = <442>;
···
234
228
device_type = "cpu";
235
229
compatible = "qcom,kryo385";
236
230
reg = <0x0 0x600>;
231
+
clocks = <&cpufreq_hw 1>;
237
232
enable-method = "psci";
238
233
capacity-dmips-mhz = <1024>;
239
234
dynamic-power-coefficient = <442>;
···
257
250
device_type = "cpu";
258
251
compatible = "qcom,kryo385";
259
252
reg = <0x0 0x700>;
253
+
clocks = <&cpufreq_hw 1>;
260
254
enable-method = "psci";
261
255
capacity-dmips-mhz = <1024>;
262
256
dynamic-power-coefficient = <442>;
···
339
331
domain-idle-states {
340
332
CLUSTER_SLEEP_0: cluster-sleep-0 {
341
333
compatible = "domain-idle-state";
342
-
idle-state-name = "cluster-power-collapse";
343
334
arm,psci-suspend-param = <0x4100c244>;
344
335
entry-latency-us = <3263>;
345
336
exit-latency-us = <6562>;
346
337
min-residency-us = <9987>;
347
-
local-timer-stop;
348
338
};
349
339
};
350
340
};
···
2198
2192
2199
2193
llcc: system-cache-controller@1100000 {
2200
2194
compatible = "qcom,sdm845-llcc";
2201
-
reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>;
2202
-
reg-names = "llcc_base", "llcc_broadcast_base";
2195
+
reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>,
2196
+
<0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,
2197
+
<0 0x01300000 0 0x50000>;
2198
+
reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2199
+
"llcc3_base", "llcc_broadcast_base";
2203
2200
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2204
2201
};
2205
2202
···
2250
2241
};
2251
2242
2252
2243
pmu@1436400 {
2253
-
compatible = "qcom,sdm845-bwmon", "qcom,msm8998-bwmon";
2244
+
compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon";
2254
2245
reg = <0 0x01436400 0 0x600>;
2255
2246
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
2256
2247
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>;
···
2291
2282
reg = <0 0x01c00000 0 0x2000>,
2292
2283
<0 0x60000000 0 0xf1d>,
2293
2284
<0 0x60000f20 0 0xa8>,
2294
-
<0 0x60100000 0 0x100000>;
2295
-
reg-names = "parf", "dbi", "elbi", "config";
2285
+
<0 0x60100000 0 0x100000>,
2286
+
<0 0x01c07000 0 0x1000>;
2287
+
reg-names = "parf", "dbi", "elbi", "config", "mhi";
2296
2288
device_type = "pci";
2297
2289
linux,pci-domain = <0>;
2298
2290
bus-range = <0x00 0xff>;
···
2302
2292
#address-cells = <3>;
2303
2293
#size-cells = <2>;
2304
2294
2305
-
ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
2306
-
<0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>;
2295
+
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2296
+
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>;
2307
2297
2308
2298
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
2309
2299
interrupt-names = "msi";
···
2397
2387
reg = <0 0x01c08000 0 0x2000>,
2398
2388
<0 0x40000000 0 0xf1d>,
2399
2389
<0 0x40000f20 0 0xa8>,
2400
-
<0 0x40100000 0 0x100000>;
2401
-
reg-names = "parf", "dbi", "elbi", "config";
2390
+
<0 0x40100000 0 0x100000>,
2391
+
<0 0x01c0c000 0 0x1000>;
2392
+
reg-names = "parf", "dbi", "elbi", "config", "mhi";
2402
2393
device_type = "pci";
2403
2394
linux,pci-domain = <1>;
2404
2395
bus-range = <0x00 0xff>;
···
2408
2397
#address-cells = <3>;
2409
2398
#size-cells = <2>;
2410
2399
2411
-
ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
2400
+
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2412
2401
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2413
2402
2414
2403
interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
···
2628
2617
};
2629
2618
2630
2619
cryptobam: dma-controller@1dc4000 {
2631
-
compatible = "qcom,bam-v1.7.0";
2620
+
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2632
2621
reg = <0 0x01dc4000 0 0x24000>;
2633
2622
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2634
2623
clocks = <&rpmhcc RPMH_CE_CLK>;
···
4935
4924
#size-cells = <0>;
4936
4925
interrupt-controller;
4937
4926
#interrupt-cells = <4>;
4938
-
cell-index = <0>;
4939
4927
};
4940
4928
4941
4929
sram@146bf000 {
···
5232
5222
};
5233
5223
5234
5224
cpufreq_hw: cpufreq@17d43000 {
5235
-
compatible = "qcom,cpufreq-hw";
5225
+
compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
5236
5226
reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
5237
5227
reg-names = "freq-domain0", "freq-domain1";
5238
5228
···
5242
5232
clock-names = "xo", "alternate";
5243
5233
5244
5234
#freq-domain-cells = <1>;
5235
+
#clock-cells = <1>;
5245
5236
};
5246
5237
5247
5238
wifi: wifi@18800000 {
+2
-2
arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
+2
-2
arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
···
753
753
left_spkr: speaker@0,3 {
754
754
compatible = "sdw10217211000";
755
755
reg = <0 3>;
756
-
powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>;
756
+
powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_LOW>;
757
757
#thermal-sensor-cells = <0>;
758
758
sound-name-prefix = "SpkrLeft";
759
759
#sound-dai-cells = <0>;
···
761
761
762
762
right_spkr: speaker@0,4 {
763
763
compatible = "sdw10217211000";
764
-
powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_HIGH>;
764
+
powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_LOW>;
765
765
reg = <0 4>;
766
766
#thermal-sensor-cells = <0>;
767
767
sound-name-prefix = "SpkrRight";
+2
-2
arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts
+2
-2
arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts
···
662
662
left_spkr: speaker@0,3 {
663
663
compatible = "sdw10217211000";
664
664
reg = <0 3>;
665
-
powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>;
665
+
powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_LOW>;
666
666
#thermal-sensor-cells = <0>;
667
667
sound-name-prefix = "SpkrLeft";
668
668
#sound-dai-cells = <0>;
···
670
670
671
671
right_spkr: speaker@0,4 {
672
672
compatible = "sdw10217211000";
673
-
powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_HIGH>;
673
+
powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_LOW>;
674
674
reg = <0 4>;
675
675
#thermal-sensor-cells = <0>;
676
676
sound-name-prefix = "SpkrRight";
+17
-2
arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts
+17
-2
arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts
···
202
202
vqmmc-supply = <&vreg_l5a>;
203
203
204
204
cd-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>;
205
+
pinctrl-names = "default", "sleep";
206
+
pinctrl-0 = <&sdc2_state_on &sdc2_card_det_n>;
207
+
pinctrl-1 = <&sdc2_state_off &sdc2_card_det_n>;
205
208
206
209
status = "okay";
207
210
};
208
211
209
212
&tlmm {
210
213
gpio-reserved-ranges = <14 4>;
214
+
215
+
sdc2_card_det_n: sd-card-det-n-state {
216
+
pins = "gpio88";
217
+
function = "gpio";
218
+
drive-strength = <2>;
219
+
bias-pull-up;
220
+
};
211
221
};
212
222
213
223
&ufs_mem_hc {
···
235
225
status = "okay";
236
226
};
237
227
238
-
&usb_1 {
228
+
&usb {
239
229
status = "okay";
240
230
};
241
231
242
-
&usb_1_hsphy {
232
+
&usb_dwc3 {
233
+
maximum-speed = "high-speed";
234
+
dr_mode = "peripheral";
235
+
};
236
+
237
+
&usb_hsphy {
243
238
vdd-supply = <&vreg_l4a>;
244
239
vdda-pll-supply = <&vreg_l12a>;
245
240
vdda-phy-dpdm-supply = <&vreg_l15a>;
+237
-29
arch/arm64/boot/dts/qcom/sm6115.dtsi
+237
-29
arch/arm64/boot/dts/qcom/sm6115.dtsi
···
5
5
6
6
#include <dt-bindings/clock/qcom,gcc-sm6115.h>
7
7
#include <dt-bindings/clock/qcom,sm6115-dispcc.h>
8
+
#include <dt-bindings/clock/qcom,sm6115-gpucc.h>
8
9
#include <dt-bindings/clock/qcom,rpmcc.h>
9
10
#include <dt-bindings/dma/qcom-gpi.h>
10
11
#include <dt-bindings/gpio/gpio.h>
···
40
39
device_type = "cpu";
41
40
compatible = "qcom,kryo260";
42
41
reg = <0x0 0x0>;
42
+
clocks = <&cpufreq_hw 0>;
43
43
capacity-dmips-mhz = <1024>;
44
44
dynamic-power-coefficient = <100>;
45
45
enable-method = "psci";
···
56
54
device_type = "cpu";
57
55
compatible = "qcom,kryo260";
58
56
reg = <0x0 0x1>;
57
+
clocks = <&cpufreq_hw 0>;
59
58
capacity-dmips-mhz = <1024>;
60
59
dynamic-power-coefficient = <100>;
61
60
enable-method = "psci";
···
68
65
device_type = "cpu";
69
66
compatible = "qcom,kryo260";
70
67
reg = <0x0 0x2>;
68
+
clocks = <&cpufreq_hw 0>;
71
69
capacity-dmips-mhz = <1024>;
72
70
dynamic-power-coefficient = <100>;
73
71
enable-method = "psci";
···
80
76
device_type = "cpu";
81
77
compatible = "qcom,kryo260";
82
78
reg = <0x0 0x3>;
79
+
clocks = <&cpufreq_hw 0>;
83
80
capacity-dmips-mhz = <1024>;
84
81
dynamic-power-coefficient = <100>;
85
82
enable-method = "psci";
···
92
87
device_type = "cpu";
93
88
compatible = "qcom,kryo260";
94
89
reg = <0x0 0x100>;
90
+
clocks = <&cpufreq_hw 1>;
95
91
enable-method = "psci";
96
92
capacity-dmips-mhz = <1638>;
97
93
dynamic-power-coefficient = <282>;
···
108
102
device_type = "cpu";
109
103
compatible = "qcom,kryo260";
110
104
reg = <0x0 0x101>;
105
+
clocks = <&cpufreq_hw 1>;
111
106
capacity-dmips-mhz = <1638>;
112
107
dynamic-power-coefficient = <282>;
113
108
enable-method = "psci";
···
120
113
device_type = "cpu";
121
114
compatible = "qcom,kryo260";
122
115
reg = <0x0 0x102>;
116
+
clocks = <&cpufreq_hw 1>;
123
117
capacity-dmips-mhz = <1638>;
124
118
dynamic-power-coefficient = <282>;
125
119
enable-method = "psci";
···
132
124
device_type = "cpu";
133
125
compatible = "qcom,kryo260";
134
126
reg = <0x0 0x103>;
127
+
clocks = <&cpufreq_hw 1>;
135
128
capacity-dmips-mhz = <1638>;
136
129
dynamic-power-coefficient = <282>;
137
130
enable-method = "psci";
···
604
595
bias-pull-up;
605
596
drive-strength = <10>;
606
597
};
607
-
608
-
sd-cd-pins {
609
-
pins = "gpio88";
610
-
function = "gpio";
611
-
bias-pull-up;
612
-
drive-strength = <2>;
613
-
};
614
598
};
615
599
616
600
sdc2_state_off: sdc2-off-state {
···
624
622
bias-pull-up;
625
623
drive-strength = <2>;
626
624
};
627
-
628
-
sd-cd-pins {
629
-
pins = "gpio88";
630
-
function = "gpio";
631
-
bias-disable;
632
-
drive-strength = <2>;
633
-
};
634
625
};
635
626
};
636
627
···
637
642
#power-domain-cells = <1>;
638
643
};
639
644
640
-
usb_1_hsphy: phy@1613000 {
645
+
usb_hsphy: phy@1613000 {
641
646
compatible = "qcom,sm6115-qusb2-phy";
642
647
reg = <0x0 0x01613000 0x0 0x180>;
643
648
#phy-cells = <0>;
···
726
731
<&gcc GCC_SDCC1_ICE_CORE_CLK>;
727
732
clock-names = "iface", "core", "xo", "ice";
728
733
729
-
pinctrl-0 = <&sdc1_state_on>;
730
-
pinctrl-1 = <&sdc1_state_off>;
731
-
pinctrl-names = "default", "sleep";
732
-
733
734
bus-width = <8>;
734
735
status = "disabled";
735
736
};
···
743
752
<&gcc GCC_SDCC2_APPS_CLK>,
744
753
<&rpmcc RPM_SMD_XO_CLK_SRC>;
745
754
clock-names = "iface", "core", "xo";
746
-
747
-
pinctrl-0 = <&sdc2_state_on>;
748
-
pinctrl-1 = <&sdc2_state_off>;
749
-
pinctrl-names = "default", "sleep";
750
755
751
756
power-domains = <&rpmpd SM6115_VDDCX>;
752
757
operating-points-v2 = <&sdhc2_opp_table>;
···
1065
1078
dma-names = "tx", "rx";
1066
1079
#address-cells = <1>;
1067
1080
#size-cells = <0>;
1081
+
status = "disabled";
1068
1082
};
1069
1083
};
1070
1084
1071
-
usb_1: usb@4ef8800 {
1085
+
usb: usb@4ef8800 {
1072
1086
compatible = "qcom,sm6115-dwc3", "qcom,dwc3";
1073
1087
reg = <0x0 0x04ef8800 0x0 0x400>;
1074
1088
#address-cells = <2>;
···
1097
1109
qcom,select-utmi-as-pipe-clk;
1098
1110
status = "disabled";
1099
1111
1100
-
usb_1_dwc3: usb@4e00000 {
1112
+
usb_dwc3: usb@4e00000 {
1101
1113
compatible = "snps,dwc3";
1102
1114
reg = <0x0 0x04e00000 0x0 0xcd00>;
1103
1115
interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1104
-
phys = <&usb_1_hsphy>;
1116
+
phys = <&usb_hsphy>;
1105
1117
phy-names = "usb2-phy";
1106
1118
iommus = <&apps_smmu 0x120 0x0>;
1107
1119
snps,dis_u2_susphy_quirk;
···
1109
1121
snps,has-lpm-erratum;
1110
1122
snps,hird-threshold = /bits/ 8 <0x10>;
1111
1123
snps,usb3_lpm_capable;
1112
-
maximum-speed = "high-speed";
1113
-
dr_mode = "peripheral";
1114
1124
};
1125
+
};
1126
+
1127
+
gpucc: clock-controller@5990000 {
1128
+
compatible = "qcom,sm6115-gpucc";
1129
+
reg = <0x0 0x05990000 0x0 0x9000>;
1130
+
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1131
+
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
1132
+
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1133
+
#clock-cells = <1>;
1134
+
#reset-cells = <1>;
1135
+
#power-domain-cells = <1>;
1136
+
};
1137
+
1138
+
adreno_smmu: iommu@59a0000 {
1139
+
compatible = "qcom,sm6115-smmu-500", "qcom,adreno-smmu",
1140
+
"qcom,smmu-500", "arm,mmu-500";
1141
+
reg = <0x0 0x059a0000 0x0 0x10000>;
1142
+
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1143
+
<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
1144
+
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
1145
+
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
1146
+
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1147
+
<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
1148
+
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
1149
+
<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
1150
+
<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1151
+
1152
+
clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1153
+
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
1154
+
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
1155
+
clock-names = "mem",
1156
+
"hlos",
1157
+
"iface";
1158
+
power-domains = <&gpucc GPU_CX_GDSC>;
1159
+
1160
+
#global-interrupts = <1>;
1161
+
#iommu-cells = <2>;
1115
1162
};
1116
1163
1117
1164
mdss: display-subsystem@5e00000 {
···
1343
1320
#clock-cells = <1>;
1344
1321
#reset-cells = <1>;
1345
1322
#power-domain-cells = <1>;
1323
+
};
1324
+
1325
+
remoteproc_mpss: remoteproc@6080000 {
1326
+
compatible = "qcom,sm6115-mpss-pas";
1327
+
reg = <0x0 0x06080000 0x0 0x100>;
1328
+
1329
+
interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
1330
+
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1331
+
<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1332
+
<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1333
+
<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1334
+
<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1335
+
interrupt-names = "wdog", "fatal", "ready", "handover",
1336
+
"stop-ack", "shutdown-ack";
1337
+
1338
+
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1339
+
clock-names = "xo";
1340
+
1341
+
power-domains = <&rpmpd SM6115_VDDCX>;
1342
+
1343
+
memory-region = <&pil_modem_mem>;
1344
+
1345
+
qcom,smem-states = <&modem_smp2p_out 0>;
1346
+
qcom,smem-state-names = "stop";
1347
+
1348
+
status = "disabled";
1349
+
1350
+
glink-edge {
1351
+
interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
1352
+
label = "mpss";
1353
+
qcom,remote-pid = <1>;
1354
+
mboxes = <&apcs_glb 12>;
1355
+
};
1346
1356
};
1347
1357
1348
1358
stm@8002000 {
···
1990
1934
};
1991
1935
};
1992
1936
1937
+
remoteproc_adsp: remoteproc@ab00000 {
1938
+
compatible = "qcom,sm6115-adsp-pas";
1939
+
reg = <0x0 0x0ab00000 0x0 0x100>;
1940
+
1941
+
interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
1942
+
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1943
+
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1944
+
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1945
+
<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1946
+
interrupt-names = "wdog", "fatal", "ready",
1947
+
"handover", "stop-ack";
1948
+
1949
+
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1950
+
clock-names = "xo";
1951
+
1952
+
power-domains = <&rpmpd SM6115_VDD_LPI_CX>,
1953
+
<&rpmpd SM6115_VDD_LPI_MX>;
1954
+
1955
+
memory-region = <&pil_adsp_mem>;
1956
+
1957
+
qcom,smem-states = <&adsp_smp2p_out 0>;
1958
+
qcom,smem-state-names = "stop";
1959
+
1960
+
status = "disabled";
1961
+
1962
+
glink-edge {
1963
+
interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
1964
+
label = "lpass";
1965
+
qcom,remote-pid = <2>;
1966
+
mboxes = <&apcs_glb 8>;
1967
+
1968
+
fastrpc {
1969
+
compatible = "qcom,fastrpc";
1970
+
qcom,glink-channels = "fastrpcglink-apps-dsp";
1971
+
label = "adsp";
1972
+
qcom,non-secure-domain;
1973
+
#address-cells = <1>;
1974
+
#size-cells = <0>;
1975
+
1976
+
compute-cb@3 {
1977
+
compatible = "qcom,fastrpc-compute-cb";
1978
+
reg = <3>;
1979
+
iommus = <&apps_smmu 0x01c3 0x0>;
1980
+
};
1981
+
1982
+
compute-cb@4 {
1983
+
compatible = "qcom,fastrpc-compute-cb";
1984
+
reg = <4>;
1985
+
iommus = <&apps_smmu 0x01c4 0x0>;
1986
+
};
1987
+
1988
+
compute-cb@5 {
1989
+
compatible = "qcom,fastrpc-compute-cb";
1990
+
reg = <5>;
1991
+
iommus = <&apps_smmu 0x01c5 0x0>;
1992
+
};
1993
+
1994
+
compute-cb@6 {
1995
+
compatible = "qcom,fastrpc-compute-cb";
1996
+
reg = <6>;
1997
+
iommus = <&apps_smmu 0x01c6 0x0>;
1998
+
};
1999
+
2000
+
compute-cb@7 {
2001
+
compatible = "qcom,fastrpc-compute-cb";
2002
+
reg = <7>;
2003
+
iommus = <&apps_smmu 0x01c7 0x0>;
2004
+
};
2005
+
};
2006
+
};
2007
+
};
2008
+
2009
+
remoteproc_cdsp: remoteproc@b300000 {
2010
+
compatible = "qcom,sm6115-cdsp-pas";
2011
+
reg = <0x0 0x0b300000 0x0 0x100000>;
2012
+
2013
+
interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
2014
+
<&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2015
+
<&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2016
+
<&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2017
+
<&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2018
+
interrupt-names = "wdog", "fatal", "ready",
2019
+
"handover", "stop-ack";
2020
+
2021
+
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2022
+
clock-names = "xo";
2023
+
2024
+
power-domains = <&rpmpd SM6115_VDDCX>;
2025
+
2026
+
memory-region = <&pil_cdsp_mem>;
2027
+
2028
+
qcom,smem-states = <&cdsp_smp2p_out 0>;
2029
+
qcom,smem-state-names = "stop";
2030
+
2031
+
status = "disabled";
2032
+
2033
+
glink-edge {
2034
+
interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>;
2035
+
label = "cdsp";
2036
+
qcom,remote-pid = <5>;
2037
+
mboxes = <&apcs_glb 28>;
2038
+
2039
+
fastrpc {
2040
+
compatible = "qcom,fastrpc";
2041
+
qcom,glink-channels = "fastrpcglink-apps-dsp";
2042
+
label = "cdsp";
2043
+
qcom,non-secure-domain;
2044
+
#address-cells = <1>;
2045
+
#size-cells = <0>;
2046
+
2047
+
compute-cb@1 {
2048
+
compatible = "qcom,fastrpc-compute-cb";
2049
+
reg = <1>;
2050
+
iommus = <&apps_smmu 0x0c01 0x0>;
2051
+
};
2052
+
2053
+
compute-cb@2 {
2054
+
compatible = "qcom,fastrpc-compute-cb";
2055
+
reg = <2>;
2056
+
iommus = <&apps_smmu 0x0c02 0x0>;
2057
+
};
2058
+
2059
+
compute-cb@3 {
2060
+
compatible = "qcom,fastrpc-compute-cb";
2061
+
reg = <3>;
2062
+
iommus = <&apps_smmu 0x0c03 0x0>;
2063
+
};
2064
+
2065
+
compute-cb@4 {
2066
+
compatible = "qcom,fastrpc-compute-cb";
2067
+
reg = <4>;
2068
+
iommus = <&apps_smmu 0x0c04 0x0>;
2069
+
};
2070
+
2071
+
compute-cb@5 {
2072
+
compatible = "qcom,fastrpc-compute-cb";
2073
+
reg = <5>;
2074
+
iommus = <&apps_smmu 0x0c05 0x0>;
2075
+
};
2076
+
2077
+
compute-cb@6 {
2078
+
compatible = "qcom,fastrpc-compute-cb";
2079
+
reg = <6>;
2080
+
iommus = <&apps_smmu 0x0c06 0x0>;
2081
+
};
2082
+
2083
+
/* note: secure cb9 in downstream */
2084
+
};
2085
+
};
2086
+
};
2087
+
1993
2088
apps_smmu: iommu@c600000 {
1994
2089
compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1995
2090
reg = <0x0 0x0c600000 0x0 0x80000>;
···
2321
2114
};
2322
2115
2323
2116
cpufreq_hw: cpufreq@f521000 {
2324
-
compatible = "qcom,cpufreq-hw";
2117
+
compatible = "qcom,sm6115-cpufreq-hw", "qcom,cpufreq-hw";
2325
2118
reg = <0x0 0x0f521000 0x0 0x1000>,
2326
2119
<0x0 0x0f523000 0x0 0x1000>;
2327
2120
···
2330
2123
clock-names = "xo", "alternate";
2331
2124
2332
2125
#freq-domain-cells = <1>;
2126
+
#clock-cells = <1>;
2333
2127
};
2334
2128
};
2335
2129
+8
-3
arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts
+8
-3
arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts
···
49
49
gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>;
50
50
debounce-interval = <15>;
51
51
linux,can-disable;
52
-
gpio-key,wakeup;
52
+
wakeup-source;
53
53
};
54
54
};
55
55
};
···
273
273
status = "okay";
274
274
};
275
275
276
-
&usb_1 {
276
+
&usb {
277
277
status = "okay";
278
278
};
279
279
280
-
&usb_1_hsphy {
280
+
&usb_dwc3 {
281
+
maximum-speed = "high-speed";
282
+
dr_mode = "peripheral";
283
+
};
284
+
285
+
&usb_hsphy {
281
286
vdd-supply = <&pm6125_l4>;
282
287
vdda-pll-supply = <&pm6125_l12>;
283
288
vdda-phy-dpdm-supply = <&pm6125_l15>;
-1
arch/arm64/boot/dts/qcom/sm6125.dtsi
-1
arch/arm64/boot/dts/qcom/sm6125.dtsi
-2
arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts
-2
arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts
···
233
233
regulator-allow-set-load;
234
234
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
235
235
RPMH_REGULATOR_MODE_HPM>;
236
-
237
236
};
238
237
239
238
pm6150l_l7: ldo7 {
···
254
255
regulator-allow-set-load;
255
256
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
256
257
RPMH_REGULATOR_MODE_HPM>;
257
-
258
258
};
259
259
260
260
pm6150l_l10: ldo10 {
+11
-4
arch/arm64/boot/dts/qcom/sm6350.dtsi
+11
-4
arch/arm64/boot/dts/qcom/sm6350.dtsi
···
46
46
device_type = "cpu";
47
47
compatible = "qcom,kryo560";
48
48
reg = <0x0 0x0>;
49
+
clocks = <&cpufreq_hw 0>;
49
50
enable-method = "psci";
50
51
capacity-dmips-mhz = <1024>;
51
52
dynamic-power-coefficient = <100>;
···
72
71
device_type = "cpu";
73
72
compatible = "qcom,kryo560";
74
73
reg = <0x0 0x100>;
74
+
clocks = <&cpufreq_hw 0>;
75
75
enable-method = "psci";
76
76
capacity-dmips-mhz = <1024>;
77
77
dynamic-power-coefficient = <100>;
···
94
92
device_type = "cpu";
95
93
compatible = "qcom,kryo560";
96
94
reg = <0x0 0x200>;
95
+
clocks = <&cpufreq_hw 0>;
97
96
enable-method = "psci";
98
97
capacity-dmips-mhz = <1024>;
99
98
dynamic-power-coefficient = <100>;
···
116
113
device_type = "cpu";
117
114
compatible = "qcom,kryo560";
118
115
reg = <0x0 0x300>;
116
+
clocks = <&cpufreq_hw 0>;
119
117
enable-method = "psci";
120
118
capacity-dmips-mhz = <1024>;
121
119
dynamic-power-coefficient = <100>;
···
138
134
device_type = "cpu";
139
135
compatible = "qcom,kryo560";
140
136
reg = <0x0 0x400>;
137
+
clocks = <&cpufreq_hw 0>;
141
138
enable-method = "psci";
142
139
capacity-dmips-mhz = <1024>;
143
140
dynamic-power-coefficient = <100>;
···
160
155
device_type = "cpu";
161
156
compatible = "qcom,kryo560";
162
157
reg = <0x0 0x500>;
158
+
clocks = <&cpufreq_hw 0>;
163
159
enable-method = "psci";
164
160
capacity-dmips-mhz = <1024>;
165
161
dynamic-power-coefficient = <100>;
···
176
170
cache-level = <2>;
177
171
next-level-cache = <&L3_0>;
178
172
};
179
-
180
173
};
181
174
182
175
CPU6: cpu@600 {
183
176
device_type = "cpu";
184
177
compatible = "qcom,kryo560";
185
178
reg = <0x0 0x600>;
179
+
clocks = <&cpufreq_hw 1>;
186
180
enable-method = "psci";
187
181
capacity-dmips-mhz = <1894>;
188
182
dynamic-power-coefficient = <703>;
···
204
198
device_type = "cpu";
205
199
compatible = "qcom,kryo560";
206
200
reg = <0x0 0x700>;
201
+
clocks = <&cpufreq_hw 1>;
207
202
enable-method = "psci";
208
203
capacity-dmips-mhz = <1894>;
209
204
dynamic-power-coefficient = <703>;
···
887
880
interconnect-names = "qup-core", "qup-config", "qup-memory";
888
881
status = "disabled";
889
882
};
890
-
891
883
};
892
884
893
885
config_noc: interconnect@1500000 {
···
1354
1348
system-cache-controller@9200000 {
1355
1349
compatible = "qcom,sm6350-llcc";
1356
1350
reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
1357
-
reg-names = "llcc_base", "llcc_broadcast_base";
1351
+
reg-names = "llcc0_base", "llcc_broadcast_base";
1358
1352
};
1359
1353
1360
1354
gem_noc: interconnect@9680000 {
···
2001
1995
};
2002
1996
2003
1997
cpufreq_hw: cpufreq@18323000 {
2004
-
compatible = "qcom,cpufreq-hw";
1998
+
compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw";
2005
1999
reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>;
2006
2000
reg-names = "freq-domain0", "freq-domain1";
2007
2001
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
2008
2002
clock-names = "xo", "alternate";
2009
2003
2010
2004
#freq-domain-cells = <1>;
2005
+
#clock-cells = <1>;
2011
2006
};
2012
2007
};
2013
2008
+27
arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts
+27
arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts
···
46
46
};
47
47
};
48
48
49
+
gpio-keys {
50
+
compatible = "gpio-keys";
51
+
label = "gpio-keys";
52
+
53
+
pinctrl-0 = <&vol_down_n>;
54
+
pinctrl-names = "default";
55
+
56
+
key-volume-down {
57
+
label = "Volume Down";
58
+
linux,code = <KEY_VOLUMEDOWN>;
59
+
gpios = <&pmr735a_gpios 1 GPIO_ACTIVE_LOW>;
60
+
debounce-interval = <15>;
61
+
linux,can-disable;
62
+
wakeup-source;
63
+
};
64
+
};
65
+
49
66
reserved-memory {
50
67
cont_splash_mem: memory@85200000 {
51
68
reg = <0 0x85200000 0 0xc00000>;
···
148
131
149
132
&pmk8350_rtc {
150
133
status = "okay";
134
+
};
135
+
136
+
&pmr735a_gpios {
137
+
vol_down_n: vol-down-n-state {
138
+
pins = "gpio1";
139
+
function = "normal";
140
+
power-source = <1>;
141
+
bias-pull-up;
142
+
input-enable;
143
+
};
151
144
};
152
145
153
146
&pon_pwrkey {
+906
-11
arch/arm64/boot/dts/qcom/sm6375.dtsi
+906
-11
arch/arm64/boot/dts/qcom/sm6375.dtsi
···
6
6
#include <dt-bindings/clock/qcom,rpmcc.h>
7
7
#include <dt-bindings/clock/qcom,sm6375-gcc.h>
8
8
#include <dt-bindings/dma/qcom-gpi.h>
9
+
#include <dt-bindings/firmware/qcom,scm.h>
9
10
#include <dt-bindings/interrupt-controller/arm-gic.h>
10
11
#include <dt-bindings/mailbox/qcom-ipcc.h>
11
12
#include <dt-bindings/power/qcom-rpmpd.h>
···
40
39
device_type = "cpu";
41
40
compatible = "qcom,kryo660";
42
41
reg = <0x0 0x0>;
42
+
clocks = <&cpufreq_hw 0>;
43
43
enable-method = "psci";
44
44
next-level-cache = <&L2_0>;
45
45
qcom,freq-domain = <&cpufreq_hw 0>;
···
60
58
device_type = "cpu";
61
59
compatible = "qcom,kryo660";
62
60
reg = <0x0 0x100>;
61
+
clocks = <&cpufreq_hw 0>;
63
62
enable-method = "psci";
64
63
next-level-cache = <&L2_100>;
65
64
qcom,freq-domain = <&cpufreq_hw 0>;
···
77
74
device_type = "cpu";
78
75
compatible = "qcom,kryo660";
79
76
reg = <0x0 0x200>;
77
+
clocks = <&cpufreq_hw 0>;
80
78
enable-method = "psci";
81
79
next-level-cache = <&L2_200>;
82
80
qcom,freq-domain = <&cpufreq_hw 0>;
···
94
90
device_type = "cpu";
95
91
compatible = "qcom,kryo660";
96
92
reg = <0x0 0x300>;
93
+
clocks = <&cpufreq_hw 0>;
97
94
enable-method = "psci";
98
95
next-level-cache = <&L2_300>;
99
96
qcom,freq-domain = <&cpufreq_hw 0>;
···
111
106
device_type = "cpu";
112
107
compatible = "qcom,kryo660";
113
108
reg = <0x0 0x400>;
109
+
clocks = <&cpufreq_hw 0>;
114
110
enable-method = "psci";
115
111
next-level-cache = <&L2_400>;
116
112
qcom,freq-domain = <&cpufreq_hw 0>;
···
128
122
device_type = "cpu";
129
123
compatible = "qcom,kryo660";
130
124
reg = <0x0 0x500>;
125
+
clocks = <&cpufreq_hw 0>;
131
126
enable-method = "psci";
132
127
next-level-cache = <&L2_500>;
133
128
qcom,freq-domain = <&cpufreq_hw 0>;
···
139
132
compatible = "cache";
140
133
next-level-cache = <&L3_0>;
141
134
};
142
-
143
135
};
144
136
145
137
CPU6: cpu@600 {
146
138
device_type = "cpu";
147
139
compatible = "qcom,kryo660";
148
140
reg = <0x0 0x600>;
141
+
clocks = <&cpufreq_hw 1>;
149
142
enable-method = "psci";
150
143
next-level-cache = <&L2_600>;
151
144
qcom,freq-domain = <&cpufreq_hw 1>;
···
162
155
device_type = "cpu";
163
156
compatible = "qcom,kryo660";
164
157
reg = <0x0 0x700>;
158
+
clocks = <&cpufreq_hw 1>;
165
159
enable-method = "psci";
166
160
next-level-cache = <&L2_700>;
167
161
qcom,freq-domain = <&cpufreq_hw 1>;
···
216
208
217
209
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
218
210
compatible = "arm,idle-state";
211
+
idle-state-name = "silver-power-collapse";
212
+
arm,psci-suspend-param = <0x40000003>;
213
+
entry-latency-us = <549>;
214
+
exit-latency-us = <901>;
215
+
min-residency-us = <1774>;
216
+
local-timer-stop;
217
+
};
218
+
219
+
LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
220
+
compatible = "arm,idle-state";
219
221
idle-state-name = "silver-rail-power-collapse";
220
222
arm,psci-suspend-param = <0x40000004>;
221
223
entry-latency-us = <702>;
···
235
217
};
236
218
237
219
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
220
+
compatible = "arm,idle-state";
221
+
idle-state-name = "gold-power-collapse";
222
+
arm,psci-suspend-param = <0x40000003>;
223
+
entry-latency-us = <523>;
224
+
exit-latency-us = <1244>;
225
+
min-residency-us = <2207>;
226
+
local-timer-stop;
227
+
};
228
+
229
+
BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
238
230
compatible = "arm,idle-state";
239
231
idle-state-name = "gold-rail-power-collapse";
240
232
arm,psci-suspend-param = <0x40000004>;
···
258
230
domain-idle-states {
259
231
CLUSTER_SLEEP_0: cluster-sleep-0 {
260
232
compatible = "domain-idle-state";
261
-
idle-state-name = "cluster-power-collapse";
262
233
arm,psci-suspend-param = <0x41000044>;
263
234
entry-latency-us = <2752>;
264
235
exit-latency-us = <3048>;
265
236
min-residency-us = <6118>;
266
-
local-timer-stop;
267
237
};
268
238
};
269
239
};
···
293
267
CPU_PD0: power-domain-cpu0 {
294
268
#power-domain-cells = <0>;
295
269
power-domains = <&CLUSTER_PD>;
296
-
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
270
+
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
297
271
};
298
272
299
273
CPU_PD1: power-domain-cpu1 {
300
274
#power-domain-cells = <0>;
301
275
power-domains = <&CLUSTER_PD>;
302
-
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
276
+
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
303
277
};
304
278
305
279
CPU_PD2: power-domain-cpu2 {
306
280
#power-domain-cells = <0>;
307
281
power-domains = <&CLUSTER_PD>;
308
-
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
282
+
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
309
283
};
310
284
311
285
CPU_PD3: power-domain-cpu3 {
312
286
#power-domain-cells = <0>;
313
287
power-domains = <&CLUSTER_PD>;
314
-
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
288
+
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
315
289
};
316
290
317
291
CPU_PD4: power-domain-cpu4 {
318
292
#power-domain-cells = <0>;
319
293
power-domains = <&CLUSTER_PD>;
320
-
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
294
+
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
321
295
};
322
296
323
297
CPU_PD5: power-domain-cpu5 {
324
298
#power-domain-cells = <0>;
325
299
power-domains = <&CLUSTER_PD>;
326
-
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
300
+
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
327
301
};
328
302
329
303
CPU_PD6: power-domain-cpu6 {
330
304
#power-domain-cells = <0>;
331
305
power-domains = <&CLUSTER_PD>;
332
-
domain-idle-states = <&BIG_CPU_SLEEP_0>;
306
+
domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
333
307
};
334
308
335
309
CPU_PD7: power-domain-cpu7 {
336
310
#power-domain-cells = <0>;
337
311
power-domains = <&CLUSTER_PD>;
338
-
domain-idle-states = <&BIG_CPU_SLEEP_0>;
312
+
domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
339
313
};
340
314
341
315
CLUSTER_PD: power-domain-cpu-cluster0 {
···
448
422
removed_mem: removed@c0000000 {
449
423
reg = <0 0xc0000000 0 0x5100000>;
450
424
no-map;
425
+
};
426
+
427
+
rmtfs_mem: rmtfs@f3900000 {
428
+
compatible = "qcom,rmtfs-mem";
429
+
reg = <0 0xf3900000 0 0x280000>;
430
+
no-map;
431
+
432
+
qcom,client-id = <1>;
433
+
qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>;
451
434
};
452
435
453
436
debug_mem: debug@ffb00000 {
···
585
550
586
551
smp2p_cdsp_in: slave-kernel {
587
552
qcom,entry-name = "slave-kernel";
553
+
interrupt-controller;
554
+
#interrupt-cells = <2>;
555
+
};
556
+
};
557
+
558
+
smp2p-modem {
559
+
compatible = "qcom,smp2p";
560
+
qcom,smem = <435>, <428>;
561
+
interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
562
+
IPCC_MPROC_SIGNAL_SMP2P
563
+
IRQ_TYPE_EDGE_RISING>;
564
+
mboxes = <&ipcc IPCC_CLIENT_MPSS
565
+
IPCC_MPROC_SIGNAL_SMP2P>;
566
+
567
+
qcom,local-pid = <0>;
568
+
qcom,remote-pid = <1>;
569
+
570
+
smp2p_modem_out: master-kernel {
571
+
qcom,entry-name = "master-kernel";
572
+
#qcom,smem-state-cells = <1>;
573
+
};
574
+
575
+
smp2p_modem_in: slave-kernel {
576
+
qcom,entry-name = "slave-kernel";
577
+
interrupt-controller;
578
+
#interrupt-cells = <2>;
579
+
};
580
+
581
+
ipa_smp2p_out: ipa-ap-to-modem {
582
+
qcom,entry-name = "ipa";
583
+
#qcom,smem-state-cells = <1>;
584
+
};
585
+
586
+
ipa_smp2p_in: ipa-modem-to-ap {
587
+
qcom,entry-name = "ipa";
588
+
interrupt-controller;
589
+
#interrupt-cells = <2>;
590
+
};
591
+
592
+
wlan_smp2p_in: wlan-wpss-to-ap {
593
+
qcom,entry-name = "wlan";
588
594
interrupt-controller;
589
595
#interrupt-cells = <2>;
590
596
};
···
789
713
#interrupt-cells = <4>;
790
714
};
791
715
716
+
tsens0: thermal-sensor@4411000 {
717
+
compatible = "qcom,sm6375-tsens", "qcom,tsens-v2";
718
+
reg = <0 0x04411000 0 0x140>, /* TM */
719
+
<0 0x04410000 0 0x20>; /* SROT */
720
+
interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
721
+
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
722
+
interrupt-names = "uplow", "critical";
723
+
#thermal-sensor-cells = <1>;
724
+
#qcom,sensors = <15>;
725
+
};
726
+
727
+
tsens1: thermal-sensor@4413000 {
728
+
compatible = "qcom,sm6375-tsens", "qcom,tsens-v2";
729
+
reg = <0 0x04413000 0 0x140>, /* TM */
730
+
<0 0x04412000 0 0x20>; /* SROT */
731
+
interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
732
+
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
733
+
interrupt-names = "uplow", "critical";
734
+
#thermal-sensor-cells = <1>;
735
+
#qcom,sensors = <11>;
736
+
};
737
+
792
738
rpm_msg_ram: sram@45f0000 {
793
739
compatible = "qcom,rpm-msg-ram";
794
740
reg = <0 0x045f0000 0 0x7000>;
741
+
};
742
+
743
+
sram@4690000 {
744
+
compatible = "qcom,rpm-stats";
745
+
reg = <0 0x04690000 0 0x400>;
795
746
};
796
747
797
748
sdhc_2: mmc@4784000 {
···
1258
1155
};
1259
1156
};
1260
1157
1158
+
remoteproc_mss: remoteproc@6000000 {
1159
+
compatible = "qcom,sm6375-mpss-pas";
1160
+
reg = <0 0x06000000 0 0x4040>;
1161
+
1162
+
interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
1163
+
<&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
1164
+
<&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
1165
+
<&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
1166
+
<&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
1167
+
<&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
1168
+
interrupt-names = "wdog",
1169
+
"fatal",
1170
+
"ready",
1171
+
"handover",
1172
+
"stop-ack",
1173
+
"shutdown-ack";
1174
+
1175
+
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1176
+
clock-names = "xo";
1177
+
1178
+
power-domains = <&rpmpd SM6375_VDDCX>;
1179
+
power-domain-names = "cx";
1180
+
1181
+
memory-region = <&pil_mpss_wlan_mem>;
1182
+
1183
+
qcom,smem-states = <&smp2p_modem_out 0>;
1184
+
qcom,smem-state-names = "stop";
1185
+
1186
+
status = "disabled";
1187
+
1188
+
glink-edge {
1189
+
interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
1190
+
IPCC_MPROC_SIGNAL_GLINK_QMP
1191
+
IRQ_TYPE_EDGE_RISING>;
1192
+
mboxes = <&ipcc IPCC_CLIENT_MPSS
1193
+
IPCC_MPROC_SIGNAL_GLINK_QMP>;
1194
+
label = "modem";
1195
+
qcom,remote-pid = <1>;
1196
+
};
1197
+
};
1198
+
1261
1199
remoteproc_adsp: remoteproc@a400000 {
1262
1200
compatible = "qcom,sm6375-adsp-pas";
1263
1201
reg = <0 0x0a400000 0 0x100>;
···
1353
1209
clock-names = "xo";
1354
1210
1355
1211
power-domains = <&rpmpd SM6375_VDDCX>;
1212
+
power-domain-names = "cx";
1356
1213
1357
1214
memory-region = <&pil_cdsp_mem>;
1358
1215
···
1370
1225
IPCC_MPROC_SIGNAL_GLINK_QMP>;
1371
1226
label = "cdsp";
1372
1227
qcom,remote-pid = <5>;
1228
+
};
1229
+
};
1230
+
1231
+
sram@c125000 {
1232
+
compatible = "qcom,sm6375-imem", "syscon", "simple-mfd";
1233
+
reg = <0 0x0c125000 0 0x1000>;
1234
+
ranges = <0 0 0x0c125000 0x1000>;
1235
+
1236
+
#address-cells = <1>;
1237
+
#size-cells = <1>;
1238
+
1239
+
pil-reloc@94c {
1240
+
compatible = "qcom,pil-reloc-info";
1241
+
reg = <0x94c 0xc8>;
1373
1242
};
1374
1243
};
1375
1244
···
1463
1304
#iommu-cells = <2>;
1464
1305
};
1465
1306
1307
+
wifi: wifi@c800000 {
1308
+
compatible = "qcom,wcn3990-wifi";
1309
+
reg = <0 0x0c800000 0 0x800000>;
1310
+
reg-names = "membase";
1311
+
memory-region = <&pil_wlan_mem>;
1312
+
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
1313
+
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
1314
+
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
1315
+
<GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
1316
+
<GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
1317
+
<GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
1318
+
<GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
1319
+
<GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
1320
+
<GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
1321
+
<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
1322
+
<GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
1323
+
<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
1324
+
iommus = <&apps_smmu 0x80 0x1>;
1325
+
qcom,msa-fixed-perm;
1326
+
status = "disabled";
1327
+
};
1328
+
1466
1329
intc: interrupt-controller@f200000 {
1467
1330
compatible = "arm,gic-v3";
1468
1331
reg = <0x0 0x0f200000 0x0 0x10000>, /* GICD */
···
1553
1372
};
1554
1373
};
1555
1374
1375
+
cpucp_l3: interconnect@fd90000 {
1376
+
compatible = "qcom,sm6375-cpucp-l3", "qcom,epss-l3";
1377
+
reg = <0 0x0fd90000 0 0x1000>;
1378
+
1379
+
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
1380
+
clock-names = "xo", "alternate";
1381
+
#interconnect-cells = <1>;
1382
+
};
1383
+
1556
1384
cpufreq_hw: cpufreq@fd91000 {
1557
1385
compatible = "qcom,sm6375-cpufreq-epss", "qcom,cpufreq-epss";
1558
1386
reg = <0 0x0fd91000 0 0x1000>, <0 0x0fd92000 0 0x1000>;
···
1573
1383
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1574
1384
interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1";
1575
1385
#freq-domain-cells = <1>;
1386
+
#clock-cells = <1>;
1387
+
};
1388
+
};
1389
+
1390
+
thermal-zones {
1391
+
mapss0-thermal {
1392
+
polling-delay-passive = <0>;
1393
+
polling-delay = <0>;
1394
+
1395
+
thermal-sensors = <&tsens0 0>;
1396
+
1397
+
trips {
1398
+
mapss0_alert0: trip-point0 {
1399
+
temperature = <90000>;
1400
+
hysteresis = <2000>;
1401
+
type = "passive";
1402
+
};
1403
+
1404
+
mapss0_alert1: trip-point1 {
1405
+
temperature = <95000>;
1406
+
hysteresis = <2000>;
1407
+
type = "passive";
1408
+
};
1409
+
1410
+
mapss0_crit: mapss-crit {
1411
+
temperature = <110000>;
1412
+
hysteresis = <1000>;
1413
+
type = "critical";
1414
+
};
1415
+
};
1416
+
};
1417
+
1418
+
cpu0-thermal {
1419
+
polling-delay-passive = <0>;
1420
+
polling-delay = <0>;
1421
+
1422
+
thermal-sensors = <&tsens0 1>;
1423
+
1424
+
trips {
1425
+
cpu0_alert0: trip-point0 {
1426
+
temperature = <90000>;
1427
+
hysteresis = <2000>;
1428
+
type = "passive";
1429
+
};
1430
+
1431
+
cpu0_alert1: trip-point1 {
1432
+
temperature = <95000>;
1433
+
hysteresis = <2000>;
1434
+
type = "passive";
1435
+
};
1436
+
1437
+
cpu0_crit: cpu-crit {
1438
+
temperature = <110000>;
1439
+
hysteresis = <1000>;
1440
+
type = "critical";
1441
+
};
1442
+
};
1443
+
};
1444
+
1445
+
cpu1-thermal {
1446
+
polling-delay-passive = <0>;
1447
+
polling-delay = <0>;
1448
+
1449
+
thermal-sensors = <&tsens0 2>;
1450
+
1451
+
trips {
1452
+
cpu1_alert0: trip-point0 {
1453
+
temperature = <90000>;
1454
+
hysteresis = <2000>;
1455
+
type = "passive";
1456
+
};
1457
+
1458
+
cpu1_alert1: trip-point1 {
1459
+
temperature = <95000>;
1460
+
hysteresis = <2000>;
1461
+
type = "passive";
1462
+
};
1463
+
1464
+
cpu1_crit: cpu-crit {
1465
+
temperature = <110000>;
1466
+
hysteresis = <1000>;
1467
+
type = "critical";
1468
+
};
1469
+
};
1470
+
};
1471
+
1472
+
cpu2-thermal {
1473
+
polling-delay-passive = <0>;
1474
+
polling-delay = <0>;
1475
+
1476
+
thermal-sensors = <&tsens0 3>;
1477
+
1478
+
trips {
1479
+
cpu2_alert0: trip-point0 {
1480
+
temperature = <90000>;
1481
+
hysteresis = <2000>;
1482
+
type = "passive";
1483
+
};
1484
+
1485
+
cpu2_alert1: trip-point1 {
1486
+
temperature = <95000>;
1487
+
hysteresis = <2000>;
1488
+
type = "passive";
1489
+
};
1490
+
1491
+
cpu2_crit: cpu-crit {
1492
+
temperature = <110000>;
1493
+
hysteresis = <1000>;
1494
+
type = "critical";
1495
+
};
1496
+
};
1497
+
};
1498
+
1499
+
cpu3-thermal {
1500
+
polling-delay-passive = <0>;
1501
+
polling-delay = <0>;
1502
+
1503
+
thermal-sensors = <&tsens0 4>;
1504
+
1505
+
trips {
1506
+
cpu3_alert0: trip-point0 {
1507
+
temperature = <90000>;
1508
+
hysteresis = <2000>;
1509
+
type = "passive";
1510
+
};
1511
+
1512
+
cpu3_alert1: trip-point1 {
1513
+
temperature = <95000>;
1514
+
hysteresis = <2000>;
1515
+
type = "passive";
1516
+
};
1517
+
1518
+
cpu3_crit: cpu-crit {
1519
+
temperature = <110000>;
1520
+
hysteresis = <1000>;
1521
+
type = "critical";
1522
+
};
1523
+
};
1524
+
};
1525
+
1526
+
cpu4-thermal {
1527
+
polling-delay-passive = <0>;
1528
+
polling-delay = <0>;
1529
+
1530
+
thermal-sensors = <&tsens0 5>;
1531
+
1532
+
trips {
1533
+
cpu4_alert0: trip-point0 {
1534
+
temperature = <90000>;
1535
+
hysteresis = <2000>;
1536
+
type = "passive";
1537
+
};
1538
+
1539
+
cpu4_alert1: trip-point1 {
1540
+
temperature = <95000>;
1541
+
hysteresis = <2000>;
1542
+
type = "passive";
1543
+
};
1544
+
1545
+
cpu4_crit: cpu-crit {
1546
+
temperature = <110000>;
1547
+
hysteresis = <1000>;
1548
+
type = "critical";
1549
+
};
1550
+
};
1551
+
};
1552
+
1553
+
cpu5-thermal {
1554
+
polling-delay-passive = <0>;
1555
+
polling-delay = <0>;
1556
+
1557
+
thermal-sensors = <&tsens0 6>;
1558
+
1559
+
trips {
1560
+
cpu5_alert0: trip-point0 {
1561
+
temperature = <90000>;
1562
+
hysteresis = <2000>;
1563
+
type = "passive";
1564
+
};
1565
+
1566
+
cpu5_alert1: trip-point1 {
1567
+
temperature = <95000>;
1568
+
hysteresis = <2000>;
1569
+
type = "passive";
1570
+
};
1571
+
1572
+
cpu5_crit: cpu-crit {
1573
+
temperature = <110000>;
1574
+
hysteresis = <1000>;
1575
+
type = "critical";
1576
+
};
1577
+
};
1578
+
};
1579
+
1580
+
cluster0-thermal {
1581
+
polling-delay-passive = <0>;
1582
+
polling-delay = <0>;
1583
+
1584
+
thermal-sensors = <&tsens0 7>;
1585
+
1586
+
trips {
1587
+
cluster0_alert0: trip-point0 {
1588
+
temperature = <90000>;
1589
+
hysteresis = <2000>;
1590
+
type = "passive";
1591
+
};
1592
+
1593
+
cluster0_alert1: trip-point1 {
1594
+
temperature = <95000>;
1595
+
hysteresis = <2000>;
1596
+
type = "passive";
1597
+
};
1598
+
1599
+
cluster0_crit: cpu-crit {
1600
+
temperature = <110000>;
1601
+
hysteresis = <1000>;
1602
+
type = "critical";
1603
+
};
1604
+
};
1605
+
};
1606
+
1607
+
cluster1-thermal {
1608
+
polling-delay-passive = <0>;
1609
+
polling-delay = <0>;
1610
+
1611
+
thermal-sensors = <&tsens0 8>;
1612
+
1613
+
trips {
1614
+
cluster1_alert0: trip-point0 {
1615
+
temperature = <90000>;
1616
+
hysteresis = <2000>;
1617
+
type = "passive";
1618
+
};
1619
+
1620
+
cluster1_alert1: trip-point1 {
1621
+
temperature = <95000>;
1622
+
hysteresis = <2000>;
1623
+
type = "passive";
1624
+
};
1625
+
1626
+
cluster1_crit: cpu-crit {
1627
+
temperature = <110000>;
1628
+
hysteresis = <1000>;
1629
+
type = "critical";
1630
+
};
1631
+
};
1632
+
};
1633
+
1634
+
cpu6-thermal {
1635
+
polling-delay-passive = <0>;
1636
+
polling-delay = <0>;
1637
+
1638
+
thermal-sensors = <&tsens0 9>;
1639
+
1640
+
trips {
1641
+
cpu6_alert0: trip-point0 {
1642
+
temperature = <90000>;
1643
+
hysteresis = <2000>;
1644
+
type = "passive";
1645
+
};
1646
+
1647
+
cpu6_alert1: trip-point1 {
1648
+
temperature = <95000>;
1649
+
hysteresis = <2000>;
1650
+
type = "passive";
1651
+
};
1652
+
1653
+
cpu6_crit: cpu-crit {
1654
+
temperature = <110000>;
1655
+
hysteresis = <1000>;
1656
+
type = "critical";
1657
+
};
1658
+
};
1659
+
};
1660
+
1661
+
cpu7-thermal {
1662
+
polling-delay-passive = <0>;
1663
+
polling-delay = <0>;
1664
+
1665
+
thermal-sensors = <&tsens0 10>;
1666
+
1667
+
trips {
1668
+
cpu7_alert0: trip-point0 {
1669
+
temperature = <90000>;
1670
+
hysteresis = <2000>;
1671
+
type = "passive";
1672
+
};
1673
+
1674
+
cpu7_alert1: trip-point1 {
1675
+
temperature = <95000>;
1676
+
hysteresis = <2000>;
1677
+
type = "passive";
1678
+
};
1679
+
1680
+
cpu7_crit: cpu-crit {
1681
+
temperature = <110000>;
1682
+
hysteresis = <1000>;
1683
+
type = "critical";
1684
+
};
1685
+
};
1686
+
};
1687
+
1688
+
cpu-unk0-thermal {
1689
+
polling-delay-passive = <0>;
1690
+
polling-delay = <0>;
1691
+
1692
+
thermal-sensors = <&tsens0 11>;
1693
+
1694
+
trips {
1695
+
cpu_unk0_alert0: trip-point0 {
1696
+
temperature = <90000>;
1697
+
hysteresis = <2000>;
1698
+
type = "passive";
1699
+
};
1700
+
1701
+
cpu_unk0_alert1: trip-point1 {
1702
+
temperature = <95000>;
1703
+
hysteresis = <2000>;
1704
+
type = "passive";
1705
+
};
1706
+
1707
+
cpu_unk0_crit: cpu-crit {
1708
+
temperature = <110000>;
1709
+
hysteresis = <1000>;
1710
+
type = "critical";
1711
+
};
1712
+
};
1713
+
};
1714
+
1715
+
cpu-unk1-thermal {
1716
+
polling-delay-passive = <0>;
1717
+
polling-delay = <0>;
1718
+
1719
+
thermal-sensors = <&tsens0 12>;
1720
+
1721
+
trips {
1722
+
cpu_unk1_alert0: trip-point0 {
1723
+
temperature = <90000>;
1724
+
hysteresis = <2000>;
1725
+
type = "passive";
1726
+
};
1727
+
1728
+
cpu_unk1_alert1: trip-point1 {
1729
+
temperature = <95000>;
1730
+
hysteresis = <2000>;
1731
+
type = "passive";
1732
+
};
1733
+
1734
+
cpu_unk1_crit: cpu-crit {
1735
+
temperature = <110000>;
1736
+
hysteresis = <1000>;
1737
+
type = "critical";
1738
+
};
1739
+
};
1740
+
};
1741
+
1742
+
gpuss0-thermal {
1743
+
polling-delay-passive = <0>;
1744
+
polling-delay = <0>;
1745
+
1746
+
thermal-sensors = <&tsens0 13>;
1747
+
1748
+
trips {
1749
+
gpuss0_alert0: trip-point0 {
1750
+
temperature = <90000>;
1751
+
hysteresis = <2000>;
1752
+
type = "passive";
1753
+
};
1754
+
1755
+
gpuss0_alert1: trip-point1 {
1756
+
temperature = <95000>;
1757
+
hysteresis = <2000>;
1758
+
type = "passive";
1759
+
};
1760
+
1761
+
gpuss0_crit: gpu-crit {
1762
+
temperature = <110000>;
1763
+
hysteresis = <1000>;
1764
+
type = "critical";
1765
+
};
1766
+
};
1767
+
};
1768
+
1769
+
gpuss1-thermal {
1770
+
polling-delay-passive = <0>;
1771
+
polling-delay = <0>;
1772
+
1773
+
thermal-sensors = <&tsens0 14>;
1774
+
1775
+
trips {
1776
+
gpuss1_alert0: trip-point0 {
1777
+
temperature = <90000>;
1778
+
hysteresis = <2000>;
1779
+
type = "passive";
1780
+
};
1781
+
1782
+
gpuss1_alert1: trip-point1 {
1783
+
temperature = <95000>;
1784
+
hysteresis = <2000>;
1785
+
type = "passive";
1786
+
};
1787
+
1788
+
gpuss1_crit: gpu-crit {
1789
+
temperature = <110000>;
1790
+
hysteresis = <1000>;
1791
+
type = "critical";
1792
+
};
1793
+
};
1794
+
};
1795
+
1796
+
mapss1-thermal {
1797
+
polling-delay-passive = <0>;
1798
+
polling-delay = <0>;
1799
+
1800
+
thermal-sensors = <&tsens1 0>;
1801
+
1802
+
trips {
1803
+
mapss1_alert0: trip-point0 {
1804
+
temperature = <90000>;
1805
+
hysteresis = <2000>;
1806
+
type = "passive";
1807
+
};
1808
+
1809
+
mapss1_alert1: trip-point1 {
1810
+
temperature = <95000>;
1811
+
hysteresis = <2000>;
1812
+
type = "passive";
1813
+
};
1814
+
1815
+
mapss1_crit: mapss-crit {
1816
+
temperature = <110000>;
1817
+
hysteresis = <1000>;
1818
+
type = "critical";
1819
+
};
1820
+
};
1821
+
};
1822
+
1823
+
cwlan-thermal {
1824
+
polling-delay-passive = <0>;
1825
+
polling-delay = <0>;
1826
+
1827
+
thermal-sensors = <&tsens1 1>;
1828
+
1829
+
trips {
1830
+
cwlan_alert0: trip-point0 {
1831
+
temperature = <90000>;
1832
+
hysteresis = <2000>;
1833
+
type = "passive";
1834
+
};
1835
+
1836
+
cwlan_alert1: trip-point1 {
1837
+
temperature = <95000>;
1838
+
hysteresis = <2000>;
1839
+
type = "passive";
1840
+
};
1841
+
1842
+
cwlan_crit: cwlan-crit {
1843
+
temperature = <110000>;
1844
+
hysteresis = <1000>;
1845
+
type = "critical";
1846
+
};
1847
+
};
1848
+
};
1849
+
1850
+
audio-thermal {
1851
+
polling-delay-passive = <0>;
1852
+
polling-delay = <0>;
1853
+
1854
+
thermal-sensors = <&tsens1 2>;
1855
+
1856
+
trips {
1857
+
audio_alert0: trip-point0 {
1858
+
temperature = <90000>;
1859
+
hysteresis = <2000>;
1860
+
type = "passive";
1861
+
};
1862
+
1863
+
audio_alert1: trip-point1 {
1864
+
temperature = <95000>;
1865
+
hysteresis = <2000>;
1866
+
type = "passive";
1867
+
};
1868
+
1869
+
audio_crit: audio-crit {
1870
+
temperature = <110000>;
1871
+
hysteresis = <1000>;
1872
+
type = "critical";
1873
+
};
1874
+
};
1875
+
};
1876
+
1877
+
ddr-thermal {
1878
+
polling-delay-passive = <0>;
1879
+
polling-delay = <0>;
1880
+
1881
+
thermal-sensors = <&tsens1 3>;
1882
+
1883
+
trips {
1884
+
ddr_alert0: trip-point0 {
1885
+
temperature = <90000>;
1886
+
hysteresis = <2000>;
1887
+
type = "passive";
1888
+
};
1889
+
1890
+
ddr_alert1: trip-point1 {
1891
+
temperature = <95000>;
1892
+
hysteresis = <2000>;
1893
+
type = "passive";
1894
+
};
1895
+
1896
+
ddr_crit: ddr-crit {
1897
+
temperature = <110000>;
1898
+
hysteresis = <1000>;
1899
+
type = "critical";
1900
+
};
1901
+
};
1902
+
};
1903
+
1904
+
q6hvx-thermal {
1905
+
polling-delay-passive = <0>;
1906
+
polling-delay = <0>;
1907
+
1908
+
thermal-sensors = <&tsens1 4>;
1909
+
1910
+
trips {
1911
+
q6hvx_alert0: trip-point0 {
1912
+
temperature = <90000>;
1913
+
hysteresis = <2000>;
1914
+
type = "passive";
1915
+
};
1916
+
1917
+
q6hvx_alert1: trip-point1 {
1918
+
temperature = <95000>;
1919
+
hysteresis = <2000>;
1920
+
type = "passive";
1921
+
};
1922
+
1923
+
q6hvx_crit: q6hvx-crit {
1924
+
temperature = <110000>;
1925
+
hysteresis = <1000>;
1926
+
type = "critical";
1927
+
};
1928
+
};
1929
+
};
1930
+
1931
+
camera-thermal {
1932
+
polling-delay-passive = <0>;
1933
+
polling-delay = <0>;
1934
+
1935
+
thermal-sensors = <&tsens1 5>;
1936
+
1937
+
trips {
1938
+
camera_alert0: trip-point0 {
1939
+
temperature = <90000>;
1940
+
hysteresis = <2000>;
1941
+
type = "passive";
1942
+
};
1943
+
1944
+
camera_alert1: trip-point1 {
1945
+
temperature = <95000>;
1946
+
hysteresis = <2000>;
1947
+
type = "passive";
1948
+
};
1949
+
1950
+
camera_crit: camera-crit {
1951
+
temperature = <110000>;
1952
+
hysteresis = <1000>;
1953
+
type = "critical";
1954
+
};
1955
+
};
1956
+
};
1957
+
1958
+
mdm-core0-thermal {
1959
+
polling-delay-passive = <0>;
1960
+
polling-delay = <0>;
1961
+
1962
+
thermal-sensors = <&tsens1 6>;
1963
+
1964
+
trips {
1965
+
mdm_core0_alert0: trip-point0 {
1966
+
temperature = <90000>;
1967
+
hysteresis = <2000>;
1968
+
type = "passive";
1969
+
};
1970
+
1971
+
mdm_core0_alert1: trip-point1 {
1972
+
temperature = <95000>;
1973
+
hysteresis = <2000>;
1974
+
type = "passive";
1975
+
};
1976
+
1977
+
mdm_core0_crit: mdm-core0-crit {
1978
+
temperature = <110000>;
1979
+
hysteresis = <1000>;
1980
+
type = "critical";
1981
+
};
1982
+
};
1983
+
};
1984
+
1985
+
mdm-core1-thermal {
1986
+
polling-delay-passive = <0>;
1987
+
polling-delay = <0>;
1988
+
1989
+
thermal-sensors = <&tsens1 7>;
1990
+
1991
+
trips {
1992
+
mdm_core1_alert0: trip-point0 {
1993
+
temperature = <90000>;
1994
+
hysteresis = <2000>;
1995
+
type = "passive";
1996
+
};
1997
+
1998
+
mdm_core1_alert1: trip-point1 {
1999
+
temperature = <95000>;
2000
+
hysteresis = <2000>;
2001
+
type = "passive";
2002
+
};
2003
+
2004
+
mdm_core1_crit: mdm-core1-crit {
2005
+
temperature = <110000>;
2006
+
hysteresis = <1000>;
2007
+
type = "critical";
2008
+
};
2009
+
};
2010
+
};
2011
+
2012
+
mdm-vec-thermal {
2013
+
polling-delay-passive = <0>;
2014
+
polling-delay = <0>;
2015
+
2016
+
thermal-sensors = <&tsens1 8>;
2017
+
2018
+
trips {
2019
+
mdm_vec_alert0: trip-point0 {
2020
+
temperature = <90000>;
2021
+
hysteresis = <2000>;
2022
+
type = "passive";
2023
+
};
2024
+
2025
+
mdm_vec_alert1: trip-point1 {
2026
+
temperature = <95000>;
2027
+
hysteresis = <2000>;
2028
+
type = "passive";
2029
+
};
2030
+
2031
+
mdm_vec_crit: mdm-vec-crit {
2032
+
temperature = <110000>;
2033
+
hysteresis = <1000>;
2034
+
type = "critical";
2035
+
};
2036
+
};
2037
+
};
2038
+
2039
+
msm-scl-thermal {
2040
+
polling-delay-passive = <0>;
2041
+
polling-delay = <0>;
2042
+
2043
+
thermal-sensors = <&tsens1 9>;
2044
+
2045
+
trips {
2046
+
msm_scl_alert0: trip-point0 {
2047
+
temperature = <90000>;
2048
+
hysteresis = <2000>;
2049
+
type = "passive";
2050
+
};
2051
+
2052
+
msm_scl_alert1: trip-point1 {
2053
+
temperature = <95000>;
2054
+
hysteresis = <2000>;
2055
+
type = "passive";
2056
+
};
2057
+
2058
+
msm_scl_crit: msm-scl-crit {
2059
+
temperature = <110000>;
2060
+
hysteresis = <1000>;
2061
+
type = "critical";
2062
+
};
2063
+
};
2064
+
};
2065
+
2066
+
video-thermal {
2067
+
polling-delay-passive = <0>;
2068
+
polling-delay = <0>;
2069
+
2070
+
thermal-sensors = <&tsens1 10>;
2071
+
2072
+
trips {
2073
+
video_alert0: trip-point0 {
2074
+
temperature = <90000>;
2075
+
hysteresis = <2000>;
2076
+
type = "passive";
2077
+
};
2078
+
2079
+
video_alert1: trip-point1 {
2080
+
temperature = <95000>;
2081
+
hysteresis = <2000>;
2082
+
type = "passive";
2083
+
};
2084
+
2085
+
video_crit: video-crit {
2086
+
temperature = <110000>;
2087
+
hysteresis = <1000>;
2088
+
type = "critical";
2089
+
};
2090
+
};
1576
2091
};
1577
2092
};
1578
2093
+3
-3
arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi
+3
-3
arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi
···
59
59
gpios = <&pm8150b_gpios 2 GPIO_ACTIVE_LOW>;
60
60
debounce-interval = <15>;
61
61
linux,can-disable;
62
-
gpio-key,wakeup;
62
+
wakeup-source;
63
63
};
64
64
65
65
key-camera-snapshot {
···
68
68
gpios = <&pm8150b_gpios 1 GPIO_ACTIVE_LOW>;
69
69
debounce-interval = <15>;
70
70
linux,can-disable;
71
-
gpio-key,wakeup;
71
+
wakeup-source;
72
72
};
73
73
74
74
key-vol-down {
···
77
77
gpios = <&pm8150_gpios 1 GPIO_ACTIVE_LOW>;
78
78
debounce-interval = <15>;
79
79
linux,can-disable;
80
-
gpio-key,wakeup;
80
+
wakeup-source;
81
81
};
82
82
};
83
83
+43
-13
arch/arm64/boot/dts/qcom/sm8150.dtsi
+43
-13
arch/arm64/boot/dts/qcom/sm8150.dtsi
···
48
48
device_type = "cpu";
49
49
compatible = "qcom,kryo485";
50
50
reg = <0x0 0x0>;
51
+
clocks = <&cpufreq_hw 0>;
51
52
enable-method = "psci";
52
53
capacity-dmips-mhz = <488>;
53
54
dynamic-power-coefficient = <232>;
···
75
74
device_type = "cpu";
76
75
compatible = "qcom,kryo485";
77
76
reg = <0x0 0x100>;
77
+
clocks = <&cpufreq_hw 0>;
78
78
enable-method = "psci";
79
79
capacity-dmips-mhz = <488>;
80
80
dynamic-power-coefficient = <232>;
···
92
90
cache-level = <2>;
93
91
next-level-cache = <&L3_0>;
94
92
};
95
-
96
93
};
97
94
98
95
CPU2: cpu@200 {
99
96
device_type = "cpu";
100
97
compatible = "qcom,kryo485";
101
98
reg = <0x0 0x200>;
99
+
clocks = <&cpufreq_hw 0>;
102
100
enable-method = "psci";
103
101
capacity-dmips-mhz = <488>;
104
102
dynamic-power-coefficient = <232>;
···
121
119
device_type = "cpu";
122
120
compatible = "qcom,kryo485";
123
121
reg = <0x0 0x300>;
122
+
clocks = <&cpufreq_hw 0>;
124
123
enable-method = "psci";
125
124
capacity-dmips-mhz = <488>;
126
125
dynamic-power-coefficient = <232>;
···
144
141
device_type = "cpu";
145
142
compatible = "qcom,kryo485";
146
143
reg = <0x0 0x400>;
144
+
clocks = <&cpufreq_hw 1>;
147
145
enable-method = "psci";
148
146
capacity-dmips-mhz = <1024>;
149
147
dynamic-power-coefficient = <369>;
···
167
163
device_type = "cpu";
168
164
compatible = "qcom,kryo485";
169
165
reg = <0x0 0x500>;
166
+
clocks = <&cpufreq_hw 1>;
170
167
enable-method = "psci";
171
168
capacity-dmips-mhz = <1024>;
172
169
dynamic-power-coefficient = <369>;
···
190
185
device_type = "cpu";
191
186
compatible = "qcom,kryo485";
192
187
reg = <0x0 0x600>;
188
+
clocks = <&cpufreq_hw 1>;
193
189
enable-method = "psci";
194
190
capacity-dmips-mhz = <1024>;
195
191
dynamic-power-coefficient = <369>;
···
213
207
device_type = "cpu";
214
208
compatible = "qcom,kryo485";
215
209
reg = <0x0 0x700>;
210
+
clocks = <&cpufreq_hw 2>;
216
211
enable-method = "psci";
217
212
capacity-dmips-mhz = <1024>;
218
213
dynamic-power-coefficient = <421>;
···
295
288
domain-idle-states {
296
289
CLUSTER_SLEEP_0: cluster-sleep-0 {
297
290
compatible = "domain-idle-state";
298
-
idle-state-name = "cluster-power-collapse";
299
291
arm,psci-suspend-param = <0x4100c244>;
300
292
entry-latency-us = <3263>;
301
293
exit-latency-us = <6562>;
302
294
min-residency-us = <9987>;
303
-
local-timer-stop;
304
295
};
305
296
};
306
297
};
···
1339
1334
status = "disabled";
1340
1335
};
1341
1336
1337
+
uart9: serial@a84000 {
1338
+
compatible = "qcom,geni-uart";
1339
+
reg = <0x0 0x00a84000 0x0 0x4000>;
1340
+
reg-names = "se";
1341
+
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1342
+
clock-names = "se";
1343
+
pinctrl-0 = <&qup_uart9_default>;
1344
+
pinctrl-names = "default";
1345
+
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1346
+
#address-cells = <1>;
1347
+
#size-cells = <0>;
1348
+
status = "disabled";
1349
+
};
1350
+
1342
1351
i2c10: i2c@a88000 {
1343
1352
compatible = "qcom,geni-i2c";
1344
1353
reg = <0 0x00a88000 0 0x4000>;
···
1791
1772
1792
1773
system-cache-controller@9200000 {
1793
1774
compatible = "qcom,sm8150-llcc";
1794
-
reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
1795
-
reg-names = "llcc_base", "llcc_broadcast_base";
1775
+
reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
1776
+
<0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
1777
+
<0 0x09600000 0 0x50000>;
1778
+
reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
1779
+
"llcc3_base", "llcc_broadcast_base";
1796
1780
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1797
1781
};
1798
1782
···
1821
1799
#address-cells = <3>;
1822
1800
#size-cells = <2>;
1823
1801
1824
-
ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1825
-
<0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
1802
+
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1803
+
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1826
1804
1827
1805
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1828
1806
interrupt-names = "msi";
···
1848
1826
"slave_q2a",
1849
1827
"tbu";
1850
1828
1851
-
iommus = <&apps_smmu 0x1d80 0x7f>;
1829
+
iommus = <&apps_smmu 0x1d80 0x3f>;
1852
1830
iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1853
1831
<0x100 &apps_smmu 0x1d81 0x1>;
1854
1832
···
1917
1895
#address-cells = <3>;
1918
1896
#size-cells = <2>;
1919
1897
1920
-
ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
1898
+
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1921
1899
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1922
1900
1923
1901
interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
···
1947
1925
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1948
1926
assigned-clock-rates = <19200000>;
1949
1927
1950
-
iommus = <&apps_smmu 0x1e00 0x7f>;
1928
+
iommus = <&apps_smmu 0x1e00 0x3f>;
1951
1929
iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1952
1930
<0x100 &apps_smmu 0x1e01 0x1>;
1953
1931
···
2271
2249
};
2272
2250
2273
2251
adreno_smmu: iommu@2ca0000 {
2274
-
compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
2252
+
compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu",
2253
+
"qcom,smmu-500", "arm,mmu-500";
2275
2254
reg = <0 0x02ca0000 0 0x10000>;
2276
2255
#iommu-cells = <2>;
2277
2256
#global-interrupts = <1>;
···
2445
2422
pins = "gpio39", "gpio40", "gpio41", "gpio42";
2446
2423
function = "qup9";
2447
2424
drive-strength = <6>;
2425
+
bias-disable;
2426
+
};
2427
+
2428
+
qup_uart9_default: qup-uart9-default-state {
2429
+
pins = "gpio41", "gpio42";
2430
+
function = "qup9";
2431
+
drive-strength = <2>;
2448
2432
bias-disable;
2449
2433
};
2450
2434
···
3965
3935
#size-cells = <0>;
3966
3936
interrupt-controller;
3967
3937
#interrupt-cells = <4>;
3968
-
cell-index = <0>;
3969
3938
};
3970
3939
3971
3940
apps_smmu: iommu@15000000 {
···
4292
4263
};
4293
4264
4294
4265
cpufreq_hw: cpufreq@18323000 {
4295
-
compatible = "qcom,cpufreq-hw";
4266
+
compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw";
4296
4267
reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
4297
4268
<0 0x18327800 0 0x1400>;
4298
4269
reg-names = "freq-domain0", "freq-domain1",
···
4302
4273
clock-names = "xo", "alternate";
4303
4274
4304
4275
#freq-domain-cells = <1>;
4276
+
#clock-cells = <1>;
4305
4277
};
4306
4278
4307
4279
lmh_cluster1: lmh@18350800 {
+2
-2
arch/arm64/boot/dts/qcom/sm8250-mtp.dts
+2
-2
arch/arm64/boot/dts/qcom/sm8250-mtp.dts
···
764
764
left_spkr: speaker@0,3 {
765
765
compatible = "sdw10217211000";
766
766
reg = <0 3>;
767
-
powerdown-gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
767
+
powerdown-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
768
768
#thermal-sensor-cells = <0>;
769
769
sound-name-prefix = "SpkrLeft";
770
770
#sound-dai-cells = <0>;
···
773
773
right_spkr: speaker@0,4 {
774
774
compatible = "sdw10217211000";
775
775
reg = <0 4>;
776
-
powerdown-gpios = <&tlmm 127 GPIO_ACTIVE_HIGH>;
776
+
powerdown-gpios = <&tlmm 127 GPIO_ACTIVE_LOW>;
777
777
#thermal-sensor-cells = <0>;
778
778
sound-name-prefix = "SpkrRight";
779
779
#sound-dai-cells = <0>;
+1
-1
arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts
+1
-1
arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts
+1
-1
arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi
+1
-1
arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi
+3
-3
arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts
+3
-3
arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts
···
95
95
linux,code = <KEY_VOLUMEUP>;
96
96
debounce-interval = <15>;
97
97
linux,can-disable;
98
-
gpio-key,wakeup;
98
+
wakeup-source;
99
99
};
100
100
};
101
101
···
595
595
596
596
&usb_1_dwc3 {
597
597
dr_mode = "peripheral";
598
-
maximum-spped = "high-speed";
598
+
maximum-speed = "high-speed";
599
599
/* Remove USB3 phy */
600
600
phys = <&usb_1_hsphy>;
601
601
phy-names = "usb2-phy";
···
625
625
};
626
626
627
627
&venus {
628
-
firmware-name = "qcom/sm8250/elish/venus.mbn";
628
+
firmware-name = "qcom/sm8250/xiaomi/elish/venus.mbn";
629
629
status = "okay";
630
630
};
+194
-28
arch/arm64/boot/dts/qcom/sm8250.dtsi
+194
-28
arch/arm64/boot/dts/qcom/sm8250.dtsi
···
97
97
device_type = "cpu";
98
98
compatible = "qcom,kryo485";
99
99
reg = <0x0 0x0>;
100
+
clocks = <&cpufreq_hw 0>;
100
101
enable-method = "psci";
101
102
capacity-dmips-mhz = <448>;
102
103
dynamic-power-coefficient = <205>;
···
128
127
device_type = "cpu";
129
128
compatible = "qcom,kryo485";
130
129
reg = <0x0 0x100>;
130
+
clocks = <&cpufreq_hw 0>;
131
131
enable-method = "psci";
132
132
capacity-dmips-mhz = <448>;
133
133
dynamic-power-coefficient = <205>;
···
153
151
device_type = "cpu";
154
152
compatible = "qcom,kryo485";
155
153
reg = <0x0 0x200>;
154
+
clocks = <&cpufreq_hw 0>;
156
155
enable-method = "psci";
157
156
capacity-dmips-mhz = <448>;
158
157
dynamic-power-coefficient = <205>;
···
178
175
device_type = "cpu";
179
176
compatible = "qcom,kryo485";
180
177
reg = <0x0 0x300>;
178
+
clocks = <&cpufreq_hw 0>;
181
179
enable-method = "psci";
182
180
capacity-dmips-mhz = <448>;
183
181
dynamic-power-coefficient = <205>;
···
203
199
device_type = "cpu";
204
200
compatible = "qcom,kryo485";
205
201
reg = <0x0 0x400>;
202
+
clocks = <&cpufreq_hw 1>;
206
203
enable-method = "psci";
207
204
capacity-dmips-mhz = <1024>;
208
205
dynamic-power-coefficient = <379>;
···
228
223
device_type = "cpu";
229
224
compatible = "qcom,kryo485";
230
225
reg = <0x0 0x500>;
226
+
clocks = <&cpufreq_hw 1>;
231
227
enable-method = "psci";
232
228
capacity-dmips-mhz = <1024>;
233
229
dynamic-power-coefficient = <379>;
···
247
241
cache-unified;
248
242
next-level-cache = <&L3_0>;
249
243
};
250
-
251
244
};
252
245
253
246
CPU6: cpu@600 {
254
247
device_type = "cpu";
255
248
compatible = "qcom,kryo485";
256
249
reg = <0x0 0x600>;
250
+
clocks = <&cpufreq_hw 1>;
257
251
enable-method = "psci";
258
252
capacity-dmips-mhz = <1024>;
259
253
dynamic-power-coefficient = <379>;
···
278
272
device_type = "cpu";
279
273
compatible = "qcom,kryo485";
280
274
reg = <0x0 0x700>;
275
+
clocks = <&cpufreq_hw 2>;
281
276
enable-method = "psci";
282
277
capacity-dmips-mhz = <1024>;
283
278
dynamic-power-coefficient = <444>;
···
362
355
domain-idle-states {
363
356
CLUSTER_SLEEP_0: cluster-sleep-0 {
364
357
compatible = "domain-idle-state";
365
-
idle-state-name = "cluster-llcc-off";
366
358
arm,psci-suspend-param = <0x4100c244>;
367
359
entry-latency-us = <3264>;
368
360
exit-latency-us = <6562>;
369
361
min-residency-us = <9987>;
370
-
local-timer-stop;
371
362
};
372
363
};
373
364
};
···
1829
1824
<0 0x60000000 0 0xf1d>,
1830
1825
<0 0x60000f20 0 0xa8>,
1831
1826
<0 0x60001000 0 0x1000>,
1832
-
<0 0x60100000 0 0x100000>;
1833
-
reg-names = "parf", "dbi", "elbi", "atu", "config";
1827
+
<0 0x60100000 0 0x100000>,
1828
+
<0 0x01c03000 0 0x1000>;
1829
+
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1834
1830
device_type = "pci";
1835
1831
linux,pci-domain = <0>;
1836
1832
bus-range = <0x00 0xff>;
···
1840
1834
#address-cells = <3>;
1841
1835
#size-cells = <2>;
1842
1836
1843
-
ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1844
-
<0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
1837
+
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1838
+
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1845
1839
1846
1840
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1847
1841
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
···
1939
1933
<0 0x40000000 0 0xf1d>,
1940
1934
<0 0x40000f20 0 0xa8>,
1941
1935
<0 0x40001000 0 0x1000>,
1942
-
<0 0x40100000 0 0x100000>;
1943
-
reg-names = "parf", "dbi", "elbi", "atu", "config";
1936
+
<0 0x40100000 0 0x100000>,
1937
+
<0 0x01c0b000 0 0x1000>;
1938
+
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1944
1939
device_type = "pci";
1945
1940
linux,pci-domain = <1>;
1946
1941
bus-range = <0x00 0xff>;
···
1950
1943
#address-cells = <3>;
1951
1944
#size-cells = <2>;
1952
1945
1953
-
ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
1946
+
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1954
1947
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1955
1948
1956
1949
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
···
2048
2041
<0 0x64000000 0 0xf1d>,
2049
2042
<0 0x64000f20 0 0xa8>,
2050
2043
<0 0x64001000 0 0x1000>,
2051
-
<0 0x64100000 0 0x100000>;
2052
-
reg-names = "parf", "dbi", "elbi", "atu", "config";
2044
+
<0 0x64100000 0 0x100000>,
2045
+
<0 0x01c13000 0 0x1000>;
2046
+
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2053
2047
device_type = "pci";
2054
2048
linux,pci-domain = <2>;
2055
2049
bus-range = <0x00 0xff>;
···
2059
2051
#address-cells = <3>;
2060
2052
#size-cells = <2>;
2061
2053
2062
-
ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>,
2054
+
ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>,
2063
2055
<0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2064
2056
2065
2057
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
···
2428
2420
drive-strength = <2>;
2429
2421
slew-rate = <1>;
2430
2422
bias-bus-hold;
2431
-
2432
2423
};
2433
2424
};
2434
2425
···
2446
2439
drive-strength = <2>;
2447
2440
input-enable;
2448
2441
bias-pull-down;
2449
-
2450
2442
};
2451
2443
};
2452
2444
···
2662
2656
};
2663
2657
2664
2658
adreno_smmu: iommu@3da0000 {
2665
-
compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
2659
+
compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu",
2660
+
"qcom,smmu-500", "arm,mmu-500";
2666
2661
reg = <0 0x03da0000 0 0x10000>;
2667
2662
#iommu-cells = <2>;
2668
2663
#global-interrupts = <2>;
···
2770
2763
};
2771
2764
};
2772
2765
2766
+
tpda@6004000 {
2767
+
compatible = "qcom,coresight-tpda", "arm,primecell";
2768
+
reg = <0 0x06004000 0 0x1000>;
2769
+
2770
+
clocks = <&aoss_qmp>;
2771
+
clock-names = "apb_pclk";
2772
+
2773
+
out-ports {
2774
+
#address-cells = <1>;
2775
+
#size-cells = <0>;
2776
+
2777
+
port@0 {
2778
+
reg = <0>;
2779
+
tpda_out_funnel_qatb: endpoint {
2780
+
remote-endpoint = <&funnel_qatb_in_tpda>;
2781
+
};
2782
+
};
2783
+
};
2784
+
2785
+
in-ports {
2786
+
#address-cells = <1>;
2787
+
#size-cells = <0>;
2788
+
2789
+
port@9 {
2790
+
reg = <9>;
2791
+
tpda_9_in_tpdm_mm: endpoint {
2792
+
remote-endpoint = <&tpdm_mm_out_tpda9>;
2793
+
};
2794
+
};
2795
+
2796
+
port@17 {
2797
+
reg = <23>;
2798
+
tpda_23_in_tpdm_prng: endpoint {
2799
+
remote-endpoint = <&tpdm_prng_out_tpda_23>;
2800
+
};
2801
+
};
2802
+
};
2803
+
};
2804
+
2805
+
funnel@6005000 {
2806
+
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2807
+
reg = <0 0x06005000 0 0x1000>;
2808
+
2809
+
clocks = <&aoss_qmp>;
2810
+
clock-names = "apb_pclk";
2811
+
2812
+
out-ports {
2813
+
port {
2814
+
funnel_qatb_out_funnel_in0: endpoint {
2815
+
remote-endpoint = <&funnel_in0_in_funnel_qatb>;
2816
+
};
2817
+
};
2818
+
};
2819
+
2820
+
in-ports {
2821
+
#address-cells = <1>;
2822
+
#size-cells = <0>;
2823
+
2824
+
port@0 {
2825
+
reg = <0>;
2826
+
funnel_qatb_in_tpda: endpoint {
2827
+
remote-endpoint = <&tpda_out_funnel_qatb>;
2828
+
};
2829
+
};
2830
+
};
2831
+
};
2832
+
2773
2833
funnel@6041000 {
2774
2834
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2775
2835
reg = <0 0x06041000 0 0x1000>;
···
2856
2782
#address-cells = <1>;
2857
2783
#size-cells = <0>;
2858
2784
2785
+
port@6 {
2786
+
reg = <6>;
2787
+
funnel_in0_in_funnel_qatb: endpoint {
2788
+
remote-endpoint = <&funnel_qatb_out_funnel_in0>;
2789
+
};
2790
+
};
2791
+
2859
2792
port@7 {
2860
2793
reg = <7>;
2861
2794
funnel0_in7: endpoint {
···
2880
2799
clock-names = "apb_pclk";
2881
2800
2882
2801
out-ports {
2883
-
#address-cells = <1>;
2884
-
#size-cells = <0>;
2885
-
2886
-
port@0 {
2887
-
reg = <0>;
2802
+
port {
2888
2803
funnel_in1_out_funnel_merg: endpoint {
2889
2804
remote-endpoint = <&funnel_merg_in_funnel_in1>;
2890
2805
};
···
2976
2899
};
2977
2900
};
2978
2901
2902
+
tpdm@684c000 {
2903
+
compatible = "qcom,coresight-tpdm", "arm,primecell";
2904
+
reg = <0 0x0684c000 0 0x1000>;
2905
+
2906
+
clocks = <&aoss_qmp>;
2907
+
clock-names = "apb_pclk";
2908
+
2909
+
out-ports {
2910
+
port {
2911
+
tpdm_prng_out_tpda_23: endpoint {
2912
+
remote-endpoint = <&tpda_23_in_tpdm_prng>;
2913
+
};
2914
+
};
2915
+
};
2916
+
};
2917
+
2979
2918
funnel@6b04000 {
2980
2919
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2981
2920
arm,primecell-periphid = <0x000bb908>;
2982
2921
2983
2922
reg = <0 0x06b04000 0 0x1000>;
2984
-
reg-names = "funnel-base";
2985
2923
2986
2924
clocks = <&aoss_qmp>;
2987
2925
clock-names = "apb_pclk";
···
3020
2928
};
3021
2929
};
3022
2930
};
3023
-
3024
2931
};
3025
2932
3026
2933
etf@6b05000 {
···
3069
2978
port {
3070
2979
replicator_in: endpoint {
3071
2980
remote-endpoint = <&etf_out>;
2981
+
};
2982
+
};
2983
+
};
2984
+
};
2985
+
2986
+
tpdm@6c08000 {
2987
+
compatible = "qcom,coresight-tpdm", "arm,primecell";
2988
+
reg = <0 0x06c08000 0 0x1000>;
2989
+
2990
+
clocks = <&aoss_qmp>;
2991
+
clock-names = "apb_pclk";
2992
+
2993
+
out-ports {
2994
+
port {
2995
+
tpdm_mm_out_funnel_dl_mm: endpoint {
2996
+
remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>;
2997
+
};
2998
+
};
2999
+
};
3000
+
};
3001
+
3002
+
funnel@6c0b000 {
3003
+
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3004
+
reg = <0 0x06c0b000 0 0x1000>;
3005
+
3006
+
clocks = <&aoss_qmp>;
3007
+
clock-names = "apb_pclk";
3008
+
3009
+
out-ports {
3010
+
port {
3011
+
funnel_dl_mm_out_funnel_dl_center: endpoint {
3012
+
remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>;
3013
+
};
3014
+
};
3015
+
};
3016
+
3017
+
in-ports {
3018
+
#address-cells = <1>;
3019
+
#size-cells = <0>;
3020
+
3021
+
port@3 {
3022
+
reg = <3>;
3023
+
funnel_dl_mm_in_tpdm_mm: endpoint {
3024
+
remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>;
3025
+
};
3026
+
};
3027
+
};
3028
+
};
3029
+
3030
+
funnel@6c2d000 {
3031
+
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3032
+
reg = <0 0x06c2d000 0 0x1000>;
3033
+
3034
+
clocks = <&aoss_qmp>;
3035
+
clock-names = "apb_pclk";
3036
+
3037
+
out-ports {
3038
+
#address-cells = <1>;
3039
+
#size-cells = <0>;
3040
+
port {
3041
+
tpdm_mm_out_tpda9: endpoint {
3042
+
remote-endpoint = <&tpda_9_in_tpdm_mm>;
3043
+
};
3044
+
};
3045
+
};
3046
+
3047
+
in-ports {
3048
+
#address-cells = <1>;
3049
+
#size-cells = <0>;
3050
+
3051
+
port@2 {
3052
+
reg = <2>;
3053
+
funnel_dl_center_in_funnel_dl_mm: endpoint {
3054
+
remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>;
3072
3055
};
3073
3056
};
3074
3057
};
···
3385
3220
clock-names = "apb_pclk";
3386
3221
3387
3222
out-ports {
3388
-
#address-cells = <1>;
3389
-
#size-cells = <0>;
3390
-
3391
3223
port {
3392
3224
funnel_apss_merg_out_funnel_in1: endpoint {
3393
3225
remote-endpoint = <&funnel_in1_in_funnel_apss_merg>;
···
3721
3559
3722
3560
system-cache-controller@9200000 {
3723
3561
compatible = "qcom,sm8250-llcc";
3724
-
reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
3725
-
reg-names = "llcc_base", "llcc_broadcast_base";
3562
+
reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
3563
+
<0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
3564
+
<0 0x09600000 0 0x50000>;
3565
+
reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
3566
+
"llcc3_base", "llcc_broadcast_base";
3726
3567
};
3727
3568
3728
3569
usb_2: usb@a8f8800 {
···
5646
5481
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
5647
5482
interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
5648
5483
#freq-domain-cells = <1>;
5484
+
#clock-cells = <1>;
5649
5485
};
5650
5486
};
5651
5487
+44
-3
arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+44
-3
arch/arm64/boot/dts/qcom/sm8350-hdk.dts
···
31
31
};
32
32
};
33
33
34
+
pmic-glink {
35
+
compatible = "qcom,sm8350-pmic-glink", "qcom,pmic-glink";
36
+
#address-cells = <1>;
37
+
#size-cells = <0>;
38
+
39
+
connector@0 {
40
+
compatible = "usb-c-connector";
41
+
reg = <0>;
42
+
power-role = "dual";
43
+
data-role = "dual";
44
+
45
+
ports {
46
+
#address-cells = <1>;
47
+
#size-cells = <0>;
48
+
49
+
port@0 {
50
+
reg = <0>;
51
+
52
+
pmic_glink_hs_in: endpoint {
53
+
remote-endpoint = <&usb_1_dwc3_hs>;
54
+
};
55
+
};
56
+
57
+
port@1 {
58
+
reg = <1>;
59
+
60
+
pmic_glink_ss_in: endpoint {
61
+
remote-endpoint = <&usb_1_dwc3_ss>;
62
+
};
63
+
};
64
+
};
65
+
};
66
+
};
67
+
34
68
vph_pwr: vph-pwr-regulator {
35
69
compatible = "regulator-fixed";
36
70
regulator-name = "vph_pwr";
···
678
644
bias-pull-up;
679
645
};
680
646
};
681
-
682
647
};
683
648
684
649
&uart2 {
···
707
674
};
708
675
709
676
&usb_1_dwc3 {
710
-
/* TODO: Define USB-C connector properly */
711
-
dr_mode = "peripheral";
677
+
dr_mode = "otg";
678
+
usb-role-switch;
679
+
};
680
+
681
+
&usb_1_dwc3_hs {
682
+
remote-endpoint = <&pmic_glink_hs_in>;
683
+
};
684
+
685
+
&usb_1_dwc3_ss {
686
+
remote-endpoint = <&pmic_glink_ss_in>;
712
687
};
713
688
714
689
&usb_1_hsphy {
+3
arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts
+3
arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts
+134
-37
arch/arm64/boot/dts/qcom/sm8350.dtsi
+134
-37
arch/arm64/boot/dts/qcom/sm8350.dtsi
···
13
13
#include <dt-bindings/gpio/gpio.h>
14
14
#include <dt-bindings/interconnect/qcom,sm8350.h>
15
15
#include <dt-bindings/mailbox/qcom-ipcc.h>
16
+
#include <dt-bindings/phy/phy-qcom-qmp.h>
16
17
#include <dt-bindings/power/qcom-rpmpd.h>
17
18
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
18
19
#include <dt-bindings/thermal/thermal.h>
···
50
49
device_type = "cpu";
51
50
compatible = "qcom,kryo685";
52
51
reg = <0x0 0x0>;
52
+
clocks = <&cpufreq_hw 0>;
53
53
enable-method = "psci";
54
54
next-level-cache = <&L2_0>;
55
55
qcom,freq-domain = <&cpufreq_hw 0>;
···
72
70
device_type = "cpu";
73
71
compatible = "qcom,kryo685";
74
72
reg = <0x0 0x100>;
73
+
clocks = <&cpufreq_hw 0>;
75
74
enable-method = "psci";
76
75
next-level-cache = <&L2_100>;
77
76
qcom,freq-domain = <&cpufreq_hw 0>;
···
90
87
device_type = "cpu";
91
88
compatible = "qcom,kryo685";
92
89
reg = <0x0 0x200>;
90
+
clocks = <&cpufreq_hw 0>;
93
91
enable-method = "psci";
94
92
next-level-cache = <&L2_200>;
95
93
qcom,freq-domain = <&cpufreq_hw 0>;
···
108
104
device_type = "cpu";
109
105
compatible = "qcom,kryo685";
110
106
reg = <0x0 0x300>;
107
+
clocks = <&cpufreq_hw 0>;
111
108
enable-method = "psci";
112
109
next-level-cache = <&L2_300>;
113
110
qcom,freq-domain = <&cpufreq_hw 0>;
···
126
121
device_type = "cpu";
127
122
compatible = "qcom,kryo685";
128
123
reg = <0x0 0x400>;
124
+
clocks = <&cpufreq_hw 1>;
129
125
enable-method = "psci";
130
126
next-level-cache = <&L2_400>;
131
127
qcom,freq-domain = <&cpufreq_hw 1>;
···
144
138
device_type = "cpu";
145
139
compatible = "qcom,kryo685";
146
140
reg = <0x0 0x500>;
141
+
clocks = <&cpufreq_hw 1>;
147
142
enable-method = "psci";
148
143
next-level-cache = <&L2_500>;
149
144
qcom,freq-domain = <&cpufreq_hw 1>;
···
156
149
cache-level = <2>;
157
150
next-level-cache = <&L3_0>;
158
151
};
159
-
160
152
};
161
153
162
154
CPU6: cpu@600 {
163
155
device_type = "cpu";
164
156
compatible = "qcom,kryo685";
165
157
reg = <0x0 0x600>;
158
+
clocks = <&cpufreq_hw 1>;
166
159
enable-method = "psci";
167
160
next-level-cache = <&L2_600>;
168
161
qcom,freq-domain = <&cpufreq_hw 1>;
···
180
173
device_type = "cpu";
181
174
compatible = "qcom,kryo685";
182
175
reg = <0x0 0x700>;
176
+
clocks = <&cpufreq_hw 2>;
183
177
enable-method = "psci";
184
178
next-level-cache = <&L2_700>;
185
179
qcom,freq-domain = <&cpufreq_hw 2>;
···
257
249
domain-idle-states {
258
250
CLUSTER_SLEEP_0: cluster-sleep-0 {
259
251
compatible = "domain-idle-state";
260
-
idle-state-name = "cluster-power-collapse";
261
252
arm,psci-suspend-param = <0x4100c344>;
262
253
entry-latency-us = <3263>;
263
254
exit-latency-us = <6562>;
264
255
min-residency-us = <9987>;
265
-
local-timer-stop;
266
256
};
267
257
};
268
258
};
···
659
653
<&ufs_mem_phy_lanes 0>,
660
654
<&ufs_mem_phy_lanes 1>,
661
655
<&ufs_mem_phy_lanes 2>,
662
-
<0>,
656
+
<&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
663
657
<0>;
664
658
};
665
659
···
1493
1487
#address-cells = <3>;
1494
1488
#size-cells = <2>;
1495
1489
1496
-
ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1497
-
<0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
1490
+
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1491
+
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1498
1492
1499
1493
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1500
1494
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
···
1587
1581
#address-cells = <3>;
1588
1582
#size-cells = <2>;
1589
1583
1590
-
ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>,
1591
-
<0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>;
1584
+
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1585
+
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1592
1586
1593
1587
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1594
1588
interrupt-names = "msi";
···
1670
1664
power-domains = <&gcc UFS_PHY_GDSC>;
1671
1665
1672
1666
iommus = <&apps_smmu 0xe0 0x0>;
1667
+
dma-coherent;
1673
1668
1674
1669
clock-names =
1675
1670
"core_clk",
···
1914
1907
};
1915
1908
1916
1909
adreno_smmu: iommu@3da0000 {
1917
-
compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
1910
+
compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu",
1911
+
"qcom,smmu-500", "arm,mmu-500";
1918
1912
reg = <0 0x03da0000 0 0x20000>;
1919
1913
#iommu-cells = <2>;
1920
1914
#global-interrupts = <2>;
···
2133
2125
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2134
2126
};
2135
2127
2136
-
usb_1_qmpphy: phy-wrapper@88e9000 {
2137
-
compatible = "qcom,sm8350-qmp-usb3-phy";
2138
-
reg = <0 0x088e9000 0 0x200>,
2139
-
<0 0x088e8000 0 0x20>;
2140
-
status = "disabled";
2141
-
#address-cells = <2>;
2142
-
#size-cells = <2>;
2143
-
ranges;
2128
+
usb_1_qmpphy: phy@88e9000 {
2129
+
compatible = "qcom,sm8350-qmp-usb3-dp-phy";
2130
+
reg = <0 0x088e8000 0 0x3000>;
2144
2131
2145
2132
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2146
2133
<&rpmhcc RPMH_CXO_CLK>,
2147
-
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2148
-
clock-names = "aux", "ref_clk_src", "com_aux";
2134
+
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2135
+
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2136
+
clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2149
2137
2150
2138
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2151
2139
<&gcc GCC_USB3_PHY_PRIM_BCR>;
2152
2140
reset-names = "phy", "common";
2153
2141
2154
-
usb_1_ssphy: phy@88e9200 {
2155
-
reg = <0 0x088e9200 0 0x200>,
2156
-
<0 0x088e9400 0 0x200>,
2157
-
<0 0x088e9c00 0 0x400>,
2158
-
<0 0x088e9600 0 0x200>,
2159
-
<0 0x088e9800 0 0x200>,
2160
-
<0 0x088e9a00 0 0x100>;
2161
-
#phy-cells = <0>;
2162
-
#clock-cells = <0>;
2163
-
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2164
-
clock-names = "pipe0";
2165
-
clock-output-names = "usb3_phy_pipe_clk_src";
2166
-
};
2142
+
#clock-cells = <1>;
2143
+
#phy-cells = <1>;
2144
+
2145
+
status = "disabled";
2167
2146
};
2168
2147
2169
2148
usb_2_qmpphy: phy-wrapper@88eb000 {
···
2199
2204
2200
2205
system-cache-controller@9200000 {
2201
2206
compatible = "qcom,sm8350-llcc";
2202
-
reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
2203
-
reg-names = "llcc_base", "llcc_broadcast_base";
2207
+
reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
2208
+
<0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
2209
+
<0 0x09600000 0 0x58000>;
2210
+
reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2211
+
"llcc3_base", "llcc_broadcast_base";
2204
2212
};
2205
2213
2206
2214
compute_noc: interconnect@a0c0000 {
···
2256
2258
iommus = <&apps_smmu 0x0 0x0>;
2257
2259
snps,dis_u2_susphy_quirk;
2258
2260
snps,dis_enblslpm_quirk;
2259
-
phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2261
+
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
2260
2262
phy-names = "usb2-phy", "usb3-phy";
2263
+
2264
+
ports {
2265
+
#address-cells = <1>;
2266
+
#size-cells = <0>;
2267
+
2268
+
port@0 {
2269
+
reg = <0>;
2270
+
2271
+
usb_1_dwc3_hs: endpoint {
2272
+
};
2273
+
};
2274
+
2275
+
port@1 {
2276
+
reg = <1>;
2277
+
2278
+
usb_1_dwc3_ss: endpoint {
2279
+
};
2280
+
};
2281
+
};
2261
2282
};
2262
2283
};
2263
2284
···
2433
2416
dpu_intf2_out: endpoint {
2434
2417
remote-endpoint = <&mdss_dsi1_in>;
2435
2418
};
2419
+
};
2420
+
2421
+
port@2 {
2422
+
reg = <2>;
2423
+
dpu_intf0_out: endpoint {
2424
+
remote-endpoint = <&mdss_dp_in>;
2425
+
};
2426
+
};
2427
+
};
2428
+
};
2429
+
2430
+
mdss_dp: displayport-controller@ae90000 {
2431
+
compatible = "qcom,sm8350-dp";
2432
+
reg = <0 0xae90000 0 0x200>,
2433
+
<0 0xae90200 0 0x200>,
2434
+
<0 0xae90400 0 0x600>,
2435
+
<0 0xae91000 0 0x400>,
2436
+
<0 0xae91400 0 0x400>;
2437
+
interrupt-parent = <&mdss>;
2438
+
interrupts = <12>;
2439
+
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2440
+
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
2441
+
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
2442
+
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
2443
+
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
2444
+
clock-names = "core_iface",
2445
+
"core_aux",
2446
+
"ctrl_link",
2447
+
"ctrl_link_iface",
2448
+
"stream_pixel";
2449
+
2450
+
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
2451
+
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
2452
+
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2453
+
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
2454
+
2455
+
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
2456
+
phy-names = "dp";
2457
+
2458
+
#sound-dai-cells = <0>;
2459
+
2460
+
operating-points-v2 = <&dp_opp_table>;
2461
+
power-domains = <&rpmhpd SM8350_MMCX>;
2462
+
2463
+
status = "disabled";
2464
+
2465
+
ports {
2466
+
#address-cells = <1>;
2467
+
#size-cells = <0>;
2468
+
2469
+
port@0 {
2470
+
reg = <0>;
2471
+
mdss_dp_in: endpoint {
2472
+
remote-endpoint = <&dpu_intf0_out>;
2473
+
};
2474
+
};
2475
+
};
2476
+
2477
+
dp_opp_table: opp-table {
2478
+
compatible = "operating-points-v2";
2479
+
2480
+
opp-160000000 {
2481
+
opp-hz = /bits/ 64 <160000000>;
2482
+
required-opps = <&rpmhpd_opp_low_svs>;
2483
+
};
2484
+
2485
+
opp-270000000 {
2486
+
opp-hz = /bits/ 64 <270000000>;
2487
+
required-opps = <&rpmhpd_opp_svs>;
2488
+
};
2489
+
2490
+
opp-540000000 {
2491
+
opp-hz = /bits/ 64 <540000000>;
2492
+
required-opps = <&rpmhpd_opp_svs_l1>;
2493
+
};
2494
+
2495
+
opp-810000000 {
2496
+
opp-hz = /bits/ 64 <810000000>;
2497
+
required-opps = <&rpmhpd_opp_nom>;
2436
2498
};
2437
2499
};
2438
2500
};
···
2719
2623
clocks = <&rpmhcc RPMH_CXO_CLK>,
2720
2624
<&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>,
2721
2625
<&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>,
2722
-
<0>,
2723
-
<0>;
2626
+
<&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2627
+
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
2724
2628
clock-names = "bi_tcxo",
2725
2629
"dsi0_phy_pll_out_byteclk",
2726
2630
"dsi0_phy_pll_out_dsiclk",
···
3336
3240
clock-names = "xo", "alternate";
3337
3241
3338
3242
#freq-domain-cells = <1>;
3243
+
#clock-cells = <1>;
3339
3244
};
3340
3245
3341
3246
cdsp: remoteproc@98900000 {
+50
-6
arch/arm64/boot/dts/qcom/sm8450-hdk.dts
+50
-6
arch/arm64/boot/dts/qcom/sm8450-hdk.dts
···
25
25
};
26
26
27
27
wcd938x: audio-codec {
28
-
compatible = "qcom,wcd9380-codec";
28
+
compatible = "qcom,wcd9385-codec";
29
29
30
30
pinctrl-names = "default";
31
31
pinctrl-0 = <&wcd_default>;
···
85
85
regulator-min-microvolt = <3300000>;
86
86
regulator-max-microvolt = <3300000>;
87
87
enable-active-high;
88
+
};
89
+
90
+
pmic-glink {
91
+
compatible = "qcom,sm8450-pmic-glink", "qcom,pmic-glink";
92
+
#address-cells = <1>;
93
+
#size-cells = <0>;
94
+
95
+
connector@0 {
96
+
compatible = "usb-c-connector";
97
+
reg = <0>;
98
+
power-role = "dual";
99
+
data-role = "dual";
100
+
101
+
ports {
102
+
#address-cells = <1>;
103
+
#size-cells = <0>;
104
+
105
+
port@0 {
106
+
reg = <0>;
107
+
108
+
pmic_glink_hs_in: endpoint {
109
+
remote-endpoint = <&usb_1_dwc3_hs>;
110
+
};
111
+
};
112
+
113
+
port@1 {
114
+
reg = <1>;
115
+
116
+
pmic_glink_ss_in: endpoint {
117
+
remote-endpoint = <&usb_1_dwc3_ss>;
118
+
};
119
+
};
120
+
};
121
+
};
88
122
};
89
123
90
124
vph_pwr: vph-pwr-regulator {
···
377
343
regulator-max-microvolt = <912000>;
378
344
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
379
345
};
380
-
381
346
};
382
347
383
348
regulators-3 {
···
757
724
};
758
725
759
726
&usb_1_dwc3 {
760
-
dr_mode = "peripheral";
727
+
dr_mode = "otg";
728
+
usb-role-switch;
729
+
};
730
+
731
+
&usb_1_dwc3_hs {
732
+
remote-endpoint = <&pmic_glink_hs_in>;
733
+
};
734
+
735
+
&usb_1_dwc3_ss {
736
+
remote-endpoint = <&pmic_glink_ss_in>;
761
737
};
762
738
763
739
&usb_1_hsphy {
···
797
755
spkr_1_sd_n_active: spkr-1-sd-n-active-state {
798
756
pins = "gpio1";
799
757
function = "gpio";
800
-
drive-strength = <4>;
758
+
drive-strength = <16>;
801
759
bias-disable;
802
760
output-low;
803
761
};
···
805
763
spkr_2_sd_n_active: spkr-2-sd-n-active-state {
806
764
pins = "gpio89";
807
765
function = "gpio";
808
-
drive-strength = <4>;
766
+
drive-strength = <16>;
809
767
bias-disable;
810
768
output-low;
811
769
};
812
770
813
-
wcd_default: wcd-default-state {
771
+
wcd_default: wcd-reset-n-active-state {
814
772
pins = "gpio43";
815
773
function = "gpio";
774
+
drive-strength = <16>;
816
775
bias-disable;
776
+
output-low;
817
777
};
818
778
};
-1
arch/arm64/boot/dts/qcom/sm8450-qrd.dts
-1
arch/arm64/boot/dts/qcom/sm8450-qrd.dts
+140
-45
arch/arm64/boot/dts/qcom/sm8450.dtsi
+140
-45
arch/arm64/boot/dts/qcom/sm8450.dtsi
···
11
11
#include <dt-bindings/dma/qcom-gpi.h>
12
12
#include <dt-bindings/gpio/gpio.h>
13
13
#include <dt-bindings/mailbox/qcom-ipcc.h>
14
+
#include <dt-bindings/phy/phy-qcom-qmp.h>
14
15
#include <dt-bindings/power/qcom-rpmpd.h>
15
16
#include <dt-bindings/interconnect/qcom,sm8450.h>
16
17
#include <dt-bindings/soc/qcom,gpr.h>
···
155
154
cache-level = <2>;
156
155
next-level-cache = <&L3_0>;
157
156
};
158
-
159
157
};
160
158
161
159
CPU6: cpu@600 {
···
256
256
domain-idle-states {
257
257
CLUSTER_SLEEP_0: cluster-sleep-0 {
258
258
compatible = "domain-idle-state";
259
-
idle-state-name = "cluster-l3-off";
260
259
arm,psci-suspend-param = <0x41000044>;
261
260
entry-latency-us = <1050>;
262
261
exit-latency-us = <2500>;
263
262
min-residency-us = <5309>;
264
-
local-timer-stop;
265
263
};
266
264
267
265
CLUSTER_SLEEP_1: cluster-sleep-1 {
268
266
compatible = "domain-idle-state";
269
-
idle-state-name = "cluster-power-collapse";
270
267
arm,psci-suspend-param = <0x4100c344>;
271
268
entry-latency-us = <2700>;
272
269
exit-latency-us = <3500>;
273
270
min-residency-us = <13959>;
274
-
local-timer-stop;
275
271
};
276
272
};
277
273
};
···
744
748
<&ufs_mem_phy_lanes 0>,
745
749
<&ufs_mem_phy_lanes 1>,
746
750
<&ufs_mem_phy_lanes 2>,
747
-
<0>;
751
+
<&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
748
752
clock-names = "bi_tcxo",
749
753
"sleep_clk",
750
754
"pcie_0_pipe_clk",
···
1742
1746
#address-cells = <3>;
1743
1747
#size-cells = <2>;
1744
1748
1745
-
ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1746
-
<0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
1749
+
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1750
+
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1747
1751
1748
1752
/*
1749
1753
* MSIs for BDF (1:0.0) only works with Device ID 0x5980.
···
1794
1798
reset-names = "pci";
1795
1799
1796
1800
power-domains = <&gcc PCIE_0_GDSC>;
1797
-
power-domain-names = "gdsc";
1798
1801
1799
1802
phys = <&pcie0_lane>;
1800
1803
phy-names = "pciephy";
···
1857
1862
#address-cells = <3>;
1858
1863
#size-cells = <2>;
1859
1864
1860
-
ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>,
1861
-
<0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>;
1865
+
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1866
+
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1862
1867
1863
1868
/*
1864
1869
* MSIs for BDF (1:0.0) only works with Device ID 0x5a00.
···
1907
1912
reset-names = "pci";
1908
1913
1909
1914
power-domains = <&gcc PCIE_1_GDSC>;
1910
-
power-domain-names = "gdsc";
1911
1915
1912
1916
phys = <&pcie1_lane>;
1913
1917
phy-names = "pciephy";
1914
1918
1915
-
perst-gpio = <&tlmm 97 GPIO_ACTIVE_LOW>;
1916
-
enable-gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>;
1919
+
perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
1920
+
wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
1917
1921
1918
1922
pinctrl-names = "default";
1919
1923
pinctrl-0 = <&pcie1_default_state>;
···
2028
2034
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2029
2035
};
2030
2036
2031
-
usb_1_qmpphy: phy-wrapper@88e9000 {
2032
-
compatible = "qcom,sm8450-qmp-usb3-phy";
2033
-
reg = <0 0x088e9000 0 0x200>,
2034
-
<0 0x088e8000 0 0x20>;
2035
-
status = "disabled";
2036
-
#address-cells = <2>;
2037
-
#size-cells = <2>;
2038
-
ranges;
2037
+
usb_1_qmpphy: phy@88e8000 {
2038
+
compatible = "qcom,sm8450-qmp-usb3-dp-phy";
2039
+
reg = <0 0x088e8000 0 0x3000>;
2039
2040
2040
2041
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2041
2042
<&rpmhcc RPMH_CXO_CLK>,
2042
-
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2043
-
clock-names = "aux", "ref_clk_src", "com_aux";
2043
+
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2044
+
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2045
+
clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2044
2046
2045
2047
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2046
2048
<&gcc GCC_USB3_PHY_PRIM_BCR>;
2047
2049
reset-names = "phy", "common";
2048
2050
2049
-
usb_1_ssphy: phy@88e9200 {
2050
-
reg = <0 0x088e9200 0 0x200>,
2051
-
<0 0x088e9400 0 0x200>,
2052
-
<0 0x088e9c00 0 0x400>,
2053
-
<0 0x088e9600 0 0x200>,
2054
-
<0 0x088e9800 0 0x200>,
2055
-
<0 0x088e9a00 0 0x100>;
2056
-
#phy-cells = <0>;
2057
-
#clock-cells = <0>;
2058
-
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2059
-
clock-names = "pipe0";
2060
-
clock-output-names = "usb3_phy_pipe_clk_src";
2061
-
};
2051
+
#clock-cells = <1>;
2052
+
#phy-cells = <1>;
2053
+
2054
+
status = "disabled";
2062
2055
};
2063
2056
2064
2057
remoteproc_slpi: remoteproc@2400000 {
···
2124
2143
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2125
2144
<&vamacro>;
2126
2145
clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2127
-
assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2128
-
<&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2146
+
assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2147
+
<&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2129
2148
assigned-clock-rates = <19200000>, <19200000>;
2130
2149
2131
2150
#clock-cells = <0>;
···
2744
2763
};
2745
2764
};
2746
2765
2766
+
port@2 {
2767
+
reg = <2>;
2768
+
dpu_intf0_out: endpoint {
2769
+
remote-endpoint = <&mdss_dp0_in>;
2770
+
};
2771
+
};
2747
2772
};
2748
2773
2749
2774
mdp_opp_table: opp-table {
···
2777
2790
2778
2791
opp-500000000 {
2779
2792
opp-hz = /bits/ 64 <500000000>;
2793
+
required-opps = <&rpmhpd_opp_nom>;
2794
+
};
2795
+
};
2796
+
};
2797
+
2798
+
mdss_dp0: displayport-controller@ae90000 {
2799
+
compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";
2800
+
reg = <0 0xae90000 0 0x200>,
2801
+
<0 0xae90200 0 0x200>,
2802
+
<0 0xae90400 0 0xc00>,
2803
+
<0 0xae91000 0 0x400>,
2804
+
<0 0xae91400 0 0x400>;
2805
+
interrupt-parent = <&mdss>;
2806
+
interrupts = <12>;
2807
+
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2808
+
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
2809
+
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
2810
+
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
2811
+
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
2812
+
clock-names = "core_iface",
2813
+
"core_aux",
2814
+
"ctrl_link",
2815
+
"ctrl_link_iface",
2816
+
"stream_pixel";
2817
+
2818
+
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
2819
+
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
2820
+
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2821
+
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
2822
+
2823
+
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
2824
+
phy-names = "dp";
2825
+
2826
+
#sound-dai-cells = <0>;
2827
+
2828
+
operating-points-v2 = <&dp_opp_table>;
2829
+
power-domains = <&rpmhpd SM8450_MMCX>;
2830
+
2831
+
status = "disabled";
2832
+
2833
+
ports {
2834
+
#address-cells = <1>;
2835
+
#size-cells = <0>;
2836
+
2837
+
port@0 {
2838
+
reg = <0>;
2839
+
mdss_dp0_in: endpoint {
2840
+
remote-endpoint = <&dpu_intf0_out>;
2841
+
};
2842
+
};
2843
+
};
2844
+
2845
+
dp_opp_table: opp-table {
2846
+
compatible = "operating-points-v2";
2847
+
2848
+
opp-160000000 {
2849
+
opp-hz = /bits/ 64 <160000000>;
2850
+
required-opps = <&rpmhpd_opp_low_svs>;
2851
+
};
2852
+
2853
+
opp-270000000 {
2854
+
opp-hz = /bits/ 64 <270000000>;
2855
+
required-opps = <&rpmhpd_opp_svs>;
2856
+
};
2857
+
2858
+
opp-540000000 {
2859
+
opp-hz = /bits/ 64 <540000000>;
2860
+
required-opps = <&rpmhpd_opp_svs_l1>;
2861
+
};
2862
+
2863
+
opp-810000000 {
2864
+
opp-hz = /bits/ 64 <810000000>;
2780
2865
required-opps = <&rpmhpd_opp_nom>;
2781
2866
};
2782
2867
};
···
3031
2972
<&mdss_dsi0_phy 1>,
3032
2973
<&mdss_dsi1_phy 0>,
3033
2974
<&mdss_dsi1_phy 1>,
3034
-
<0>, /* dp0 */
3035
-
<0>,
2975
+
<&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2976
+
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
3036
2977
<0>, /* dp1 */
3037
2978
<0>,
3038
2979
<0>, /* dp2 */
···
3628
3569
pins = "gpio76", "gpio77", "gpio78", "gpio79";
3629
3570
function = "qup20";
3630
3571
};
3631
-
3632
3572
};
3633
3573
3634
3574
lpass_tlmm: pinctrl@3440000 {
···
3744
3686
slew-rate = <1>;
3745
3687
bias-bus-hold;
3746
3688
};
3689
+
};
3690
+
};
3691
+
3692
+
sram@146aa000 {
3693
+
compatible = "qcom,sm8450-imem", "syscon", "simple-mfd";
3694
+
reg = <0 0x146aa000 0 0x1000>;
3695
+
ranges = <0 0 0x146aa000 0x1000>;
3696
+
3697
+
#address-cells = <1>;
3698
+
#size-cells = <1>;
3699
+
3700
+
pil-reloc@94c {
3701
+
compatible = "qcom,pil-reloc-info";
3702
+
reg = <0x94c 0xc8>;
3747
3703
};
3748
3704
};
3749
3705
···
4053
3981
4054
3982
system-cache-controller@19200000 {
4055
3983
compatible = "qcom,sm8450-llcc";
4056
-
reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>;
4057
-
reg-names = "llcc_base", "llcc_broadcast_base";
3984
+
reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>,
3985
+
<0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>,
3986
+
<0 0x19a00000 0 0x80000>;
3987
+
reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
3988
+
"llcc3_base", "llcc_broadcast_base";
4058
3989
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
4059
3990
};
4060
3991
···
4078
4003
power-domains = <&gcc UFS_PHY_GDSC>;
4079
4004
4080
4005
iommus = <&apps_smmu 0xe0 0x0>;
4006
+
dma-coherent;
4081
4007
4082
4008
interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
4083
4009
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
···
4229
4153
iommus = <&apps_smmu 0x0 0x0>;
4230
4154
snps,dis_u2_susphy_quirk;
4231
4155
snps,dis_enblslpm_quirk;
4232
-
phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4156
+
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
4233
4157
phy-names = "usb2-phy", "usb3-phy";
4158
+
4159
+
ports {
4160
+
#address-cells = <1>;
4161
+
#size-cells = <0>;
4162
+
4163
+
port@0 {
4164
+
reg = <0>;
4165
+
4166
+
usb_1_dwc3_hs: endpoint {
4167
+
};
4168
+
};
4169
+
4170
+
port@1 {
4171
+
reg = <1>;
4172
+
4173
+
usb_1_dwc3_ss: endpoint {
4174
+
};
4175
+
};
4176
+
};
4234
4177
};
4235
4178
};
4236
4179
+61
-1
arch/arm64/boot/dts/qcom/sm8550-mtp.dts
+61
-1
arch/arm64/boot/dts/qcom/sm8550-mtp.dts
···
27
27
stdout-path = "serial0:115200n8";
28
28
};
29
29
30
+
pmic-glink {
31
+
compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
32
+
#address-cells = <1>;
33
+
#size-cells = <0>;
34
+
35
+
connector@0 {
36
+
compatible = "usb-c-connector";
37
+
reg = <0>;
38
+
power-role = "dual";
39
+
data-role = "dual";
40
+
41
+
ports {
42
+
#address-cells = <1>;
43
+
#size-cells = <0>;
44
+
45
+
port@0 {
46
+
reg = <0>;
47
+
48
+
pmic_glink_hs_in: endpoint {
49
+
remote-endpoint = <&usb_1_dwc3_hs>;
50
+
};
51
+
};
52
+
53
+
port@1 {
54
+
reg = <1>;
55
+
56
+
pmic_glink_ss_in: endpoint {
57
+
remote-endpoint = <&usb_1_dwc3_ss>;
58
+
};
59
+
};
60
+
};
61
+
};
62
+
};
63
+
30
64
vph_pwr: vph-pwr-regulator {
31
65
compatible = "regulator-fixed";
32
66
regulator-name = "vph_pwr";
···
448
414
&pcie0 {
449
415
wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
450
416
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
417
+
418
+
pinctrl-names = "default";
419
+
pinctrl-0 = <&pcie0_default_state>;
420
+
451
421
status = "okay";
452
422
};
453
423
454
424
&pcie0_phy {
455
425
vdda-phy-supply = <&vreg_l1e_0p88>;
456
426
vdda-pll-supply = <&vreg_l3e_1p2>;
427
+
457
428
status = "okay";
458
429
};
459
430
460
431
&pcie1 {
461
432
wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
462
433
perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
434
+
435
+
pinctrl-names = "default";
436
+
pinctrl-0 = <&pcie1_default_state>;
437
+
463
438
status = "okay";
464
439
};
465
440
···
476
433
vdda-phy-supply = <&vreg_l3c_0p91>;
477
434
vdda-pll-supply = <&vreg_l3e_1p2>;
478
435
vdda-qref-supply = <&vreg_l1e_0p88>;
436
+
479
437
status = "okay";
480
438
};
481
439
···
489
445
bias-pull-up;
490
446
power-source = <1>; /* 1.8 V */
491
447
};
448
+
};
449
+
450
+
&pm8550b_eusb2_repeater {
451
+
vdd18-supply = <&vreg_l15b_1p8>;
452
+
vdd3-supply = <&vreg_l5b_3p1>;
492
453
};
493
454
494
455
&qupv3_id_0 {
···
595
546
};
596
547
597
548
&usb_1_dwc3 {
598
-
dr_mode = "peripheral";
549
+
dr_mode = "otg";
550
+
usb-role-switch;
551
+
};
552
+
553
+
&usb_1_dwc3_hs {
554
+
remote-endpoint = <&pmic_glink_hs_in>;
555
+
};
556
+
557
+
&usb_1_dwc3_ss {
558
+
remote-endpoint = <&pmic_glink_ss_in>;
599
559
};
600
560
601
561
&usb_1_hsphy {
602
562
vdd-supply = <&vreg_l1e_0p88>;
603
563
vdda12-supply = <&vreg_l3e_1p2>;
564
+
565
+
phys = <&pm8550b_eusb2_repeater>;
604
566
605
567
status = "okay";
606
568
};
+439
arch/arm64/boot/dts/qcom/sm8550-qrd.dts
+439
arch/arm64/boot/dts/qcom/sm8550-qrd.dts
···
1
+
// SPDX-License-Identifier: BSD-3-Clause
2
+
/*
3
+
* Copyright (c) 2023 Linaro Limited
4
+
*/
5
+
6
+
/dts-v1/;
7
+
8
+
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
9
+
#include "sm8550.dtsi"
10
+
#include "pm8010.dtsi"
11
+
#include "pm8550.dtsi"
12
+
#include "pm8550b.dtsi"
13
+
#include "pm8550ve.dtsi"
14
+
#include "pm8550vs.dtsi"
15
+
#include "pmk8550.dtsi"
16
+
#include "pmr735d.dtsi"
17
+
18
+
/ {
19
+
model = "Qualcomm Technologies, Inc. SM8550 QRD";
20
+
compatible = "qcom,sm8550-qrd", "qcom,sm8550";
21
+
22
+
aliases {
23
+
serial0 = &uart7;
24
+
};
25
+
26
+
chosen {
27
+
stdout-path = "serial0:115200n8";
28
+
};
29
+
30
+
vph_pwr: vph-pwr-regulator {
31
+
compatible = "regulator-fixed";
32
+
regulator-name = "vph_pwr";
33
+
regulator-min-microvolt = <3700000>;
34
+
regulator-max-microvolt = <3700000>;
35
+
36
+
regulator-always-on;
37
+
regulator-boot-on;
38
+
};
39
+
};
40
+
41
+
&apps_rsc {
42
+
regulators-0 {
43
+
compatible = "qcom,pm8550-rpmh-regulators";
44
+
qcom,pmic-id = "b";
45
+
46
+
vdd-bob1-supply = <&vph_pwr>;
47
+
vdd-bob2-supply = <&vph_pwr>;
48
+
vdd-l1-l4-l10-supply = <&vreg_s6g_1p86>;
49
+
vdd-l2-l13-l14-supply = <&vreg_bob1>;
50
+
vdd-l3-supply = <&vreg_s4g_1p25>;
51
+
vdd-l5-l16-supply = <&vreg_bob1>;
52
+
vdd-l6-l7-supply = <&vreg_bob1>;
53
+
vdd-l8-l9-supply = <&vreg_bob1>;
54
+
vdd-l11-supply = <&vreg_s4g_1p25>;
55
+
vdd-l12-supply = <&vreg_s6g_1p86>;
56
+
vdd-l15-supply = <&vreg_s6g_1p86>;
57
+
vdd-l17-supply = <&vreg_bob2>;
58
+
59
+
vreg_bob1: bob1 {
60
+
regulator-name = "vreg_bob1";
61
+
regulator-min-microvolt = <3296000>;
62
+
regulator-max-microvolt = <3960000>;
63
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
64
+
};
65
+
66
+
vreg_bob2: bob2 {
67
+
regulator-name = "vreg_bob2";
68
+
regulator-min-microvolt = <2720000>;
69
+
regulator-max-microvolt = <3960000>;
70
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
71
+
};
72
+
73
+
vreg_l1b_1p8: ldo1 {
74
+
regulator-name = "vreg_l1b_1p8";
75
+
regulator-min-microvolt = <1800000>;
76
+
regulator-max-microvolt = <1800000>;
77
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
78
+
};
79
+
80
+
vreg_l2b_3p0: ldo2 {
81
+
regulator-name = "vreg_l2b_3p0";
82
+
regulator-min-microvolt = <3008000>;
83
+
regulator-max-microvolt = <3008000>;
84
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
85
+
};
86
+
87
+
vreg_l5b_3p1: ldo5 {
88
+
regulator-name = "vreg_l5b_3p1";
89
+
regulator-min-microvolt = <3104000>;
90
+
regulator-max-microvolt = <3104000>;
91
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
92
+
};
93
+
94
+
vreg_l6b_1p8: ldo6 {
95
+
regulator-name = "vreg_l6b_1p8";
96
+
regulator-min-microvolt = <1800000>;
97
+
regulator-max-microvolt = <3008000>;
98
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
99
+
};
100
+
101
+
vreg_l7b_1p8: ldo7 {
102
+
regulator-name = "vreg_l7b_1p8";
103
+
regulator-min-microvolt = <1800000>;
104
+
regulator-max-microvolt = <3008000>;
105
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
106
+
};
107
+
108
+
vreg_l8b_1p8: ldo8 {
109
+
regulator-name = "vreg_l8b_1p8";
110
+
regulator-min-microvolt = <1800000>;
111
+
regulator-max-microvolt = <3008000>;
112
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
113
+
};
114
+
115
+
vreg_l9b_2p9: ldo9 {
116
+
regulator-name = "vreg_l9b_2p9";
117
+
regulator-min-microvolt = <2960000>;
118
+
regulator-max-microvolt = <3008000>;
119
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
120
+
};
121
+
122
+
vreg_l11b_1p2: ldo11 {
123
+
regulator-name = "vreg_l11b_1p2";
124
+
regulator-min-microvolt = <1200000>;
125
+
regulator-max-microvolt = <1504000>;
126
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
127
+
};
128
+
129
+
vreg_l12b_1p8: ldo12 {
130
+
regulator-name = "vreg_l12b_1p8";
131
+
regulator-min-microvolt = <1800000>;
132
+
regulator-max-microvolt = <1800000>;
133
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
134
+
};
135
+
136
+
vreg_l13b_3p0: ldo13 {
137
+
regulator-name = "vreg_l13b_3p0";
138
+
regulator-min-microvolt = <3000000>;
139
+
regulator-max-microvolt = <3000000>;
140
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
141
+
};
142
+
143
+
vreg_l14b_3p2: ldo14 {
144
+
regulator-name = "vreg_l14b_3p2";
145
+
regulator-min-microvolt = <3200000>;
146
+
regulator-max-microvolt = <3200000>;
147
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
148
+
};
149
+
150
+
vreg_l15b_1p8: ldo15 {
151
+
regulator-name = "vreg_l15b_1p8";
152
+
regulator-min-microvolt = <1800000>;
153
+
regulator-max-microvolt = <1800000>;
154
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
155
+
};
156
+
157
+
vreg_l16b_2p8: ldo16 {
158
+
regulator-name = "vreg_l16b_2p8";
159
+
regulator-min-microvolt = <2800000>;
160
+
regulator-max-microvolt = <2800000>;
161
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
162
+
};
163
+
164
+
vreg_l17b_2p5: ldo17 {
165
+
regulator-name = "vreg_l17b_2p5";
166
+
regulator-min-microvolt = <2504000>;
167
+
regulator-max-microvolt = <2504000>;
168
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
169
+
};
170
+
};
171
+
172
+
regulators-1 {
173
+
compatible = "qcom,pm8550vs-rpmh-regulators";
174
+
qcom,pmic-id = "c";
175
+
176
+
vdd-l1-supply = <&vreg_s4g_1p25>;
177
+
vdd-l2-supply = <&vreg_s4e_0p95>;
178
+
vdd-l3-supply = <&vreg_s4e_0p95>;
179
+
180
+
vreg_l3c_0p9: ldo3 {
181
+
regulator-name = "vreg_l3c_0p9";
182
+
regulator-min-microvolt = <880000>;
183
+
regulator-max-microvolt = <912000>;
184
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
185
+
};
186
+
};
187
+
188
+
regulators-2 {
189
+
compatible = "qcom,pm8550vs-rpmh-regulators";
190
+
qcom,pmic-id = "d";
191
+
192
+
vdd-l1-supply = <&vreg_s4e_0p95>;
193
+
vdd-l2-supply = <&vreg_s4e_0p95>;
194
+
vdd-l3-supply = <&vreg_s4e_0p95>;
195
+
196
+
vreg_l1d_0p88: ldo1 {
197
+
regulator-name = "vreg_l1d_0p88";
198
+
regulator-min-microvolt = <880000>;
199
+
regulator-max-microvolt = <920000>;
200
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
201
+
};
202
+
203
+
/* ldo2 supplies SM8550 VDD_LPI_MX */
204
+
};
205
+
206
+
regulators-3 {
207
+
compatible = "qcom,pm8550vs-rpmh-regulators";
208
+
qcom,pmic-id = "e";
209
+
210
+
vdd-l1-supply = <&vreg_s4e_0p95>;
211
+
vdd-l2-supply = <&vreg_s4e_0p95>;
212
+
vdd-l3-supply = <&vreg_s4g_1p25>;
213
+
vdd-s4-supply = <&vph_pwr>;
214
+
vdd-s5-supply = <&vph_pwr>;
215
+
216
+
vreg_s4e_0p95: smps4 {
217
+
regulator-name = "vreg_s4e_0p95";
218
+
regulator-min-microvolt = <904000>;
219
+
regulator-max-microvolt = <984000>;
220
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
221
+
};
222
+
223
+
vreg_s5e_1p08: smps5 {
224
+
regulator-name = "vreg_s5e_1p08";
225
+
regulator-min-microvolt = <1080000>;
226
+
regulator-max-microvolt = <1120000>;
227
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
228
+
};
229
+
230
+
vreg_l1e_0p88: ldo1 {
231
+
regulator-name = "vreg_l1e_0p88";
232
+
regulator-min-microvolt = <880000>;
233
+
regulator-max-microvolt = <880000>;
234
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
235
+
};
236
+
237
+
vreg_l2e_0p9: ldo2 {
238
+
regulator-name = "vreg_l2e_0p9";
239
+
regulator-min-microvolt = <904000>;
240
+
regulator-max-microvolt = <970000>;
241
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
242
+
};
243
+
244
+
vreg_l3e_1p2: ldo3 {
245
+
regulator-name = "vreg_l3e_1p2";
246
+
regulator-min-microvolt = <1200000>;
247
+
regulator-max-microvolt = <1200000>;
248
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
249
+
};
250
+
};
251
+
252
+
regulators-4 {
253
+
compatible = "qcom,pm8550ve-rpmh-regulators";
254
+
qcom,pmic-id = "f";
255
+
256
+
vdd-l1-supply = <&vreg_s4e_0p95>;
257
+
vdd-l2-supply = <&vreg_s4e_0p95>;
258
+
vdd-l3-supply = <&vreg_s4e_0p95>;
259
+
vdd-s4-supply = <&vph_pwr>;
260
+
261
+
vreg_s4f_0p5: smps4 {
262
+
regulator-name = "vreg_s4f_0p5";
263
+
regulator-min-microvolt = <500000>;
264
+
regulator-max-microvolt = <700000>;
265
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
266
+
};
267
+
268
+
vreg_l1f_0p9: ldo1 {
269
+
regulator-name = "vreg_l1f_0p9";
270
+
regulator-min-microvolt = <912000>;
271
+
regulator-max-microvolt = <912000>;
272
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
273
+
};
274
+
275
+
vreg_l2f_0p88: ldo2 {
276
+
regulator-name = "vreg_l2f_0p88";
277
+
regulator-min-microvolt = <880000>;
278
+
regulator-max-microvolt = <912000>;
279
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
280
+
};
281
+
282
+
vreg_l3f_0p88: ldo3 {
283
+
regulator-name = "vreg_l3f_0p88";
284
+
regulator-min-microvolt = <880000>;
285
+
regulator-max-microvolt = <912000>;
286
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
287
+
};
288
+
};
289
+
290
+
regulators-5 {
291
+
compatible = "qcom,pm8550vs-rpmh-regulators";
292
+
qcom,pmic-id = "g";
293
+
294
+
vdd-l1-supply = <&vreg_s4g_1p25>;
295
+
vdd-l2-supply = <&vreg_s4g_1p25>;
296
+
vdd-l3-supply = <&vreg_s4g_1p25>;
297
+
vdd-s1-supply = <&vph_pwr>;
298
+
vdd-s2-supply = <&vph_pwr>;
299
+
vdd-s3-supply = <&vph_pwr>;
300
+
vdd-s4-supply = <&vph_pwr>;
301
+
vdd-s5-supply = <&vph_pwr>;
302
+
vdd-s6-supply = <&vph_pwr>;
303
+
304
+
vreg_s1g_1p25: smps1 {
305
+
regulator-name = "vreg_s1g_1p25";
306
+
regulator-min-microvolt = <1200000>;
307
+
regulator-max-microvolt = <1300000>;
308
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
309
+
};
310
+
311
+
vreg_s2g_0p85: smps2 {
312
+
regulator-name = "vreg_s2g_0p85";
313
+
regulator-min-microvolt = <800000>;
314
+
regulator-max-microvolt = <1000000>;
315
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
316
+
};
317
+
318
+
vreg_s3g_0p8: smps3 {
319
+
regulator-name = "vreg_s3g_0p8";
320
+
regulator-min-microvolt = <300000>;
321
+
regulator-max-microvolt = <1004000>;
322
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
323
+
};
324
+
325
+
vreg_s4g_1p25: smps4 {
326
+
regulator-name = "vreg_s4g_1p25";
327
+
regulator-min-microvolt = <1200000>;
328
+
regulator-max-microvolt = <1352000>;
329
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
330
+
};
331
+
332
+
vreg_s5g_0p85: smps5 {
333
+
regulator-name = "vreg_s5g_0p85";
334
+
regulator-min-microvolt = <500000>;
335
+
regulator-max-microvolt = <1004000>;
336
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
337
+
};
338
+
339
+
vreg_s6g_1p86: smps6 {
340
+
regulator-name = "vreg_s6g_1p86";
341
+
regulator-min-microvolt = <1800000>;
342
+
regulator-max-microvolt = <2000000>;
343
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
344
+
};
345
+
346
+
vreg_l1g_1p2: ldo1 {
347
+
regulator-name = "vreg_l1g_1p2";
348
+
regulator-min-microvolt = <1200000>;
349
+
regulator-max-microvolt = <1200000>;
350
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
351
+
};
352
+
353
+
vreg_l3g_1p2: ldo3 {
354
+
regulator-name = "vreg_l3g_1p2";
355
+
regulator-min-microvolt = <1200000>;
356
+
regulator-max-microvolt = <1200000>;
357
+
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
358
+
};
359
+
};
360
+
};
361
+
362
+
&qupv3_id_0 {
363
+
status = "okay";
364
+
};
365
+
366
+
&remoteproc_adsp {
367
+
firmware-name = "qcom/sm8550/adsp.mbn",
368
+
"qcom/sm8550/adsp_dtb.mbn";
369
+
status = "okay";
370
+
};
371
+
372
+
&remoteproc_cdsp {
373
+
firmware-name = "qcom/sm8550/cdsp.mbn",
374
+
"qcom/sm8550/cdsp_dtb.mbn";
375
+
status = "okay";
376
+
};
377
+
378
+
&remoteproc_mpss {
379
+
firmware-name = "qcom/sm8550/modem.mbn",
380
+
"qcom/sm8550/modem_dtb.mbn";
381
+
status = "okay";
382
+
};
383
+
384
+
&sleep_clk {
385
+
clock-frequency = <32000>;
386
+
};
387
+
388
+
&tlmm {
389
+
gpio-reserved-ranges = <32 8>;
390
+
};
391
+
392
+
&uart7 {
393
+
status = "okay";
394
+
};
395
+
396
+
&ufs_mem_hc {
397
+
reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
398
+
vcc-supply = <&vreg_l17b_2p5>;
399
+
vcc-max-microamp = <1300000>;
400
+
vccq-supply = <&vreg_l1g_1p2>;
401
+
vccq-max-microamp = <1200000>;
402
+
vccq2-supply = <&vreg_l3g_1p2>;
403
+
vccq2-max-microamp = <100>;
404
+
405
+
status = "okay";
406
+
};
407
+
408
+
&ufs_mem_phy {
409
+
vdda-phy-supply = <&vreg_l1d_0p88>;
410
+
vdda-pll-supply = <&vreg_l3e_1p2>;
411
+
412
+
status = "okay";
413
+
};
414
+
415
+
&usb_1 {
416
+
status = "okay";
417
+
};
418
+
419
+
&usb_1_dwc3 {
420
+
dr_mode = "peripheral";
421
+
};
422
+
423
+
&usb_1_hsphy {
424
+
vdd-supply = <&vreg_l1e_0p88>;
425
+
vdda12-supply = <&vreg_l3e_1p2>;
426
+
427
+
status = "okay";
428
+
};
429
+
430
+
&usb_dp_qmpphy {
431
+
vdda-phy-supply = <&vreg_l3e_1p2>;
432
+
vdda-pll-supply = <&vreg_l3f_0p88>;
433
+
434
+
status = "okay";
435
+
};
436
+
437
+
&xo_board {
438
+
clock-frequency = <76800000>;
439
+
};
+87
-72
arch/arm64/boot/dts/qcom/sm8550.dtsi
+87
-72
arch/arm64/boot/dts/qcom/sm8550.dtsi
···
66
66
67
67
CPU0: cpu@0 {
68
68
device_type = "cpu";
69
-
compatible = "qcom,kryo";
69
+
compatible = "arm,cortex-a510";
70
70
reg = <0 0>;
71
+
clocks = <&cpufreq_hw 0>;
71
72
enable-method = "psci";
72
73
next-level-cache = <&L2_0>;
73
74
power-domains = <&CPU_PD0>;
···
90
89
91
90
CPU1: cpu@100 {
92
91
device_type = "cpu";
93
-
compatible = "qcom,kryo";
92
+
compatible = "arm,cortex-a510";
94
93
reg = <0 0x100>;
94
+
clocks = <&cpufreq_hw 0>;
95
95
enable-method = "psci";
96
96
next-level-cache = <&L2_100>;
97
97
power-domains = <&CPU_PD1>;
···
110
108
111
109
CPU2: cpu@200 {
112
110
device_type = "cpu";
113
-
compatible = "qcom,kryo";
111
+
compatible = "arm,cortex-a510";
114
112
reg = <0 0x200>;
113
+
clocks = <&cpufreq_hw 0>;
115
114
enable-method = "psci";
116
115
next-level-cache = <&L2_200>;
117
116
power-domains = <&CPU_PD2>;
···
130
127
131
128
CPU3: cpu@300 {
132
129
device_type = "cpu";
133
-
compatible = "qcom,kryo";
130
+
compatible = "arm,cortex-a715";
134
131
reg = <0 0x300>;
132
+
clocks = <&cpufreq_hw 1>;
135
133
enable-method = "psci";
136
134
next-level-cache = <&L2_300>;
137
135
power-domains = <&CPU_PD3>;
···
150
146
151
147
CPU4: cpu@400 {
152
148
device_type = "cpu";
153
-
compatible = "qcom,kryo";
149
+
compatible = "arm,cortex-a715";
154
150
reg = <0 0x400>;
151
+
clocks = <&cpufreq_hw 1>;
155
152
enable-method = "psci";
156
153
next-level-cache = <&L2_400>;
157
154
power-domains = <&CPU_PD4>;
···
170
165
171
166
CPU5: cpu@500 {
172
167
device_type = "cpu";
173
-
compatible = "qcom,kryo";
168
+
compatible = "arm,cortex-a710";
174
169
reg = <0 0x500>;
170
+
clocks = <&cpufreq_hw 1>;
175
171
enable-method = "psci";
176
172
next-level-cache = <&L2_500>;
177
173
power-domains = <&CPU_PD5>;
···
190
184
191
185
CPU6: cpu@600 {
192
186
device_type = "cpu";
193
-
compatible = "qcom,kryo";
187
+
compatible = "arm,cortex-a710";
194
188
reg = <0 0x600>;
189
+
clocks = <&cpufreq_hw 1>;
195
190
enable-method = "psci";
196
191
next-level-cache = <&L2_600>;
197
192
power-domains = <&CPU_PD6>;
···
210
203
211
204
CPU7: cpu@700 {
212
205
device_type = "cpu";
213
-
compatible = "qcom,kryo";
206
+
compatible = "arm,cortex-x3";
214
207
reg = <0 0x700>;
208
+
clocks = <&cpufreq_hw 2>;
215
209
enable-method = "psci";
216
210
next-level-cache = <&L2_700>;
217
211
power-domains = <&CPU_PD7>;
···
419
411
reg = <0 0xd8100000 0 0x40000>;
420
412
no-map;
421
413
};
422
-
423
414
424
415
hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 {
425
416
reg = <0 0x811d0000 0 0x30000>;
···
1660
1653
reg-names = "parf", "dbi", "elbi", "atu", "config";
1661
1654
#address-cells = <3>;
1662
1655
#size-cells = <2>;
1663
-
ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1664
-
<0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
1656
+
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1657
+
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1665
1658
bus-range = <0x00 0xff>;
1666
1659
1667
1660
dma-coherent;
···
1679
1672
<0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1680
1673
<0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1681
1674
1682
-
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1683
-
<&gcc GCC_PCIE_0_AUX_CLK>,
1675
+
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1684
1676
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1685
1677
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1686
1678
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1687
1679
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1688
1680
<&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
1689
1681
<&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>;
1690
-
clock-names = "pipe",
1691
-
"aux",
1682
+
clock-names = "aux",
1692
1683
"cfg",
1693
1684
"bus_master",
1694
1685
"bus_slave",
1695
1686
"slave_q2a",
1696
1687
"ddrss_sf_tbu",
1697
-
"aggre0";
1688
+
"noc_aggr";
1698
1689
1699
-
interconnect-names = "pcie-mem";
1700
-
interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>;
1690
+
interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
1691
+
<&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>;
1692
+
interconnect-names = "pcie-mem", "cpu-pcie";
1701
1693
1702
1694
iommus = <&apps_smmu 0x1400 0x7f>;
1703
1695
iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
···
1709
1703
1710
1704
phys = <&pcie0_phy>;
1711
1705
phy-names = "pciephy";
1712
-
1713
-
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
1714
-
wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
1715
-
1716
-
pinctrl-names = "default";
1717
-
pinctrl-0 = <&pcie0_default_state>;
1718
1706
1719
1707
status = "disabled";
1720
1708
};
···
1752
1752
reg-names = "parf", "dbi", "elbi", "atu", "config";
1753
1753
#address-cells = <3>;
1754
1754
#size-cells = <2>;
1755
-
ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>,
1756
-
<0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>;
1755
+
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1756
+
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1757
1757
bus-range = <0x00 0xff>;
1758
1758
1759
1759
dma-coherent;
···
1771
1771
<0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1772
1772
<0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1773
1773
1774
-
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1775
-
<&gcc GCC_PCIE_1_AUX_CLK>,
1774
+
clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
1776
1775
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1777
1776
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1778
1777
<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
···
1779
1780
<&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
1780
1781
<&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
1781
1782
<&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
1782
-
clock-names = "pipe",
1783
-
"aux",
1783
+
clock-names = "aux",
1784
1784
"cfg",
1785
1785
"bus_master",
1786
1786
"bus_slave",
1787
1787
"slave_q2a",
1788
1788
"ddrss_sf_tbu",
1789
-
"aggre1",
1790
-
"cnoc_pcie_sf_axi";
1789
+
"noc_aggr",
1790
+
"cnoc_sf_axi";
1791
1791
1792
1792
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1793
1793
assigned-clock-rates = <19200000>;
1794
1794
1795
-
interconnect-names = "pcie-mem";
1796
-
interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>;
1795
+
interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
1796
+
<&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>;
1797
+
interconnect-names = "pcie-mem", "cpu-pcie";
1797
1798
1798
1799
iommus = <&apps_smmu 0x1480 0x7f>;
1799
1800
iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
···
1801
1802
1802
1803
resets = <&gcc GCC_PCIE_1_BCR>,
1803
1804
<&gcc GCC_PCIE_1_LINK_DOWN_BCR>;
1804
-
reset-names = "pci",
1805
-
"pcie_1_link_down_reset";
1805
+
reset-names = "pci", "link_down";
1806
1806
1807
1807
power-domains = <&gcc PCIE_1_GDSC>;
1808
1808
1809
1809
phys = <&pcie1_phy>;
1810
1810
phy-names = "pciephy";
1811
-
1812
-
perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
1813
-
enable-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
1814
-
1815
-
pinctrl-names = "default";
1816
-
pinctrl-0 = <&pcie1_default_state>;
1817
1811
1818
1812
status = "disabled";
1819
1813
};
···
1815
1823
compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy";
1816
1824
reg = <0x0 0x01c0e000 0x0 0x2000>;
1817
1825
1818
-
clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
1826
+
clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
1819
1827
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1820
1828
<&tcsr TCSR_PCIE_1_CLKREF_EN>,
1821
1829
<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
1822
-
<&gcc GCC_PCIE_1_PIPE_CLK>,
1823
-
<&gcc GCC_PCIE_1_PHY_AUX_CLK>;
1830
+
<&gcc GCC_PCIE_1_PIPE_CLK>;
1824
1831
clock-names = "aux", "cfg_ahb", "ref", "rchng",
1825
-
"pipe", "aux_phy";
1832
+
"pipe";
1826
1833
1827
1834
resets = <&gcc GCC_PCIE_1_PHY_BCR>,
1828
1835
<&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>;
1829
-
reset-names = "phy", "nocsr";
1836
+
reset-names = "phy", "phy_nocsr";
1830
1837
1831
1838
assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1832
1839
assigned-clock-rates = <100000000>;
···
1896
1905
required-opps = <&rpmhpd_opp_nom>;
1897
1906
1898
1907
iommus = <&apps_smmu 0x60 0x0>;
1908
+
dma-coherent;
1899
1909
1900
1910
interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
1901
1911
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
···
1989
1997
lpass_tlmm: pinctrl@6e80000 {
1990
1998
compatible = "qcom,sm8550-lpass-lpi-pinctrl";
1991
1999
reg = <0 0x06e80000 0 0x20000>,
1992
-
<0 0x0725a000 0 0x10000>;
2000
+
<0 0x07250000 0 0x10000>;
1993
2001
gpio-controller;
1994
2002
#gpio-cells = <2>;
1995
2003
gpio-ranges = <&lpass_tlmm 0 0 23>;
···
2202
2210
2203
2211
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2204
2212
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
2205
-
assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
2213
+
assigned-clock-parents = <&mdss_dsi0_phy 0>,
2214
+
<&mdss_dsi0_phy 1>;
2206
2215
2207
2216
operating-points-v2 = <&mdss_dsi_opp_table>;
2208
2217
···
2295
2302
2296
2303
power-domains = <&rpmhpd SM8550_MMCX>;
2297
2304
2298
-
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
2299
-
assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
2305
+
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
2306
+
<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
2307
+
assigned-clock-parents = <&mdss_dsi1_phy 0>,
2308
+
<&mdss_dsi1_phy 1>;
2300
2309
2301
2310
operating-points-v2 = <&mdss_dsi_opp_table>;
2302
2311
···
2462
2467
phys = <&usb_1_hsphy>,
2463
2468
<&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
2464
2469
phy-names = "usb2-phy", "usb3-phy";
2470
+
2471
+
ports {
2472
+
#address-cells = <1>;
2473
+
#size-cells = <0>;
2474
+
2475
+
port@0 {
2476
+
reg = <0>;
2477
+
2478
+
usb_1_dwc3_hs: endpoint {
2479
+
};
2480
+
};
2481
+
2482
+
port@1 {
2483
+
reg = <1>;
2484
+
2485
+
usb_1_dwc3_ss: endpoint {
2486
+
};
2487
+
};
2488
+
};
2465
2489
};
2466
2490
};
2467
2491
···
2705
2691
pins = "gpio28", "gpio29";
2706
2692
function = "qup1_se0";
2707
2693
drive-strength = <2>;
2708
-
bias-pull-up;
2694
+
bias-pull-up = <2200>;
2709
2695
};
2710
2696
2711
2697
qup_i2c1_data_clk: qup-i2c1-data-clk-state {
···
2713
2699
pins = "gpio32", "gpio33";
2714
2700
function = "qup1_se1";
2715
2701
drive-strength = <2>;
2716
-
bias-pull-up;
2702
+
bias-pull-up = <2200>;
2717
2703
};
2718
2704
2719
2705
qup_i2c2_data_clk: qup-i2c2-data-clk-state {
···
2721
2707
pins = "gpio36", "gpio37";
2722
2708
function = "qup1_se2";
2723
2709
drive-strength = <2>;
2724
-
bias-pull-up;
2710
+
bias-pull-up = <2200>;
2725
2711
};
2726
2712
2727
2713
qup_i2c3_data_clk: qup-i2c3-data-clk-state {
···
2729
2715
pins = "gpio40", "gpio41";
2730
2716
function = "qup1_se3";
2731
2717
drive-strength = <2>;
2732
-
bias-pull-up;
2718
+
bias-pull-up = <2200>;
2733
2719
};
2734
2720
2735
2721
qup_i2c4_data_clk: qup-i2c4-data-clk-state {
···
2737
2723
pins = "gpio44", "gpio45";
2738
2724
function = "qup1_se4";
2739
2725
drive-strength = <2>;
2740
-
bias-pull-up;
2726
+
bias-pull-up = <2200>;
2741
2727
};
2742
2728
2743
2729
qup_i2c5_data_clk: qup-i2c5-data-clk-state {
···
2745
2731
pins = "gpio52", "gpio53";
2746
2732
function = "qup1_se5";
2747
2733
drive-strength = <2>;
2748
-
bias-pull-up;
2734
+
bias-pull-up = <2200>;
2749
2735
};
2750
2736
2751
2737
qup_i2c6_data_clk: qup-i2c6-data-clk-state {
···
2753
2739
pins = "gpio48", "gpio49";
2754
2740
function = "qup1_se6";
2755
2741
drive-strength = <2>;
2756
-
bias-pull-up;
2742
+
bias-pull-up = <2200>;
2757
2743
};
2758
2744
2759
2745
qup_i2c8_data_clk: qup-i2c8-data-clk-state {
···
2761
2747
pins = "gpio57";
2762
2748
function = "qup2_se0_l1_mira";
2763
2749
drive-strength = <2>;
2764
-
bias-pull-up;
2750
+
bias-pull-up = <2200>;
2765
2751
};
2766
2752
2767
2753
sda-pins {
2768
2754
pins = "gpio56";
2769
2755
function = "qup2_se0_l0_mira";
2770
2756
drive-strength = <2>;
2771
-
bias-pull-up;
2757
+
bias-pull-up = <2200>;
2772
2758
};
2773
2759
};
2774
2760
···
2777
2763
pins = "gpio60", "gpio61";
2778
2764
function = "qup2_se1";
2779
2765
drive-strength = <2>;
2780
-
bias-pull-up;
2766
+
bias-pull-up = <2200>;
2781
2767
};
2782
2768
2783
2769
qup_i2c10_data_clk: qup-i2c10-data-clk-state {
···
2785
2771
pins = "gpio64", "gpio65";
2786
2772
function = "qup2_se2";
2787
2773
drive-strength = <2>;
2788
-
bias-pull-up;
2774
+
bias-pull-up = <2200>;
2789
2775
};
2790
2776
2791
2777
qup_i2c11_data_clk: qup-i2c11-data-clk-state {
···
2793
2779
pins = "gpio68", "gpio69";
2794
2780
function = "qup2_se3";
2795
2781
drive-strength = <2>;
2796
-
bias-pull-up;
2782
+
bias-pull-up = <2200>;
2797
2783
};
2798
2784
2799
2785
qup_i2c12_data_clk: qup-i2c12-data-clk-state {
···
2801
2787
pins = "gpio2", "gpio3";
2802
2788
function = "qup2_se4";
2803
2789
drive-strength = <2>;
2804
-
bias-pull-up;
2790
+
bias-pull-up = <2200>;
2805
2791
};
2806
2792
2807
2793
qup_i2c13_data_clk: qup-i2c13-data-clk-state {
···
2809
2795
pins = "gpio80", "gpio81";
2810
2796
function = "qup2_se5";
2811
2797
drive-strength = <2>;
2812
-
bias-pull-up;
2798
+
bias-pull-up = <2200>;
2813
2799
};
2814
2800
2815
2801
qup_i2c15_data_clk: qup-i2c15-data-clk-state {
···
2817
2803
pins = "gpio72", "gpio106";
2818
2804
function = "qup2_se7";
2819
2805
drive-strength = <2>;
2820
-
bias-pull-up;
2806
+
bias-pull-up = <2200>;
2821
2807
};
2822
2808
2823
2809
qup_spi0_cs: qup-spi0-cs-state {
2824
-
cs-pins {
2825
-
pins = "gpio31";
2826
-
function = "qup1_se0";
2827
-
};
2810
+
pins = "gpio31";
2811
+
function = "qup1_se0";
2812
+
drive-strength = <6>;
2813
+
bias-disable;
2828
2814
};
2829
2815
2830
2816
qup_spi0_data_clk: qup-spi0-data-clk-state {
···
3185
3171
3186
3172
intc: interrupt-controller@17100000 {
3187
3173
compatible = "arm,gic-v3";
3188
-
reg = <0 0x17100000 0 0x10000>, /* GICD */
3174
+
reg = <0 0x17100000 0 0x10000>, /* GICD */
3189
3175
<0 0x17180000 0 0x200000>; /* GICR * 8 */
3190
3176
ranges;
3191
3177
#interrupt-cells = <3>;
···
3353
3339
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
3354
3340
interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
3355
3341
#freq-domain-cells = <1>;
3342
+
#clock-cells = <1>;
3356
3343
};
3357
3344
3358
3345
pmu@24091000 {
···
3406
3391
};
3407
3392
3408
3393
pmu@240b6400 {
3409
-
compatible = "qcom,sm8550-cpu-bwmon", "qcom,msm8998-bwmon";
3394
+
compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon";
3410
3395
reg = <0 0x240b6400 0 0x600>;
3411
3396
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
3412
3397
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
+356
include/dt-bindings/clock/qcom,ipq5332-gcc.h
+356
include/dt-bindings/clock/qcom,ipq5332-gcc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_IPQ5332_H
7
+
#define _DT_BINDINGS_CLK_QCOM_GCC_IPQ5332_H
8
+
9
+
#define GPLL0_MAIN 0
10
+
#define GPLL0 1
11
+
#define GPLL2_MAIN 2
12
+
#define GPLL2 3
13
+
#define GPLL4_MAIN 4
14
+
#define GPLL4 5
15
+
#define GCC_ADSS_PWM_CLK 6
16
+
#define GCC_ADSS_PWM_CLK_SRC 7
17
+
#define GCC_AHB_CLK 8
18
+
#define GCC_APSS_AXI_CLK_SRC 9
19
+
#define GCC_BLSP1_AHB_CLK 10
20
+
#define GCC_BLSP1_QUP1_I2C_APPS_CLK 11
21
+
#define GCC_BLSP1_QUP1_SPI_APPS_CLK 12
22
+
#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 13
23
+
#define GCC_BLSP1_QUP2_I2C_APPS_CLK 14
24
+
#define GCC_BLSP1_QUP2_SPI_APPS_CLK 15
25
+
#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 16
26
+
#define GCC_BLSP1_QUP3_I2C_APPS_CLK 17
27
+
#define GCC_BLSP1_QUP3_SPI_APPS_CLK 18
28
+
#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 19
29
+
#define GCC_BLSP1_SLEEP_CLK 20
30
+
#define GCC_BLSP1_UART1_APPS_CLK 21
31
+
#define GCC_BLSP1_UART1_APPS_CLK_SRC 22
32
+
#define GCC_BLSP1_UART2_APPS_CLK 23
33
+
#define GCC_BLSP1_UART2_APPS_CLK_SRC 24
34
+
#define GCC_BLSP1_UART3_APPS_CLK 25
35
+
#define GCC_BLSP1_UART3_APPS_CLK_SRC 26
36
+
#define GCC_CE_AHB_CLK 27
37
+
#define GCC_CE_AXI_CLK 28
38
+
#define GCC_CE_PCNOC_AHB_CLK 29
39
+
#define GCC_CMN_12GPLL_AHB_CLK 30
40
+
#define GCC_CMN_12GPLL_APU_CLK 31
41
+
#define GCC_CMN_12GPLL_SYS_CLK 32
42
+
#define GCC_GP1_CLK 33
43
+
#define GCC_GP1_CLK_SRC 34
44
+
#define GCC_GP2_CLK 35
45
+
#define GCC_GP2_CLK_SRC 36
46
+
#define GCC_LPASS_CORE_AXIM_CLK 37
47
+
#define GCC_LPASS_SWAY_CLK 38
48
+
#define GCC_LPASS_SWAY_CLK_SRC 39
49
+
#define GCC_MDIO_AHB_CLK 40
50
+
#define GCC_MDIO_SLAVE_AHB_CLK 41
51
+
#define GCC_MEM_NOC_Q6_AXI_CLK 42
52
+
#define GCC_MEM_NOC_TS_CLK 43
53
+
#define GCC_NSS_TS_CLK 44
54
+
#define GCC_NSS_TS_CLK_SRC 45
55
+
#define GCC_NSSCC_CLK 46
56
+
#define GCC_NSSCFG_CLK 47
57
+
#define GCC_NSSNOC_ATB_CLK 48
58
+
#define GCC_NSSNOC_NSSCC_CLK 49
59
+
#define GCC_NSSNOC_QOSGEN_REF_CLK 50
60
+
#define GCC_NSSNOC_SNOC_1_CLK 51
61
+
#define GCC_NSSNOC_SNOC_CLK 52
62
+
#define GCC_NSSNOC_TIMEOUT_REF_CLK 53
63
+
#define GCC_NSSNOC_XO_DCD_CLK 54
64
+
#define GCC_PCIE3X1_0_AHB_CLK 55
65
+
#define GCC_PCIE3X1_0_AUX_CLK 56
66
+
#define GCC_PCIE3X1_0_AXI_CLK_SRC 57
67
+
#define GCC_PCIE3X1_0_AXI_M_CLK 58
68
+
#define GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK 59
69
+
#define GCC_PCIE3X1_0_AXI_S_CLK 60
70
+
#define GCC_PCIE3X1_0_PIPE_CLK 61
71
+
#define GCC_PCIE3X1_0_RCHG_CLK 62
72
+
#define GCC_PCIE3X1_0_RCHG_CLK_SRC 63
73
+
#define GCC_PCIE3X1_1_AHB_CLK 64
74
+
#define GCC_PCIE3X1_1_AUX_CLK 65
75
+
#define GCC_PCIE3X1_1_AXI_CLK_SRC 66
76
+
#define GCC_PCIE3X1_1_AXI_M_CLK 67
77
+
#define GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK 68
78
+
#define GCC_PCIE3X1_1_AXI_S_CLK 69
79
+
#define GCC_PCIE3X1_1_PIPE_CLK 70
80
+
#define GCC_PCIE3X1_1_RCHG_CLK 71
81
+
#define GCC_PCIE3X1_1_RCHG_CLK_SRC 72
82
+
#define GCC_PCIE3X1_PHY_AHB_CLK 73
83
+
#define GCC_PCIE3X2_AHB_CLK 74
84
+
#define GCC_PCIE3X2_AUX_CLK 75
85
+
#define GCC_PCIE3X2_AXI_M_CLK 76
86
+
#define GCC_PCIE3X2_AXI_M_CLK_SRC 77
87
+
#define GCC_PCIE3X2_AXI_S_BRIDGE_CLK 78
88
+
#define GCC_PCIE3X2_AXI_S_CLK 79
89
+
#define GCC_PCIE3X2_AXI_S_CLK_SRC 80
90
+
#define GCC_PCIE3X2_PHY_AHB_CLK 81
91
+
#define GCC_PCIE3X2_PIPE_CLK 82
92
+
#define GCC_PCIE3X2_RCHG_CLK 83
93
+
#define GCC_PCIE3X2_RCHG_CLK_SRC 84
94
+
#define GCC_PCIE_AUX_CLK_SRC 85
95
+
#define GCC_PCNOC_AT_CLK 86
96
+
#define GCC_PCNOC_BFDCD_CLK_SRC 87
97
+
#define GCC_PCNOC_LPASS_CLK 88
98
+
#define GCC_PRNG_AHB_CLK 89
99
+
#define GCC_Q6_AHB_CLK 90
100
+
#define GCC_Q6_AHB_S_CLK 91
101
+
#define GCC_Q6_AXIM_CLK 92
102
+
#define GCC_Q6_AXIM_CLK_SRC 93
103
+
#define GCC_Q6_AXIS_CLK 94
104
+
#define GCC_Q6_TSCTR_1TO2_CLK 95
105
+
#define GCC_Q6SS_ATBM_CLK 96
106
+
#define GCC_Q6SS_PCLKDBG_CLK 97
107
+
#define GCC_Q6SS_TRIG_CLK 98
108
+
#define GCC_QDSS_AT_CLK 99
109
+
#define GCC_QDSS_AT_CLK_SRC 100
110
+
#define GCC_QDSS_CFG_AHB_CLK 101
111
+
#define GCC_QDSS_DAP_AHB_CLK 102
112
+
#define GCC_QDSS_DAP_CLK 103
113
+
#define GCC_QDSS_DAP_DIV_CLK_SRC 104
114
+
#define GCC_QDSS_ETR_USB_CLK 105
115
+
#define GCC_QDSS_EUD_AT_CLK 106
116
+
#define GCC_QDSS_TSCTR_CLK_SRC 107
117
+
#define GCC_QPIC_AHB_CLK 108
118
+
#define GCC_QPIC_CLK 109
119
+
#define GCC_QPIC_IO_MACRO_CLK 110
120
+
#define GCC_QPIC_IO_MACRO_CLK_SRC 111
121
+
#define GCC_QPIC_SLEEP_CLK 112
122
+
#define GCC_SDCC1_AHB_CLK 113
123
+
#define GCC_SDCC1_APPS_CLK 114
124
+
#define GCC_SDCC1_APPS_CLK_SRC 115
125
+
#define GCC_SLEEP_CLK_SRC 116
126
+
#define GCC_SNOC_LPASS_CFG_CLK 117
127
+
#define GCC_SNOC_NSSNOC_1_CLK 118
128
+
#define GCC_SNOC_NSSNOC_CLK 119
129
+
#define GCC_SNOC_PCIE3_1LANE_1_M_CLK 120
130
+
#define GCC_SNOC_PCIE3_1LANE_1_S_CLK 121
131
+
#define GCC_SNOC_PCIE3_1LANE_M_CLK 122
132
+
#define GCC_SNOC_PCIE3_1LANE_S_CLK 123
133
+
#define GCC_SNOC_PCIE3_2LANE_M_CLK 124
134
+
#define GCC_SNOC_PCIE3_2LANE_S_CLK 125
135
+
#define GCC_SNOC_USB_CLK 126
136
+
#define GCC_SYS_NOC_AT_CLK 127
137
+
#define GCC_SYS_NOC_WCSS_AHB_CLK 128
138
+
#define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 129
139
+
#define GCC_UNIPHY0_AHB_CLK 130
140
+
#define GCC_UNIPHY0_SYS_CLK 131
141
+
#define GCC_UNIPHY1_AHB_CLK 132
142
+
#define GCC_UNIPHY1_SYS_CLK 133
143
+
#define GCC_UNIPHY_SYS_CLK_SRC 134
144
+
#define GCC_USB0_AUX_CLK 135
145
+
#define GCC_USB0_AUX_CLK_SRC 136
146
+
#define GCC_USB0_EUD_AT_CLK 137
147
+
#define GCC_USB0_LFPS_CLK 138
148
+
#define GCC_USB0_LFPS_CLK_SRC 139
149
+
#define GCC_USB0_MASTER_CLK 140
150
+
#define GCC_USB0_MASTER_CLK_SRC 141
151
+
#define GCC_USB0_MOCK_UTMI_CLK 142
152
+
#define GCC_USB0_MOCK_UTMI_CLK_SRC 143
153
+
#define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC 144
154
+
#define GCC_USB0_PHY_CFG_AHB_CLK 145
155
+
#define GCC_USB0_PIPE_CLK 146
156
+
#define GCC_USB0_SLEEP_CLK 147
157
+
#define GCC_WCSS_AHB_CLK_SRC 148
158
+
#define GCC_WCSS_AXIM_CLK 149
159
+
#define GCC_WCSS_AXIS_CLK 150
160
+
#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 151
161
+
#define GCC_WCSS_DBG_IFC_APB_CLK 152
162
+
#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 153
163
+
#define GCC_WCSS_DBG_IFC_ATB_CLK 154
164
+
#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 155
165
+
#define GCC_WCSS_DBG_IFC_NTS_CLK 156
166
+
#define GCC_WCSS_ECAHB_CLK 157
167
+
#define GCC_WCSS_MST_ASYNC_BDG_CLK 158
168
+
#define GCC_WCSS_SLV_ASYNC_BDG_CLK 159
169
+
#define GCC_XO_CLK 160
170
+
#define GCC_XO_CLK_SRC 161
171
+
#define GCC_XO_DIV4_CLK 162
172
+
#define GCC_IM_SLEEP_CLK 163
173
+
#define GCC_NSSNOC_PCNOC_1_CLK 164
174
+
#define GCC_MEM_NOC_AHB_CLK 165
175
+
#define GCC_MEM_NOC_APSS_AXI_CLK 166
176
+
#define GCC_SNOC_QOSGEN_EXTREF_DIV_CLK_SRC 167
177
+
#define GCC_MEM_NOC_QOSGEN_EXTREF_CLK 168
178
+
#define GCC_PCIE3X2_PIPE_CLK_SRC 169
179
+
#define GCC_PCIE3X1_0_PIPE_CLK_SRC 170
180
+
#define GCC_PCIE3X1_1_PIPE_CLK_SRC 171
181
+
#define GCC_USB0_PIPE_CLK_SRC 172
182
+
183
+
#define GCC_ADSS_BCR 0
184
+
#define GCC_ADSS_PWM_CLK_ARES 1
185
+
#define GCC_AHB_CLK_ARES 2
186
+
#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 3
187
+
#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES 4
188
+
#define GCC_APSS_AHB_CLK_ARES 5
189
+
#define GCC_APSS_AXI_CLK_ARES 6
190
+
#define GCC_BLSP1_AHB_CLK_ARES 7
191
+
#define GCC_BLSP1_BCR 8
192
+
#define GCC_BLSP1_QUP1_BCR 9
193
+
#define GCC_BLSP1_QUP1_I2C_APPS_CLK_ARES 10
194
+
#define GCC_BLSP1_QUP1_SPI_APPS_CLK_ARES 11
195
+
#define GCC_BLSP1_QUP2_BCR 12
196
+
#define GCC_BLSP1_QUP2_I2C_APPS_CLK_ARES 13
197
+
#define GCC_BLSP1_QUP2_SPI_APPS_CLK_ARES 14
198
+
#define GCC_BLSP1_QUP3_BCR 15
199
+
#define GCC_BLSP1_QUP3_I2C_APPS_CLK_ARES 16
200
+
#define GCC_BLSP1_QUP3_SPI_APPS_CLK_ARES 17
201
+
#define GCC_BLSP1_SLEEP_CLK_ARES 18
202
+
#define GCC_BLSP1_UART1_APPS_CLK_ARES 19
203
+
#define GCC_BLSP1_UART1_BCR 20
204
+
#define GCC_BLSP1_UART2_APPS_CLK_ARES 21
205
+
#define GCC_BLSP1_UART2_BCR 22
206
+
#define GCC_BLSP1_UART3_APPS_CLK_ARES 23
207
+
#define GCC_BLSP1_UART3_BCR 24
208
+
#define GCC_CE_BCR 25
209
+
#define GCC_CMN_BLK_BCR 26
210
+
#define GCC_CMN_LDO0_BCR 27
211
+
#define GCC_CMN_LDO1_BCR 28
212
+
#define GCC_DCC_BCR 29
213
+
#define GCC_GP1_CLK_ARES 30
214
+
#define GCC_GP2_CLK_ARES 31
215
+
#define GCC_LPASS_BCR 32
216
+
#define GCC_LPASS_CORE_AXIM_CLK_ARES 33
217
+
#define GCC_LPASS_SWAY_CLK_ARES 34
218
+
#define GCC_MDIOM_BCR 35
219
+
#define GCC_MDIOS_BCR 36
220
+
#define GCC_NSS_BCR 37
221
+
#define GCC_NSS_TS_CLK_ARES 38
222
+
#define GCC_NSSCC_CLK_ARES 39
223
+
#define GCC_NSSCFG_CLK_ARES 40
224
+
#define GCC_NSSNOC_ATB_CLK_ARES 41
225
+
#define GCC_NSSNOC_NSSCC_CLK_ARES 42
226
+
#define GCC_NSSNOC_QOSGEN_REF_CLK_ARES 43
227
+
#define GCC_NSSNOC_SNOC_1_CLK_ARES 44
228
+
#define GCC_NSSNOC_SNOC_CLK_ARES 45
229
+
#define GCC_NSSNOC_TIMEOUT_REF_CLK_ARES 46
230
+
#define GCC_NSSNOC_XO_DCD_CLK_ARES 47
231
+
#define GCC_PCIE3X1_0_AHB_CLK_ARES 48
232
+
#define GCC_PCIE3X1_0_AUX_CLK_ARES 49
233
+
#define GCC_PCIE3X1_0_AXI_M_CLK_ARES 50
234
+
#define GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK_ARES 51
235
+
#define GCC_PCIE3X1_0_AXI_S_CLK_ARES 52
236
+
#define GCC_PCIE3X1_0_BCR 53
237
+
#define GCC_PCIE3X1_0_LINK_DOWN_BCR 54
238
+
#define GCC_PCIE3X1_0_PHY_BCR 55
239
+
#define GCC_PCIE3X1_0_PHY_PHY_BCR 56
240
+
#define GCC_PCIE3X1_1_AHB_CLK_ARES 57
241
+
#define GCC_PCIE3X1_1_AUX_CLK_ARES 58
242
+
#define GCC_PCIE3X1_1_AXI_M_CLK_ARES 59
243
+
#define GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK_ARES 60
244
+
#define GCC_PCIE3X1_1_AXI_S_CLK_ARES 61
245
+
#define GCC_PCIE3X1_1_BCR 62
246
+
#define GCC_PCIE3X1_1_LINK_DOWN_BCR 63
247
+
#define GCC_PCIE3X1_1_PHY_BCR 64
248
+
#define GCC_PCIE3X1_1_PHY_PHY_BCR 65
249
+
#define GCC_PCIE3X1_PHY_AHB_CLK_ARES 66
250
+
#define GCC_PCIE3X2_AHB_CLK_ARES 67
251
+
#define GCC_PCIE3X2_AUX_CLK_ARES 68
252
+
#define GCC_PCIE3X2_AXI_M_CLK_ARES 69
253
+
#define GCC_PCIE3X2_AXI_S_BRIDGE_CLK_ARES 70
254
+
#define GCC_PCIE3X2_AXI_S_CLK_ARES 71
255
+
#define GCC_PCIE3X2_BCR 72
256
+
#define GCC_PCIE3X2_LINK_DOWN_BCR 73
257
+
#define GCC_PCIE3X2_PHY_AHB_CLK_ARES 74
258
+
#define GCC_PCIE3X2_PHY_BCR 75
259
+
#define GCC_PCIE3X2PHY_PHY_BCR 76
260
+
#define GCC_PCNOC_BCR 77
261
+
#define GCC_PCNOC_LPASS_CLK_ARES 78
262
+
#define GCC_PRNG_AHB_CLK_ARES 79
263
+
#define GCC_PRNG_BCR 80
264
+
#define GCC_Q6_AHB_CLK_ARES 81
265
+
#define GCC_Q6_AHB_S_CLK_ARES 82
266
+
#define GCC_Q6_AXIM_CLK_ARES 83
267
+
#define GCC_Q6_AXIS_CLK_ARES 84
268
+
#define GCC_Q6_TSCTR_1TO2_CLK_ARES 85
269
+
#define GCC_Q6SS_ATBM_CLK_ARES 86
270
+
#define GCC_Q6SS_PCLKDBG_CLK_ARES 87
271
+
#define GCC_Q6SS_TRIG_CLK_ARES 88
272
+
#define GCC_QDSS_APB2JTAG_CLK_ARES 89
273
+
#define GCC_QDSS_AT_CLK_ARES 90
274
+
#define GCC_QDSS_BCR 91
275
+
#define GCC_QDSS_CFG_AHB_CLK_ARES 92
276
+
#define GCC_QDSS_DAP_AHB_CLK_ARES 93
277
+
#define GCC_QDSS_DAP_CLK_ARES 94
278
+
#define GCC_QDSS_ETR_USB_CLK_ARES 95
279
+
#define GCC_QDSS_EUD_AT_CLK_ARES 96
280
+
#define GCC_QDSS_STM_CLK_ARES 97
281
+
#define GCC_QDSS_TRACECLKIN_CLK_ARES 98
282
+
#define GCC_QDSS_TS_CLK_ARES 99
283
+
#define GCC_QDSS_TSCTR_DIV16_CLK_ARES 100
284
+
#define GCC_QDSS_TSCTR_DIV2_CLK_ARES 101
285
+
#define GCC_QDSS_TSCTR_DIV3_CLK_ARES 102
286
+
#define GCC_QDSS_TSCTR_DIV4_CLK_ARES 103
287
+
#define GCC_QDSS_TSCTR_DIV8_CLK_ARES 104
288
+
#define GCC_QPIC_AHB_CLK_ARES 105
289
+
#define GCC_QPIC_CLK_ARES 106
290
+
#define GCC_QPIC_BCR 107
291
+
#define GCC_QPIC_IO_MACRO_CLK_ARES 108
292
+
#define GCC_QPIC_SLEEP_CLK_ARES 109
293
+
#define GCC_QUSB2_0_PHY_BCR 110
294
+
#define GCC_SDCC1_AHB_CLK_ARES 111
295
+
#define GCC_SDCC1_APPS_CLK_ARES 112
296
+
#define GCC_SDCC_BCR 113
297
+
#define GCC_SNOC_BCR 114
298
+
#define GCC_SNOC_LPASS_CFG_CLK_ARES 115
299
+
#define GCC_SNOC_NSSNOC_1_CLK_ARES 116
300
+
#define GCC_SNOC_NSSNOC_CLK_ARES 117
301
+
#define GCC_SYS_NOC_QDSS_STM_AXI_CLK_ARES 118
302
+
#define GCC_SYS_NOC_WCSS_AHB_CLK_ARES 119
303
+
#define GCC_UNIPHY0_AHB_CLK_ARES 120
304
+
#define GCC_UNIPHY0_BCR 121
305
+
#define GCC_UNIPHY0_SYS_CLK_ARES 122
306
+
#define GCC_UNIPHY1_AHB_CLK_ARES 123
307
+
#define GCC_UNIPHY1_BCR 124
308
+
#define GCC_UNIPHY1_SYS_CLK_ARES 125
309
+
#define GCC_USB0_AUX_CLK_ARES 126
310
+
#define GCC_USB0_EUD_AT_CLK_ARES 127
311
+
#define GCC_USB0_LFPS_CLK_ARES 128
312
+
#define GCC_USB0_MASTER_CLK_ARES 129
313
+
#define GCC_USB0_MOCK_UTMI_CLK_ARES 130
314
+
#define GCC_USB0_PHY_BCR 131
315
+
#define GCC_USB0_PHY_CFG_AHB_CLK_ARES 132
316
+
#define GCC_USB0_SLEEP_CLK_ARES 133
317
+
#define GCC_USB3PHY_0_PHY_BCR 134
318
+
#define GCC_USB_BCR 135
319
+
#define GCC_WCSS_AXIM_CLK_ARES 136
320
+
#define GCC_WCSS_AXIS_CLK_ARES 137
321
+
#define GCC_WCSS_BCR 138
322
+
#define GCC_WCSS_DBG_IFC_APB_BDG_CLK_ARES 139
323
+
#define GCC_WCSS_DBG_IFC_APB_CLK_ARES 140
324
+
#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK_ARES 141
325
+
#define GCC_WCSS_DBG_IFC_ATB_CLK_ARES 142
326
+
#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK_ARES 143
327
+
#define GCC_WCSS_DBG_IFC_NTS_CLK_ARES 144
328
+
#define GCC_WCSS_ECAHB_CLK_ARES 145
329
+
#define GCC_WCSS_MST_ASYNC_BDG_CLK_ARES 146
330
+
#define GCC_WCSS_Q6_BCR 147
331
+
#define GCC_WCSS_SLV_ASYNC_BDG_CLK_ARES 148
332
+
#define GCC_XO_CLK_ARES 149
333
+
#define GCC_XO_DIV4_CLK_ARES 150
334
+
#define GCC_Q6SS_DBG_ARES 151
335
+
#define GCC_WCSS_DBG_BDG_ARES 152
336
+
#define GCC_WCSS_DBG_ARES 153
337
+
#define GCC_WCSS_AXI_S_ARES 154
338
+
#define GCC_WCSS_AXI_M_ARES 155
339
+
#define GCC_WCSSAON_ARES 156
340
+
#define GCC_PCIE3X2_PIPE_ARES 157
341
+
#define GCC_PCIE3X2_CORE_STICKY_ARES 158
342
+
#define GCC_PCIE3X2_AXI_S_STICKY_ARES 159
343
+
#define GCC_PCIE3X2_AXI_M_STICKY_ARES 160
344
+
#define GCC_PCIE3X1_0_PIPE_ARES 161
345
+
#define GCC_PCIE3X1_0_CORE_STICKY_ARES 162
346
+
#define GCC_PCIE3X1_0_AXI_S_STICKY_ARES 163
347
+
#define GCC_PCIE3X1_0_AXI_M_STICKY_ARES 164
348
+
#define GCC_PCIE3X1_1_PIPE_ARES 165
349
+
#define GCC_PCIE3X1_1_CORE_STICKY_ARES 166
350
+
#define GCC_PCIE3X1_1_AXI_S_STICKY_ARES 167
351
+
#define GCC_PCIE3X1_1_AXI_M_STICKY_ARES 168
352
+
#define GCC_IM_SLEEP_CLK_ARES 169
353
+
#define GCC_NSSNOC_PCNOC_1_CLK_ARES 170
354
+
#define GCC_UNIPHY0_XPCS_ARES 171
355
+
#define GCC_UNIPHY1_XPCS_ARES 172
356
+
#endif
+36
include/dt-bindings/clock/qcom,sm6115-gpucc.h
+36
include/dt-bindings/clock/qcom,sm6115-gpucc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
4
+
* Copyright (c) 2023, Linaro Limited
5
+
*/
6
+
7
+
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6115_H
8
+
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6115_H
9
+
10
+
/* GPU_CC clocks */
11
+
#define GPU_CC_PLL0 0
12
+
#define GPU_CC_PLL0_OUT_AUX2 1
13
+
#define GPU_CC_PLL1 2
14
+
#define GPU_CC_PLL1_OUT_AUX 3
15
+
#define GPU_CC_AHB_CLK 4
16
+
#define GPU_CC_CRC_AHB_CLK 5
17
+
#define GPU_CC_CX_GFX3D_CLK 6
18
+
#define GPU_CC_CX_GMU_CLK 7
19
+
#define GPU_CC_CX_SNOC_DVM_CLK 8
20
+
#define GPU_CC_CXO_AON_CLK 9
21
+
#define GPU_CC_CXO_CLK 10
22
+
#define GPU_CC_GMU_CLK_SRC 11
23
+
#define GPU_CC_GX_CXO_CLK 12
24
+
#define GPU_CC_GX_GFX3D_CLK 13
25
+
#define GPU_CC_GX_GFX3D_CLK_SRC 14
26
+
#define GPU_CC_SLEEP_CLK 15
27
+
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16
28
+
29
+
/* Resets */
30
+
#define GPU_GX_BCR 0
31
+
32
+
/* GDSCs */
33
+
#define GPU_CX_GDSC 0
34
+
#define GPU_GX_GDSC 1
35
+
36
+
#endif
+31
include/dt-bindings/clock/qcom,sm6125-gpucc.h
+31
include/dt-bindings/clock/qcom,sm6125-gpucc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
4
+
* Copyright (c) 2023, Linaro Limited
5
+
*/
6
+
7
+
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6125_H
8
+
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6125_H
9
+
10
+
/* Clocks */
11
+
#define GPU_CC_PLL0_OUT_AUX2 0
12
+
#define GPU_CC_PLL1_OUT_AUX2 1
13
+
#define GPU_CC_CRC_AHB_CLK 2
14
+
#define GPU_CC_CX_APB_CLK 3
15
+
#define GPU_CC_CX_GFX3D_CLK 4
16
+
#define GPU_CC_CX_GMU_CLK 5
17
+
#define GPU_CC_CX_SNOC_DVM_CLK 6
18
+
#define GPU_CC_CXO_AON_CLK 7
19
+
#define GPU_CC_CXO_CLK 8
20
+
#define GPU_CC_GMU_CLK_SRC 9
21
+
#define GPU_CC_SLEEP_CLK 10
22
+
#define GPU_CC_GX_GFX3D_CLK 11
23
+
#define GPU_CC_GX_GFX3D_CLK_SRC 12
24
+
#define GPU_CC_AHB_CLK 13
25
+
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14
26
+
27
+
/* GDSCs */
28
+
#define GPU_CX_GDSC 0
29
+
#define GPU_GX_GDSC 1
30
+
31
+
#endif
+36
include/dt-bindings/clock/qcom,sm6375-gpucc.h
+36
include/dt-bindings/clock/qcom,sm6375-gpucc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
4
+
* Copyright (c) 2023, Linaro Limited
5
+
*/
6
+
7
+
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_BLAIR_H
8
+
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_BLAIR_H
9
+
10
+
/* GPU CC clocks */
11
+
#define GPU_CC_PLL0 0
12
+
#define GPU_CC_PLL1 1
13
+
#define GPU_CC_AHB_CLK 2
14
+
#define GPU_CC_CX_GFX3D_CLK 3
15
+
#define GPU_CC_CX_GFX3D_SLV_CLK 4
16
+
#define GPU_CC_CX_GMU_CLK 5
17
+
#define GPU_CC_CX_SNOC_DVM_CLK 6
18
+
#define GPU_CC_CXO_AON_CLK 7
19
+
#define GPU_CC_CXO_CLK 8
20
+
#define GPU_CC_GMU_CLK_SRC 9
21
+
#define GPU_CC_GX_CXO_CLK 10
22
+
#define GPU_CC_GX_GFX3D_CLK 11
23
+
#define GPU_CC_GX_GFX3D_CLK_SRC 12
24
+
#define GPU_CC_GX_GMU_CLK 13
25
+
#define GPU_CC_SLEEP_CLK 14
26
+
27
+
/* GDSCs */
28
+
#define GPU_CX_GDSC 0
29
+
#define GPU_GX_GDSC 1
30
+
31
+
/* Resets */
32
+
#define GPU_GX_BCR 0
33
+
#define GPU_ACD_BCR 1
34
+
#define GPU_GX_ACD_MISC_BCR 2
35
+
36
+
#endif