tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'qcom-dts-for-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt

Qualcomm ARM32 DeviceTree updates for v6.4

stdout-path is defined for the ALFA Network AP120C-AC, to avoid the need
to pass this information on the kernel commandline. Ath10k is wired up
to read calibration data from the "ART" partition.

PCI I/O port ranges are fixed on IPQ4019 and IPQ8064.

Supply clocks are defined for KPSS L2CC and ACC clock controllers.

Supply clocks for the global clock controller are being specified on
IPQ4019, MSM8974 and MSM8226.

PCIe RC support is enabled on the SDX55 T55 development board, IPA is
defined for the SDX55 and a number of cleanup patches are introduced.

Compatibles for QRB2210/QCM2290, IPQ9574, QRD8550 and IPQ5332 platforms
are added, and the RB1, Yiming LTE dongle, Xiaomi Mi A3, MI01.2 and
MI01.6 boards.

* tag 'qcom-dts-for-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (28 commits)
dt-bindings: arm: qcom: Add Yiming LTE dongle uz801-v3.0 (yiming-uz801v3)
dt-bindings: vendor-prefixes: Add Henan Yiming Technology Co., Ltd.
ARM: dts: qcom: sdx55: add dedicated SDX55 TCSR compatible
ARM: dts: qcom: sdx55-t55: Move "status" property down
ARM: dts: qcom: sdx55-t55: Enable PCIe RC support
ARM: dts: qcom: sdx55: List the property values vertically
ARM: dts: qcom: sdx55: Add support for PCIe RC controller
ARM: dts: qcom: sdx55: Rename pcie0_{phy/lane} to pcie_{phy/lane}
ARM: dts: qcom: sdx55: Fix the unit address of PCIe EP node
ARM: dts: qcom: ipq8064: Fix the PCI I/O port range
ARM: dts: qcom: ipq4019: Fix the PCI I/O port range
ARM: dts: qcom: apq8064: Use 0x prefix for the PCI I/O and MEM ranges
dt-bindings: arm: qcom: Add ipq9574 compatible
ARM: dts: qcom: msm8974: add correct XO clock source to GCC node
ARM: dts: qcom: msm8226: add clocks and clock-names to GCC node
ARM: dts: qcom: rename kpss-acc-v2 nodes to power-manager nodes
ARM: dts: qcom: add missing clock configuration for kpss-acc-v1
ARM: dts: qcom: add and fix clock configuration for kpss-gcc nodes
ARM: dts: qcom: add per SoC compatible for qcom,kpss-gcc nodes
dt-bindings: qcom: add ipq5332 boards
...

Link: https://lore.kernel.org/r/20230410155226.5127-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Arnd Bergmann a8127d2a c47b89b4

+304 -80
+16
Documentation/devicetree/bindings/arm/qcom.yaml
··· 30 30 apq8084 31 31 apq8096 32 32 ipq4018 33 + ipq5332 33 34 ipq6018 34 35 ipq8074 36 + ipq9574 35 37 mdm9615 36 38 msm8226 37 39 msm8916 ··· 82 80 The 'board' element must be one of the following strings: 83 81 84 82 adp 83 + ap-al02-c7 84 + ap-mi01.2 85 85 cdp 86 86 cp01-c1 87 87 dragonboard ··· 230 226 - thwc,uf896 231 227 - thwc,ufi001c 232 228 - wingtech,wt88047 229 + - yiming,uz801-v3 233 230 - const: qcom,msm8916 234 231 235 232 - items: ··· 327 322 328 323 - items: 329 324 - enum: 325 + - qcom,ipq5332-ap-mi01.2 326 + - const: qcom,ipq5332 327 + 328 + - items: 329 + - enum: 330 330 - mikrotik,rb3011 331 331 - qcom,ipq8064-ap148 332 332 - const: qcom,ipq8064 ··· 342 332 - qcom,ipq8074-hk10-c1 343 333 - qcom,ipq8074-hk10-c2 344 334 - const: qcom,ipq8074 335 + 336 + - items: 337 + - enum: 338 + - qcom,ipq9574-ap-al02-c7 339 + - const: qcom,ipq9574 345 340 346 341 - description: Sierra Wireless MangOH Green with WP8548 Module 347 342 items: ··· 928 913 - items: 929 914 - enum: 930 915 - qcom,sm8550-mtp 916 + - qcom,sm8550-qrd 931 917 - const: qcom,sm8550 932 918 933 919 # Board compatibles go above
+2
Documentation/devicetree/bindings/vendor-prefixes.yaml
··· 1538 1538 description: Yes Optoelectronics Co.,Ltd. 1539 1539 "^yic,.*": 1540 1540 description: YIC System Co., Ltd. 1541 + "^yiming,.*": 1542 + description: Henan Yiming Technology Co., Ltd. 1541 1543 "^ylm,.*": 1542 1544 description: Shenzhen Yangliming Electronic Technology Co., Ltd. 1543 1545 "^yna,.*":
+23 -4
arch/arm/boot/dts/qcom-apq8064.dtsi
··· 388 388 acc0: clock-controller@2088000 { 389 389 compatible = "qcom,kpss-acc-v1"; 390 390 reg = <0x02088000 0x1000>, <0x02008000 0x1000>; 391 + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 392 + clock-names = "pll8_vote", "pxo"; 393 + clock-output-names = "acpu0_aux"; 394 + #clock-cells = <0>; 391 395 }; 392 396 393 397 acc1: clock-controller@2098000 { 394 398 compatible = "qcom,kpss-acc-v1"; 395 399 reg = <0x02098000 0x1000>, <0x02008000 0x1000>; 400 + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 401 + clock-names = "pll8_vote", "pxo"; 402 + clock-output-names = "acpu1_aux"; 403 + #clock-cells = <0>; 396 404 }; 397 405 398 406 acc2: clock-controller@20a8000 { 399 407 compatible = "qcom,kpss-acc-v1"; 400 408 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; 409 + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 410 + clock-names = "pll8_vote", "pxo"; 411 + clock-output-names = "acpu2_aux"; 412 + #clock-cells = <0>; 401 413 }; 402 414 403 415 acc3: clock-controller@20b8000 { 404 416 compatible = "qcom,kpss-acc-v1"; 405 417 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; 418 + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 419 + clock-names = "pll8_vote", "pxo"; 420 + clock-output-names = "acpu3_aux"; 421 + #clock-cells = <0>; 406 422 }; 407 423 408 424 saw0: power-controller@2089000 { ··· 895 879 }; 896 880 897 881 l2cc: clock-controller@2011000 { 898 - compatible = "qcom,kpss-gcc", "syscon"; 882 + compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon"; 899 883 reg = <0x2011000 0x1000>; 884 + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 885 + clock-names = "pll8_vote", "pxo"; 886 + #clock-cells = <0>; 900 887 }; 901 888 902 889 rpm: rpm@108000 { ··· 1279 1260 gpu_opp_table: opp-table { 1280 1261 compatible = "operating-points-v2"; 1281 1262 1282 - opp-320000000 { 1263 + opp-450000000 { 1283 1264 opp-hz = /bits/ 64 <450000000>; 1284 1265 }; 1285 1266 ··· 1513 1494 num-lanes = <1>; 1514 1495 #address-cells = <3>; 1515 1496 #size-cells = <2>; 1516 - ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>, /* I/O */ 1517 - <0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* mem */ 1497 + ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00100000>, /* I/O */ 1498 + <0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* mem */ 1518 1499 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1519 1500 interrupt-names = "msi"; 1520 1501 #interrupt-cells = <1>;
+4 -4
arch/arm/boot/dts/qcom-apq8084.dtsi
··· 654 654 regulator; 655 655 }; 656 656 657 - acc0: clock-controller@f9088000 { 657 + acc0: power-manager@f9088000 { 658 658 compatible = "qcom,kpss-acc-v2"; 659 659 reg = <0xf9088000 0x1000>, 660 660 <0xf9008000 0x1000>; 661 661 }; 662 662 663 - acc1: clock-controller@f9098000 { 663 + acc1: power-manager@f9098000 { 664 664 compatible = "qcom,kpss-acc-v2"; 665 665 reg = <0xf9098000 0x1000>, 666 666 <0xf9008000 0x1000>; 667 667 }; 668 668 669 - acc2: clock-controller@f90a8000 { 669 + acc2: power-manager@f90a8000 { 670 670 compatible = "qcom,kpss-acc-v2"; 671 671 reg = <0xf90a8000 0x1000>, 672 672 <0xf9008000 0x1000>; 673 673 }; 674 674 675 - acc3: clock-controller@f90b8000 { 675 + acc3: power-manager@f90b8000 { 676 676 compatible = "qcom,kpss-acc-v2"; 677 677 reg = <0xf90b8000 0x1000>, 678 678 <0xf9008000 0x1000>;
+25 -2
arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi
··· 8 8 model = "ALFA Network AP120C-AC"; 9 9 compatible = "alfa-network,ap120c-ac", "qcom,ipq4018"; 10 10 11 + aliases { 12 + serial0 = &blsp1_uart1; 13 + }; 14 + 15 + chosen { 16 + stdout-path = "serial0:115200n8"; 17 + }; 18 + 11 19 keys { 12 20 compatible = "gpio-keys"; 13 21 ··· 76 68 }; 77 69 }; 78 70 79 - usb-power { 71 + usb-power-hog { 80 72 line-name = "USB-power"; 81 73 gpios = <1 GPIO_ACTIVE_HIGH>; 82 74 gpio-hog; ··· 170 162 label = "ART"; 171 163 reg = <0x00170000 0x00010000>; 172 164 read-only; 165 + compatible = "nvmem-cells"; 166 + #address-cells = <1>; 167 + #size-cells = <1>; 168 + 169 + precal_art_1000: precal@1000 { 170 + reg = <0x1000 0x2f20>; 171 + }; 172 + 173 + precal_art_5000: precal@5000 { 174 + reg = <0x5000 0x2f20>; 175 + }; 173 176 }; 174 177 175 178 partition@180000 { ··· 197 178 }; 198 179 }; 199 180 200 - nand@1 { 181 + flash@1 { 201 182 compatible = "spi-nand"; 202 183 reg = <1>; 203 184 spi-max-frequency = <40000000>; ··· 244 225 245 226 &wifi0 { 246 227 status = "okay"; 228 + nvmem-cell-names = "pre-calibration"; 229 + nvmem-cells = <&precal_art_1000>; 247 230 }; 248 231 249 232 &wifi1 { 250 233 status = "okay"; 234 + nvmem-cell-names = "pre-calibration"; 235 + nvmem-cells = <&precal_art_5000>; 251 236 qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC"; 252 237 }; 253 238
+8 -7
arch/arm/boot/dts/qcom-ipq4019.dtsi
··· 143 143 sleep_clk: sleep_clk { 144 144 compatible = "fixed-clock"; 145 145 clock-frequency = <32000>; 146 - clock-output-names = "gcc_sleep_clk_src"; 147 146 #clock-cells = <0>; 148 147 }; 149 148 ··· 189 190 #power-domain-cells = <1>; 190 191 #reset-cells = <1>; 191 192 reg = <0x1800000 0x60000>; 193 + clocks = <&xo>, <&sleep_clk>; 194 + clock-names = "xo", "sleep_clk"; 192 195 }; 193 196 194 197 prng: rng@22000 { ··· 326 325 status = "disabled"; 327 326 }; 328 327 329 - acc0: clock-controller@b088000 { 328 + acc0: power-manager@b088000 { 330 329 compatible = "qcom,kpss-acc-v2"; 331 330 reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; 332 331 }; 333 332 334 - acc1: clock-controller@b098000 { 333 + acc1: power-manager@b098000 { 335 334 compatible = "qcom,kpss-acc-v2"; 336 335 reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; 337 336 }; 338 337 339 - acc2: clock-controller@b0a8000 { 338 + acc2: power-manager@b0a8000 { 340 339 compatible = "qcom,kpss-acc-v2"; 341 340 reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; 342 341 }; 343 342 344 - acc3: clock-controller@b0b8000 { 343 + acc3: power-manager@b0b8000 { 345 344 compatible = "qcom,kpss-acc-v2"; 346 345 reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; 347 346 }; ··· 427 426 #address-cells = <3>; 428 427 #size-cells = <2>; 429 428 430 - ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>, 431 - <0x82000000 0 0x40300000 0x40300000 0 0x00d00000>; 429 + ranges = <0x81000000 0x0 0x00000000 0x40200000 0x0 0x00100000>, 430 + <0x82000000 0x0 0x40300000 0x40300000 0x0 0x00d00000>; 432 431 433 432 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 434 433 interrupt-names = "msi";
+16 -8
arch/arm/boot/dts/qcom-ipq8064.dtsi
··· 569 569 }; 570 570 571 571 l2cc: clock-controller@2011000 { 572 - compatible = "qcom,kpss-gcc", "syscon"; 572 + compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon"; 573 573 reg = <0x02011000 0x1000>; 574 574 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 575 575 clock-names = "pll8_vote", "pxo"; 576 - clock-output-names = "acpu_l2_aux"; 576 + #clock-cells = <0>; 577 577 }; 578 578 579 579 acc0: clock-controller@2088000 { 580 580 compatible = "qcom,kpss-acc-v1"; 581 581 reg = <0x02088000 0x1000>, <0x02008000 0x1000>; 582 + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 583 + clock-names = "pll8_vote", "pxo"; 584 + clock-output-names = "acpu0_aux"; 585 + #clock-cells = <0>; 582 586 }; 583 587 584 588 saw0: regulator@2089000 { ··· 594 590 acc1: clock-controller@2098000 { 595 591 compatible = "qcom,kpss-acc-v1"; 596 592 reg = <0x02098000 0x1000>, <0x02008000 0x1000>; 593 + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 594 + clock-names = "pll8_vote", "pxo"; 595 + clock-output-names = "acpu1_aux"; 596 + #clock-cells = <0>; 597 597 }; 598 598 599 599 saw1: regulator@2099000 { ··· 1089 1081 #address-cells = <3>; 1090 1082 #size-cells = <2>; 1091 1083 1092 - ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00010000 /* downstream I/O */ 1093 - 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */ 1084 + ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00010000 /* I/O */ 1085 + 0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* MEM */ 1094 1086 1095 1087 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1096 1088 interrupt-names = "msi"; ··· 1140 1132 #address-cells = <3>; 1141 1133 #size-cells = <2>; 1142 1134 1143 - ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00010000 /* downstream I/O */ 1144 - 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */ 1135 + ranges = <0x81000000 0x0 0x00000000 0x31e00000 0x0 0x00010000 /* I/O */ 1136 + 0x82000000 0x0 0x2e000000 0x2e000000 0x0 0x03e00000>; /* MEM */ 1145 1137 1146 1138 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1147 1139 interrupt-names = "msi"; ··· 1191 1183 #address-cells = <3>; 1192 1184 #size-cells = <2>; 1193 1185 1194 - ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00010000 /* downstream I/O */ 1195 - 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */ 1186 + ranges = <0x81000000 0x0 0x00000000 0x35e00000 0x0 0x00010000 /* I/O */ 1187 + 0x82000000 0x0 0x32000000 0x32000000 0x0 0x03e00000>; /* MEM */ 1196 1188 1197 1189 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1198 1190 interrupt-names = "msi";
+1 -1
arch/arm/boot/dts/qcom-mdm9615.dtsi
··· 116 116 }; 117 117 118 118 l2cc: clock-controller@2011000 { 119 - compatible = "qcom,kpss-gcc", "syscon"; 119 + compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon"; 120 120 reg = <0x02011000 0x1000>; 121 121 }; 122 122
+6
arch/arm/boot/dts/qcom-msm8226.dtsi
··· 8 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 9 #include <dt-bindings/clock/qcom,gcc-msm8974.h> 10 10 #include <dt-bindings/clock/qcom,mmcc-msm8974.h> 11 + #include <dt-bindings/clock/qcom,rpmcc.h> 11 12 #include <dt-bindings/gpio/gpio.h> 12 13 #include <dt-bindings/power/qcom-rpmpd.h> 13 14 #include <dt-bindings/reset/qcom,gcc-msm8974.h> ··· 378 377 #clock-cells = <1>; 379 378 #reset-cells = <1>; 380 379 #power-domain-cells = <1>; 380 + 381 + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 382 + <&sleep_clk>; 383 + clock-names = "xo", 384 + "sleep_clk"; 381 385 }; 382 386 383 387 mmcc: clock-controller@fd8c0000 {
+1 -1
arch/arm/boot/dts/qcom-msm8660.dtsi
··· 473 473 }; 474 474 475 475 l2cc: clock-controller@2082000 { 476 - compatible = "qcom,kpss-gcc", "syscon"; 476 + compatible = "qcom,kpss-gcc-msm8660", "qcom,kpss-gcc", "syscon"; 477 477 reg = <0x02082000 0x1000>; 478 478 }; 479 479
+12 -1
arch/arm/boot/dts/qcom-msm8960.dtsi
··· 182 182 }; 183 183 184 184 l2cc: clock-controller@2011000 { 185 - compatible = "qcom,kpss-gcc", "syscon"; 185 + compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon"; 186 186 reg = <0x2011000 0x1000>; 187 + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 188 + clock-names = "pll8_vote", "pxo"; 189 + #clock-cells = <0>; 187 190 }; 188 191 189 192 rpm: rpm@108000 { ··· 207 204 acc0: clock-controller@2088000 { 208 205 compatible = "qcom,kpss-acc-v1"; 209 206 reg = <0x02088000 0x1000>, <0x02008000 0x1000>; 207 + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 208 + clock-names = "pll8_vote", "pxo"; 209 + clock-output-names = "acpu0_aux"; 210 + #clock-cells = <0>; 210 211 }; 211 212 212 213 acc1: clock-controller@2098000 { 213 214 compatible = "qcom,kpss-acc-v1"; 214 215 reg = <0x02098000 0x1000>, <0x02008000 0x1000>; 216 + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 217 + clock-names = "pll8_vote", "pxo"; 218 + clock-output-names = "acpu1_aux"; 219 + #clock-cells = <0>; 215 220 }; 216 221 217 222 saw0: regulator@2089000 {
+5 -5
arch/arm/boot/dts/qcom-msm8974.dtsi
··· 418 418 regulator; 419 419 }; 420 420 421 - acc0: clock-controller@f9088000 { 421 + acc0: power-manager@f9088000 { 422 422 compatible = "qcom,kpss-acc-v2"; 423 423 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; 424 424 }; 425 425 426 - acc1: clock-controller@f9098000 { 426 + acc1: power-manager@f9098000 { 427 427 compatible = "qcom,kpss-acc-v2"; 428 428 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; 429 429 }; 430 430 431 - acc2: clock-controller@f90a8000 { 431 + acc2: power-manager@f90a8000 { 432 432 compatible = "qcom,kpss-acc-v2"; 433 433 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; 434 434 }; 435 435 436 - acc3: clock-controller@f90b8000 { 436 + acc3: power-manager@f90b8000 { 437 437 compatible = "qcom,kpss-acc-v2"; 438 438 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; 439 439 }; ··· 1057 1057 #power-domain-cells = <1>; 1058 1058 reg = <0xfc400000 0x4000>; 1059 1059 1060 - clocks = <&xo_board>, 1060 + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1061 1061 <&sleep_clk>; 1062 1062 clock-names = "xo", 1063 1063 "sleep_clk";
+47 -3
arch/arm/boot/dts/qcom-sdx55-t55.dts
··· 242 242 status = "okay"; 243 243 }; 244 244 245 + &pcie_phy { 246 + vdda-phy-supply = <&vreg_l1e_bb_1p2>; 247 + vdda-pll-supply = <&vreg_l4e_bb_0p875>; 248 + 249 + status = "okay"; 250 + }; 251 + 252 + &pcie_rc { 253 + perst-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; 254 + wake-gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>; 255 + 256 + pinctrl-0 = <&pcie_default>; 257 + pinctrl-names = "default"; 258 + 259 + status = "okay"; 260 + }; 261 + 245 262 &qpic_bam { 246 263 status = "okay"; 247 264 }; ··· 278 261 }; 279 262 280 263 &remoteproc_mpss { 281 - status = "okay"; 282 264 memory-region = <&mpss_adsp_mem>; 265 + status = "okay"; 266 + }; 267 + 268 + &tlmm { 269 + pcie_default: pcie-default-state { 270 + clkreq-pins { 271 + pins = "gpio56"; 272 + function = "pcie_clkreq"; 273 + drive-strength = <2>; 274 + bias-pull-up; 275 + }; 276 + 277 + perst-pins { 278 + pins = "gpio57"; 279 + function = "gpio"; 280 + drive-strength = <2>; 281 + bias-pull-down; 282 + }; 283 + 284 + wake-pins { 285 + pins = "gpio53"; 286 + function = "gpio"; 287 + drive-strength = <2>; 288 + bias-pull-up; 289 + }; 290 + }; 283 291 }; 284 292 285 293 &usb_hsphy { 286 - status = "okay"; 287 294 vdda-pll-supply = <&vreg_l4e_bb_0p875>; 288 295 vdda33-supply = <&vreg_l10e_3p1>; 289 296 vdda18-supply = <&vreg_l5e_bb_1p7>; 297 + 298 + status = "okay"; 290 299 }; 291 300 292 301 &usb_qmpphy { 293 - status = "okay"; 294 302 vdda-phy-supply = <&vreg_l4e_bb_0p875>; 295 303 vdda-pll-supply = <&vreg_l1e_bb_1p2>; 304 + 305 + status = "okay"; 296 306 }; 297 307 298 308 &usb {
+1 -1
arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts
··· 242 242 status = "okay"; 243 243 }; 244 244 245 - &pcie0_phy { 245 + &pcie_phy { 246 246 status = "okay"; 247 247 248 248 vdda-phy-supply = <&vreg_l1e_bb_1p2>;
+137 -43
arch/arm/boot/dts/qcom-sdx55.dtsi
··· 304 304 status = "disabled"; 305 305 }; 306 306 307 - pcie0_phy: phy@1c07000 { 307 + pcie_rc: pcie@1c00000 { 308 + compatible = "qcom,pcie-sdx55"; 309 + reg = <0x01c00000 0x3000>, 310 + <0x40000000 0xf1d>, 311 + <0x40000f20 0xc8>, 312 + <0x40001000 0x1000>, 313 + <0x40100000 0x100000>; 314 + reg-names = "parf", 315 + "dbi", 316 + "elbi", 317 + "atu", 318 + "config"; 319 + device_type = "pci"; 320 + linux,pci-domain = <0>; 321 + bus-range = <0x00 0xff>; 322 + num-lanes = <1>; 323 + 324 + #address-cells = <3>; 325 + #size-cells = <2>; 326 + 327 + ranges = <0x01000000 0x0 0x00000000 0x40200000 0x0 0x100000>, 328 + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>; 329 + 330 + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 331 + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 332 + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 333 + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 334 + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 335 + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 336 + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 337 + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 338 + interrupt-names = "msi", 339 + "msi2", 340 + "msi3", 341 + "msi4", 342 + "msi5", 343 + "msi6", 344 + "msi7", 345 + "msi8"; 346 + #interrupt-cells = <1>; 347 + interrupt-map-mask = <0 0 0 0x7>; 348 + interrupt-map = <0 0 0 1 &intc 0 0 0 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 349 + <0 0 0 2 &intc 0 0 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 350 + <0 0 0 3 &intc 0 0 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 351 + <0 0 0 4 &intc 0 0 0 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 352 + 353 + clocks = <&gcc GCC_PCIE_PIPE_CLK>, 354 + <&gcc GCC_PCIE_AUX_CLK>, 355 + <&gcc GCC_PCIE_CFG_AHB_CLK>, 356 + <&gcc GCC_PCIE_MSTR_AXI_CLK>, 357 + <&gcc GCC_PCIE_SLV_AXI_CLK>, 358 + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, 359 + <&gcc GCC_PCIE_SLEEP_CLK>; 360 + clock-names = "pipe", 361 + "aux", 362 + "cfg", 363 + "bus_master", 364 + "bus_slave", 365 + "slave_q2a", 366 + "sleep"; 367 + 368 + assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>; 369 + assigned-clock-rates = <19200000>; 370 + 371 + iommu-map = <0x0 &apps_smmu 0x0200 0x1>, 372 + <0x100 &apps_smmu 0x0201 0x1>, 373 + <0x200 &apps_smmu 0x0202 0x1>, 374 + <0x300 &apps_smmu 0x0203 0x1>, 375 + <0x400 &apps_smmu 0x0204 0x1>; 376 + 377 + resets = <&gcc GCC_PCIE_BCR>; 378 + reset-names = "pci"; 379 + 380 + power-domains = <&gcc PCIE_GDSC>; 381 + 382 + phys = <&pcie_lane>; 383 + phy-names = "pciephy"; 384 + 385 + status = "disabled"; 386 + }; 387 + 388 + pcie_ep: pcie-ep@1c00000 { 389 + compatible = "qcom,sdx55-pcie-ep"; 390 + reg = <0x01c00000 0x3000>, 391 + <0x40000000 0xf1d>, 392 + <0x40000f20 0xc8>, 393 + <0x40001000 0x1000>, 394 + <0x40200000 0x100000>, 395 + <0x01c03000 0x3000>; 396 + reg-names = "parf", 397 + "dbi", 398 + "elbi", 399 + "atu", 400 + "addr_space", 401 + "mmio"; 402 + 403 + qcom,perst-regs = <&tcsr 0xb258 0xb270>; 404 + 405 + clocks = <&gcc GCC_PCIE_AUX_CLK>, 406 + <&gcc GCC_PCIE_CFG_AHB_CLK>, 407 + <&gcc GCC_PCIE_MSTR_AXI_CLK>, 408 + <&gcc GCC_PCIE_SLV_AXI_CLK>, 409 + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, 410 + <&gcc GCC_PCIE_SLEEP_CLK>, 411 + <&gcc GCC_PCIE_0_CLKREF_CLK>; 412 + clock-names = "aux", 413 + "cfg", 414 + "bus_master", 415 + "bus_slave", 416 + "slave_q2a", 417 + "sleep", 418 + "ref"; 419 + 420 + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 421 + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 422 + interrupt-names = "global", 423 + "doorbell"; 424 + reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; 425 + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; 426 + resets = <&gcc GCC_PCIE_BCR>; 427 + reset-names = "core"; 428 + power-domains = <&gcc PCIE_GDSC>; 429 + phys = <&pcie_lane>; 430 + phy-names = "pciephy"; 431 + max-link-speed = <3>; 432 + num-lanes = <2>; 433 + 434 + status = "disabled"; 435 + }; 436 + 437 + pcie_phy: phy@1c07000 { 308 438 compatible = "qcom,sdx55-qmp-pcie-phy"; 309 439 reg = <0x01c07000 0x1c4>; 310 440 #address-cells = <1>; ··· 444 314 <&gcc GCC_PCIE_CFG_AHB_CLK>, 445 315 <&gcc GCC_PCIE_0_CLKREF_CLK>, 446 316 <&gcc GCC_PCIE_RCHNG_PHY_CLK>; 447 - clock-names = "aux", "cfg_ahb", "ref", "refgen"; 317 + clock-names = "aux", 318 + "cfg_ahb", 319 + "ref", 320 + "refgen"; 448 321 449 322 resets = <&gcc GCC_PCIE_PHY_BCR>; 450 323 reset-names = "phy"; ··· 457 324 458 325 status = "disabled"; 459 326 460 - pcie0_lane: lanes@1c06000 { 327 + pcie_lane: lanes@1c06000 { 461 328 reg = <0x01c06000 0x104>, /* tx0 */ 462 329 <0x01c06200 0x328>, /* rx0 */ 463 330 <0x01c07200 0x1e8>, /* pcs */ ··· 518 385 }; 519 386 520 387 tcsr: syscon@1fcb000 { 521 - compatible = "syscon"; 388 + compatible = "qcom,sdx55-tcsr", "syscon"; 522 389 reg = <0x01fc0000 0x1000>; 523 390 }; 524 391 ··· 531 398 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 532 399 <&gcc GCC_SDCC1_APPS_CLK>; 533 400 clock-names = "iface", "core"; 534 - status = "disabled"; 535 - }; 536 - 537 - pcie_ep: pcie-ep@40000000 { 538 - compatible = "qcom,sdx55-pcie-ep"; 539 - reg = <0x01c00000 0x3000>, 540 - <0x40000000 0xf1d>, 541 - <0x40000f20 0xc8>, 542 - <0x40001000 0x1000>, 543 - <0x40200000 0x100000>, 544 - <0x01c03000 0x3000>; 545 - reg-names = "parf", "dbi", "elbi", "atu", "addr_space", 546 - "mmio"; 547 - 548 - qcom,perst-regs = <&tcsr 0xb258 0xb270>; 549 - 550 - clocks = <&gcc GCC_PCIE_AUX_CLK>, 551 - <&gcc GCC_PCIE_CFG_AHB_CLK>, 552 - <&gcc GCC_PCIE_MSTR_AXI_CLK>, 553 - <&gcc GCC_PCIE_SLV_AXI_CLK>, 554 - <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, 555 - <&gcc GCC_PCIE_SLEEP_CLK>, 556 - <&gcc GCC_PCIE_0_CLKREF_CLK>; 557 - clock-names = "aux", "cfg", "bus_master", "bus_slave", 558 - "slave_q2a", "sleep", "ref"; 559 - 560 - interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 561 - <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 562 - interrupt-names = "global", "doorbell"; 563 - reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; 564 - wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; 565 - resets = <&gcc GCC_PCIE_BCR>; 566 - reset-names = "core"; 567 - power-domains = <&gcc PCIE_GDSC>; 568 - phys = <&pcie0_lane>; 569 - phy-names = "pciephy"; 570 - max-link-speed = <3>; 571 - num-lanes = <2>; 572 - 573 401 status = "disabled"; 574 402 }; 575 403