tjh.dev / kernel
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Merge branch 'icc-sa8775p' into icc-next

This enables QoS configuration for QNOC type device which can be found
on SA8775P platform. It enables QoS configuration for master ports with
predefined priority and urgency forwarding. This helps in prioritizing
the traffic originating from different interconnect masters at NOC.
The system may function normally without this feature. However, enabling
QoS helps optimize latency and bandwidth across subsystems like CPU, GPU,
and multimedia engines, which becomes important in high-throughput
scenarios. This is a feature aimed at performance enhancement to improve
system performance under concurrent workloads.

* icc-sa8775p
dt-bindings: interconnect: add reg and clocks properties to enable QoS on sa8775p
interconnect: qcom: sa8775p: enable QoS configuration

Link: https://lore.kernel.org/r/20251001073344.6599-1-odelu.kukatla@oss.qualcomm.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>

Georgi Djakov 10ae71c9 b4e8b0f2

+489 -2
+50 -2
Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.yaml
··· 33 33 - qcom,sa8775p-pcie-anoc 34 34 - qcom,sa8775p-system-noc 35 35 36 + reg: 37 + maxItems: 1 38 + 39 + clocks: 40 + minItems: 2 41 + maxItems: 5 42 + 36 43 required: 37 44 - compatible 38 45 39 46 allOf: 40 47 - $ref: qcom,rpmh-common.yaml# 48 + - if: 49 + properties: 50 + compatible: 51 + contains: 52 + enum: 53 + - qcom,sa8775p-aggre1-noc 54 + then: 55 + properties: 56 + clocks: 57 + items: 58 + - description: aggre UFS PHY AXI clock 59 + - description: aggre QUP PRIM AXI clock 60 + - description: aggre USB2 PRIM AXI clock 61 + - description: aggre USB3 PRIM AXI clock 62 + - description: aggre USB3 SEC AXI clock 63 + 64 + - if: 65 + properties: 66 + compatible: 67 + contains: 68 + enum: 69 + - qcom,sa8775p-aggre2-noc 70 + then: 71 + properties: 72 + clocks: 73 + items: 74 + - description: aggre UFS CARD AXI clock 75 + - description: RPMH CC IPA clock 41 76 42 77 unevaluatedProperties: false 43 78 44 79 examples: 45 80 - | 46 - aggre1_noc: interconnect-aggre1-noc { 47 - compatible = "qcom,sa8775p-aggre1-noc"; 81 + #include <dt-bindings/clock/qcom,sa8775p-gcc.h> 82 + clk_virt: interconnect-clk-virt { 83 + compatible = "qcom,sa8775p-clk-virt"; 48 84 #interconnect-cells = <2>; 49 85 qcom,bcm-voters = <&apps_bcm_voter>; 86 + }; 87 + 88 + aggre1_noc: interconnect@16c0000 { 89 + compatible = "qcom,sa8775p-aggre1-noc"; 90 + reg = <0x016c0000 0x18080>; 91 + #interconnect-cells = <2>; 92 + qcom,bcm-voters = <&apps_bcm_voter>; 93 + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 94 + <&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>, 95 + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 96 + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 97 + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>; 50 98 };
+439
drivers/interconnect/qcom/sa8775p.c
··· 213 213 .name = "qxm_qup3", 214 214 .channels = 1, 215 215 .buswidth = 8, 216 + .qosbox = &(const struct qcom_icc_qosbox) { 217 + .num_ports = 1, 218 + .port_offsets = { 0x11000 }, 219 + .prio_fwd_disable = 1, 220 + .prio = 2, 221 + .urg_fwd = 0, 222 + }, 216 223 .num_links = 1, 217 224 .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, 218 225 }; ··· 228 221 .name = "xm_emac_0", 229 222 .channels = 1, 230 223 .buswidth = 8, 224 + .qosbox = &(const struct qcom_icc_qosbox) { 225 + .num_ports = 1, 226 + .port_offsets = { 0x12000 }, 227 + .prio_fwd_disable = 1, 228 + .prio = 2, 229 + .urg_fwd = 0, 230 + }, 231 231 .num_links = 1, 232 232 .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, 233 233 }; ··· 243 229 .name = "xm_emac_1", 244 230 .channels = 1, 245 231 .buswidth = 8, 232 + .qosbox = &(const struct qcom_icc_qosbox) { 233 + .num_ports = 1, 234 + .port_offsets = { 0x13000 }, 235 + .prio_fwd_disable = 1, 236 + .prio = 2, 237 + .urg_fwd = 0, 238 + }, 246 239 .num_links = 1, 247 240 .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, 248 241 }; ··· 258 237 .name = "xm_sdc1", 259 238 .channels = 1, 260 239 .buswidth = 8, 240 + .qosbox = &(const struct qcom_icc_qosbox) { 241 + .num_ports = 1, 242 + .port_offsets = { 0x14000 }, 243 + .prio_fwd_disable = 1, 244 + .prio = 2, 245 + .urg_fwd = 0, 246 + }, 261 247 .num_links = 1, 262 248 .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, 263 249 }; ··· 273 245 .name = "xm_ufs_mem", 274 246 .channels = 1, 275 247 .buswidth = 8, 248 + .qosbox = &(const struct qcom_icc_qosbox) { 249 + .num_ports = 1, 250 + .port_offsets = { 0x15000 }, 251 + .prio_fwd_disable = 1, 252 + .prio = 2, 253 + .urg_fwd = 0, 254 + }, 276 255 .num_links = 1, 277 256 .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, 278 257 }; ··· 288 253 .name = "xm_usb2_2", 289 254 .channels = 1, 290 255 .buswidth = 8, 256 + .qosbox = &(const struct qcom_icc_qosbox) { 257 + .num_ports = 1, 258 + .port_offsets = { 0x16000 }, 259 + .prio_fwd_disable = 1, 260 + .prio = 2, 261 + .urg_fwd = 0, 262 + }, 291 263 .num_links = 1, 292 264 .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, 293 265 }; ··· 303 261 .name = "xm_usb3_0", 304 262 .channels = 1, 305 263 .buswidth = 8, 264 + .qosbox = &(const struct qcom_icc_qosbox) { 265 + .num_ports = 1, 266 + .port_offsets = { 0x17000 }, 267 + .prio_fwd_disable = 1, 268 + .prio = 2, 269 + .urg_fwd = 0, 270 + }, 306 271 .num_links = 1, 307 272 .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, 308 273 }; ··· 318 269 .name = "xm_usb3_1", 319 270 .channels = 1, 320 271 .buswidth = 8, 272 + .qosbox = &(const struct qcom_icc_qosbox) { 273 + .num_ports = 1, 274 + .port_offsets = { 0x18000 }, 275 + .prio_fwd_disable = 1, 276 + .prio = 2, 277 + .urg_fwd = 0, 278 + }, 321 279 .num_links = 1, 322 280 .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, 323 281 }; ··· 333 277 .name = "qhm_qdss_bam", 334 278 .channels = 1, 335 279 .buswidth = 4, 280 + .qosbox = &(const struct qcom_icc_qosbox) { 281 + .num_ports = 1, 282 + .port_offsets = { 0x14000 }, 283 + .prio_fwd_disable = 1, 284 + .prio = 2, 285 + .urg_fwd = 0, 286 + }, 336 287 .num_links = 1, 337 288 .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, 338 289 }; ··· 348 285 .name = "qhm_qup0", 349 286 .channels = 1, 350 287 .buswidth = 4, 288 + .qosbox = &(const struct qcom_icc_qosbox) { 289 + .num_ports = 1, 290 + .port_offsets = { 0x17000 }, 291 + .prio_fwd_disable = 1, 292 + .prio = 2, 293 + .urg_fwd = 0, 294 + }, 351 295 .num_links = 1, 352 296 .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, 353 297 }; ··· 363 293 .name = "qhm_qup1", 364 294 .channels = 1, 365 295 .buswidth = 4, 296 + .qosbox = &(const struct qcom_icc_qosbox) { 297 + .num_ports = 1, 298 + .port_offsets = { 0x12000 }, 299 + .prio_fwd_disable = 1, 300 + .prio = 2, 301 + .urg_fwd = 0, 302 + }, 366 303 .num_links = 1, 367 304 .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, 368 305 }; ··· 378 301 .name = "qhm_qup2", 379 302 .channels = 1, 380 303 .buswidth = 4, 304 + .qosbox = &(const struct qcom_icc_qosbox) { 305 + .num_ports = 1, 306 + .port_offsets = { 0x15000 }, 307 + .prio_fwd_disable = 1, 308 + .prio = 2, 309 + .urg_fwd = 0, 310 + }, 381 311 .num_links = 1, 382 312 .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, 383 313 }; ··· 393 309 .name = "qnm_cnoc_datapath", 394 310 .channels = 1, 395 311 .buswidth = 8, 312 + .qosbox = &(const struct qcom_icc_qosbox) { 313 + .num_ports = 1, 314 + .port_offsets = { 0x16000 }, 315 + .prio_fwd_disable = 1, 316 + .prio = 2, 317 + .urg_fwd = 0, 318 + }, 396 319 .num_links = 1, 397 320 .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, 398 321 }; ··· 408 317 .name = "qxm_crypto_0", 409 318 .channels = 1, 410 319 .buswidth = 8, 320 + .qosbox = &(const struct qcom_icc_qosbox) { 321 + .num_ports = 1, 322 + .port_offsets = { 0x18000 }, 323 + .prio_fwd_disable = 1, 324 + .prio = 2, 325 + .urg_fwd = 0, 326 + }, 411 327 .num_links = 1, 412 328 .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, 413 329 }; ··· 423 325 .name = "qxm_crypto_1", 424 326 .channels = 1, 425 327 .buswidth = 8, 328 + .qosbox = &(const struct qcom_icc_qosbox) { 329 + .num_ports = 1, 330 + .port_offsets = { 0x1a000 }, 331 + .prio_fwd_disable = 1, 332 + .prio = 2, 333 + .urg_fwd = 0, 334 + }, 426 335 .num_links = 1, 427 336 .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, 428 337 }; ··· 438 333 .name = "qxm_ipa", 439 334 .channels = 1, 440 335 .buswidth = 8, 336 + .qosbox = &(const struct qcom_icc_qosbox) { 337 + .num_ports = 1, 338 + .port_offsets = { 0x11000 }, 339 + .prio_fwd_disable = 1, 340 + .prio = 2, 341 + .urg_fwd = 0, 342 + }, 441 343 .num_links = 1, 442 344 .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, 443 345 }; ··· 453 341 .name = "xm_qdss_etr_0", 454 342 .channels = 1, 455 343 .buswidth = 8, 344 + .qosbox = &(const struct qcom_icc_qosbox) { 345 + .num_ports = 1, 346 + .port_offsets = { 0x13000 }, 347 + .prio_fwd_disable = 1, 348 + .prio = 2, 349 + .urg_fwd = 0, 350 + }, 456 351 .num_links = 1, 457 352 .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, 458 353 }; ··· 468 349 .name = "xm_qdss_etr_1", 469 350 .channels = 1, 470 351 .buswidth = 8, 352 + .qosbox = &(const struct qcom_icc_qosbox) { 353 + .num_ports = 1, 354 + .port_offsets = { 0x19000 }, 355 + .prio_fwd_disable = 1, 356 + .prio = 2, 357 + .urg_fwd = 0, 358 + }, 471 359 .num_links = 1, 472 360 .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, 473 361 }; ··· 483 357 .name = "xm_ufs_card", 484 358 .channels = 1, 485 359 .buswidth = 8, 360 + .qosbox = &(const struct qcom_icc_qosbox) { 361 + .num_ports = 1, 362 + .port_offsets = { 0x1b000 }, 363 + .prio_fwd_disable = 1, 364 + .prio = 2, 365 + .urg_fwd = 0, 366 + }, 486 367 .num_links = 1, 487 368 .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, 488 369 }; ··· 594 461 .name = "alm_gpu_tcu", 595 462 .channels = 1, 596 463 .buswidth = 8, 464 + .qosbox = &(const struct qcom_icc_qosbox) { 465 + .num_ports = 1, 466 + .port_offsets = { 0xb4000 }, 467 + .prio_fwd_disable = 1, 468 + .prio = 1, 469 + .urg_fwd = 0, 470 + }, 597 471 .num_links = 2, 598 472 .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, 599 473 }; ··· 609 469 .name = "alm_pcie_tcu", 610 470 .channels = 1, 611 471 .buswidth = 8, 472 + .qosbox = &(const struct qcom_icc_qosbox) { 473 + .num_ports = 1, 474 + .port_offsets = { 0xb5000 }, 475 + .prio_fwd_disable = 1, 476 + .prio = 3, 477 + .urg_fwd = 0, 478 + }, 612 479 .num_links = 2, 613 480 .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, 614 481 }; ··· 624 477 .name = "alm_sys_tcu", 625 478 .channels = 1, 626 479 .buswidth = 8, 480 + .qosbox = &(const struct qcom_icc_qosbox) { 481 + .num_ports = 1, 482 + .port_offsets = { 0xb6000 }, 483 + .prio_fwd_disable = 1, 484 + .prio = 6, 485 + .urg_fwd = 0, 486 + }, 627 487 .num_links = 2, 628 488 .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, 629 489 }; ··· 648 494 .name = "qnm_cmpnoc0", 649 495 .channels = 2, 650 496 .buswidth = 32, 497 + .qosbox = &(const struct qcom_icc_qosbox) { 498 + .num_ports = 2, 499 + .port_offsets = { 0xf3000, 0xf4000 }, 500 + .prio_fwd_disable = 1, 501 + .prio = 0, 502 + .urg_fwd = 0, 503 + }, 651 504 .num_links = 2, 652 505 .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, 653 506 }; ··· 663 502 .name = "qnm_cmpnoc1", 664 503 .channels = 2, 665 504 .buswidth = 32, 505 + .qosbox = &(const struct qcom_icc_qosbox) { 506 + .num_ports = 2, 507 + .port_offsets = { 0xf5000, 0xf6000 }, 508 + .prio_fwd_disable = 1, 509 + .prio = 0, 510 + .urg_fwd = 0, 511 + }, 666 512 .num_links = 2, 667 513 .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, 668 514 }; ··· 695 527 .name = "qnm_gpu", 696 528 .channels = 2, 697 529 .buswidth = 32, 530 + .qosbox = &(const struct qcom_icc_qosbox) { 531 + .num_ports = 2, 532 + .port_offsets = { 0xed000, 0xee000 }, 533 + .prio_fwd_disable = 1, 534 + .prio = 0, 535 + .urg_fwd = 0, 536 + }, 698 537 .num_links = 2, 699 538 .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, 700 539 }; ··· 710 535 .name = "qnm_mnoc_hf", 711 536 .channels = 2, 712 537 .buswidth = 32, 538 + .qosbox = &(const struct qcom_icc_qosbox) { 539 + .num_ports = 2, 540 + .port_offsets = { 0xef000, 0xf0000 }, 541 + .prio_fwd_disable = 0, 542 + .prio = 0, 543 + .urg_fwd = 1, 544 + }, 713 545 .num_links = 2, 714 546 .link_nodes = (struct qcom_icc_node *[]) { &qns_llcc, &qns_pcie }, 715 547 }; ··· 725 543 .name = "qnm_mnoc_sf", 726 544 .channels = 2, 727 545 .buswidth = 32, 546 + .qosbox = &(const struct qcom_icc_qosbox) { 547 + .num_ports = 2, 548 + .port_offsets = { 0xf1000, 0xf2000 }, 549 + .prio_fwd_disable = 0, 550 + .prio = 0, 551 + .urg_fwd = 1, 552 + }, 728 553 .num_links = 3, 729 554 .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, 730 555 &qns_pcie }, ··· 741 552 .name = "qnm_pcie", 742 553 .channels = 1, 743 554 .buswidth = 32, 555 + .qosbox = &(const struct qcom_icc_qosbox) { 556 + .num_ports = 1, 557 + .port_offsets = { 0xb8000 }, 558 + .prio_fwd_disable = 1, 559 + .prio = 2, 560 + .urg_fwd = 0, 561 + }, 744 562 .num_links = 2, 745 563 .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc }, 746 564 }; ··· 756 560 .name = "qnm_snoc_gc", 757 561 .channels = 1, 758 562 .buswidth = 8, 563 + .qosbox = &(const struct qcom_icc_qosbox) { 564 + .num_ports = 1, 565 + .port_offsets = { 0xb9000 }, 566 + .prio_fwd_disable = 0, 567 + .prio = 0, 568 + .urg_fwd = 1, 569 + }, 759 570 .num_links = 1, 760 571 .link_nodes = (struct qcom_icc_node *[]) { &qns_llcc }, 761 572 }; ··· 771 568 .name = "qnm_snoc_sf", 772 569 .channels = 1, 773 570 .buswidth = 16, 571 + .qosbox = &(const struct qcom_icc_qosbox) { 572 + .num_ports = 1, 573 + .port_offsets = { 0xba000 }, 574 + .prio_fwd_disable = 0, 575 + .prio = 0, 576 + .urg_fwd = 1, 577 + }, 774 578 .num_links = 3, 775 579 .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, 776 580 &qns_pcie }, ··· 830 620 .name = "qnm_camnoc_hf", 831 621 .channels = 1, 832 622 .buswidth = 32, 623 + .qosbox = &(const struct qcom_icc_qosbox) { 624 + .num_ports = 1, 625 + .port_offsets = { 0xa000 }, 626 + .prio_fwd_disable = 0, 627 + .prio = 0, 628 + .urg_fwd = 1, 629 + }, 833 630 .num_links = 1, 834 631 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, 835 632 }; ··· 845 628 .name = "qnm_camnoc_icp", 846 629 .channels = 1, 847 630 .buswidth = 8, 631 + .qosbox = &(const struct qcom_icc_qosbox) { 632 + .num_ports = 1, 633 + .port_offsets = { 0x2a000 }, 634 + .prio_fwd_disable = 0, 635 + .prio = 0, 636 + .urg_fwd = 1, 637 + }, 848 638 .num_links = 1, 849 639 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, 850 640 }; ··· 860 636 .name = "qnm_camnoc_sf", 861 637 .channels = 1, 862 638 .buswidth = 32, 639 + .qosbox = &(const struct qcom_icc_qosbox) { 640 + .num_ports = 1, 641 + .port_offsets = { 0x2a080 }, 642 + .prio_fwd_disable = 0, 643 + .prio = 0, 644 + .urg_fwd = 1, 645 + }, 863 646 .num_links = 1, 864 647 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, 865 648 }; ··· 875 644 .name = "qnm_mdp0_0", 876 645 .channels = 1, 877 646 .buswidth = 32, 647 + .qosbox = &(const struct qcom_icc_qosbox) { 648 + .num_ports = 1, 649 + .port_offsets = { 0xa080 }, 650 + .prio_fwd_disable = 0, 651 + .prio = 0, 652 + .urg_fwd = 1, 653 + }, 878 654 .num_links = 1, 879 655 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, 880 656 }; ··· 890 652 .name = "qnm_mdp0_1", 891 653 .channels = 1, 892 654 .buswidth = 32, 655 + .qosbox = &(const struct qcom_icc_qosbox) { 656 + .num_ports = 1, 657 + .port_offsets = { 0xa180 }, 658 + .prio_fwd_disable = 0, 659 + .prio = 0, 660 + .urg_fwd = 1, 661 + }, 893 662 .num_links = 1, 894 663 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, 895 664 }; ··· 905 660 .name = "qnm_mdp1_0", 906 661 .channels = 1, 907 662 .buswidth = 32, 663 + .qosbox = &(const struct qcom_icc_qosbox) { 664 + .num_ports = 1, 665 + .port_offsets = { 0xa100 }, 666 + .prio_fwd_disable = 0, 667 + .prio = 0, 668 + .urg_fwd = 1, 669 + }, 908 670 .num_links = 1, 909 671 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, 910 672 }; ··· 920 668 .name = "qnm_mdp1_1", 921 669 .channels = 1, 922 670 .buswidth = 32, 671 + .qosbox = &(const struct qcom_icc_qosbox) { 672 + .num_ports = 1, 673 + .port_offsets = { 0xa200 }, 674 + .prio_fwd_disable = 0, 675 + .prio = 0, 676 + .urg_fwd = 1, 677 + }, 923 678 .num_links = 1, 924 679 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, 925 680 }; ··· 951 692 .name = "qnm_video0", 952 693 .channels = 1, 953 694 .buswidth = 32, 695 + .qosbox = &(const struct qcom_icc_qosbox) { 696 + .num_ports = 1, 697 + .port_offsets = { 0x2a100 }, 698 + .prio_fwd_disable = 0, 699 + .prio = 0, 700 + .urg_fwd = 1, 701 + }, 954 702 .num_links = 1, 955 703 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, 956 704 }; ··· 966 700 .name = "qnm_video1", 967 701 .channels = 1, 968 702 .buswidth = 32, 703 + .qosbox = &(const struct qcom_icc_qosbox) { 704 + .num_ports = 1, 705 + .port_offsets = { 0x2a180 }, 706 + .prio_fwd_disable = 0, 707 + .prio = 0, 708 + .urg_fwd = 1, 709 + }, 969 710 .num_links = 1, 970 711 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, 971 712 }; ··· 981 708 .name = "qnm_video_cvp", 982 709 .channels = 1, 983 710 .buswidth = 32, 711 + .qosbox = &(const struct qcom_icc_qosbox) { 712 + .num_ports = 1, 713 + .port_offsets = { 0x2a200 }, 714 + .prio_fwd_disable = 0, 715 + .prio = 0, 716 + .urg_fwd = 1, 717 + }, 984 718 .num_links = 1, 985 719 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, 986 720 }; ··· 996 716 .name = "qnm_video_v_cpu", 997 717 .channels = 1, 998 718 .buswidth = 8, 719 + .qosbox = &(const struct qcom_icc_qosbox) { 720 + .num_ports = 1, 721 + .port_offsets = { 0x2a280 }, 722 + .prio_fwd_disable = 0, 723 + .prio = 0, 724 + .urg_fwd = 1, 725 + }, 999 726 .num_links = 1, 1000 727 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, 1001 728 }; ··· 1043 756 .name = "xm_pcie3_0", 1044 757 .channels = 1, 1045 758 .buswidth = 16, 759 + .qosbox = &(const struct qcom_icc_qosbox) { 760 + .num_ports = 1, 761 + .port_offsets = { 0xb000 }, 762 + .prio_fwd_disable = 1, 763 + .prio = 2, 764 + .urg_fwd = 0, 765 + }, 1046 766 .num_links = 1, 1047 767 .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_mem_noc }, 1048 768 }; ··· 1058 764 .name = "xm_pcie3_1", 1059 765 .channels = 1, 1060 766 .buswidth = 32, 767 + .qosbox = &(const struct qcom_icc_qosbox) { 768 + .num_ports = 1, 769 + .port_offsets = { 0xc000 }, 770 + .prio_fwd_disable = 1, 771 + .prio = 2, 772 + .urg_fwd = 0, 773 + }, 1061 774 .num_links = 1, 1062 775 .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_mem_noc }, 1063 776 }; ··· 1073 772 .name = "qhm_gic", 1074 773 .channels = 1, 1075 774 .buswidth = 4, 775 + .qosbox = &(const struct qcom_icc_qosbox) { 776 + .num_ports = 1, 777 + .port_offsets = { 0x14000 }, 778 + .prio_fwd_disable = 1, 779 + .prio = 2, 780 + .urg_fwd = 0, 781 + }, 1076 782 .num_links = 1, 1077 783 .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, 1078 784 }; ··· 1104 796 .name = "qnm_lpass_noc", 1105 797 .channels = 1, 1106 798 .buswidth = 16, 799 + .qosbox = &(const struct qcom_icc_qosbox) { 800 + .num_ports = 1, 801 + .port_offsets = { 0x12000 }, 802 + .prio_fwd_disable = 0, 803 + .prio = 0, 804 + .urg_fwd = 1, 805 + }, 1107 806 .num_links = 1, 1108 807 .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, 1109 808 }; ··· 1127 812 .name = "qxm_pimem", 1128 813 .channels = 1, 1129 814 .buswidth = 8, 815 + .qosbox = &(const struct qcom_icc_qosbox) { 816 + .num_ports = 1, 817 + .port_offsets = { 0x13000 }, 818 + .prio_fwd_disable = 1, 819 + .prio = 2, 820 + .urg_fwd = 0, 821 + }, 1130 822 .num_links = 1, 1131 823 .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_gc }, 1132 824 }; ··· 1142 820 .name = "xm_gic", 1143 821 .channels = 1, 1144 822 .buswidth = 8, 823 + .qosbox = &(const struct qcom_icc_qosbox) { 824 + .num_ports = 1, 825 + .port_offsets = { 0x15000 }, 826 + .prio_fwd_disable = 1, 827 + .prio = 2, 828 + .urg_fwd = 0, 829 + }, 1145 830 .num_links = 1, 1146 831 .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_gc }, 1147 832 }; ··· 2165 1836 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 2166 1837 }; 2167 1838 1839 + static const struct regmap_config sa8775p_aggre1_noc_regmap_config = { 1840 + .reg_bits = 32, 1841 + .reg_stride = 4, 1842 + .val_bits = 32, 1843 + .max_register = 0x18080, 1844 + .fast_io = true, 1845 + }; 1846 + 2168 1847 static const struct qcom_icc_desc sa8775p_aggre1_noc = { 1848 + .config = &sa8775p_aggre1_noc_regmap_config, 2169 1849 .nodes = aggre1_noc_nodes, 2170 1850 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 2171 1851 .bcms = aggre1_noc_bcms, 2172 1852 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 2173 1853 .alloc_dyn_id = true, 1854 + .qos_requires_clocks = true, 2174 1855 }; 2175 1856 2176 1857 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { ··· 2203 1864 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 2204 1865 }; 2205 1866 1867 + static const struct regmap_config sa8775p_aggre2_noc_regmap_config = { 1868 + .reg_bits = 32, 1869 + .reg_stride = 4, 1870 + .val_bits = 32, 1871 + .max_register = 0x1b080, 1872 + .fast_io = true, 1873 + }; 1874 + 2206 1875 static const struct qcom_icc_desc sa8775p_aggre2_noc = { 1876 + .config = &sa8775p_aggre2_noc_regmap_config, 2207 1877 .nodes = aggre2_noc_nodes, 2208 1878 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 2209 1879 .bcms = aggre2_noc_bcms, 2210 1880 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 2211 1881 .alloc_dyn_id = true, 1882 + .qos_requires_clocks = true, 2212 1883 }; 2213 1884 2214 1885 static struct qcom_icc_bcm * const clk_virt_bcms[] = { ··· 2344 1995 [SLAVE_TCU] = &xs_sys_tcu_cfg, 2345 1996 }; 2346 1997 1998 + static const struct regmap_config sa8775p_config_noc_regmap_config = { 1999 + .reg_bits = 32, 2000 + .reg_stride = 4, 2001 + .val_bits = 32, 2002 + .max_register = 0x13080, 2003 + .fast_io = true, 2004 + }; 2005 + 2347 2006 static const struct qcom_icc_desc sa8775p_config_noc = { 2007 + .config = &sa8775p_config_noc_regmap_config, 2348 2008 .nodes = config_noc_nodes, 2349 2009 .num_nodes = ARRAY_SIZE(config_noc_nodes), 2350 2010 .bcms = config_noc_bcms, ··· 2370 2012 [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, 2371 2013 }; 2372 2014 2015 + static const struct regmap_config sa8775p_dc_noc_regmap_config = { 2016 + .reg_bits = 32, 2017 + .reg_stride = 4, 2018 + .val_bits = 32, 2019 + .max_register = 0x5080, 2020 + .fast_io = true, 2021 + }; 2022 + 2373 2023 static const struct qcom_icc_desc sa8775p_dc_noc = { 2024 + .config = &sa8775p_dc_noc_regmap_config, 2374 2025 .nodes = dc_noc_nodes, 2375 2026 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 2376 2027 .bcms = dc_noc_bcms, ··· 2416 2049 [SLAVE_SERVICE_GEM_NOC2] = &srvc_sys_gemnoc_2, 2417 2050 }; 2418 2051 2052 + static const struct regmap_config sa8775p_gem_noc_regmap_config = { 2053 + .reg_bits = 32, 2054 + .reg_stride = 4, 2055 + .val_bits = 32, 2056 + .max_register = 0xf6080, 2057 + .fast_io = true, 2058 + }; 2059 + 2419 2060 static const struct qcom_icc_desc sa8775p_gem_noc = { 2061 + .config = &sa8775p_gem_noc_regmap_config, 2420 2062 .nodes = gem_noc_nodes, 2421 2063 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 2422 2064 .bcms = gem_noc_bcms, ··· 2444 2068 [SLAVE_GP_DSP_SAIL_NOC] = &qns_gp_dsp_sail_noc, 2445 2069 }; 2446 2070 2071 + static const struct regmap_config sa8775p_gpdsp_anoc_regmap_config = { 2072 + .reg_bits = 32, 2073 + .reg_stride = 4, 2074 + .val_bits = 32, 2075 + .max_register = 0xe080, 2076 + .fast_io = true, 2077 + }; 2078 + 2447 2079 static const struct qcom_icc_desc sa8775p_gpdsp_anoc = { 2080 + .config = &sa8775p_gpdsp_anoc_regmap_config, 2448 2081 .nodes = gpdsp_anoc_nodes, 2449 2082 .num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes), 2450 2083 .bcms = gpdsp_anoc_bcms, ··· 2477 2092 [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, 2478 2093 }; 2479 2094 2095 + static const struct regmap_config sa8775p_lpass_ag_noc_regmap_config = { 2096 + .reg_bits = 32, 2097 + .reg_stride = 4, 2098 + .val_bits = 32, 2099 + .max_register = 0x17200, 2100 + .fast_io = true, 2101 + }; 2102 + 2480 2103 static const struct qcom_icc_desc sa8775p_lpass_ag_noc = { 2104 + .config = &sa8775p_lpass_ag_noc_regmap_config, 2481 2105 .nodes = lpass_ag_noc_nodes, 2482 2106 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), 2483 2107 .bcms = lpass_ag_noc_bcms, ··· 2537 2143 [SLAVE_SERVICE_MNOC_SF] = &srvc_mnoc_sf, 2538 2144 }; 2539 2145 2146 + static const struct regmap_config sa8775p_mmss_noc_regmap_config = { 2147 + .reg_bits = 32, 2148 + .reg_stride = 4, 2149 + .val_bits = 32, 2150 + .max_register = 0x40000, 2151 + .fast_io = true, 2152 + }; 2153 + 2540 2154 static const struct qcom_icc_desc sa8775p_mmss_noc = { 2155 + .config = &sa8775p_mmss_noc_regmap_config, 2541 2156 .nodes = mmss_noc_nodes, 2542 2157 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 2543 2158 .bcms = mmss_noc_bcms, ··· 2567 2164 [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, 2568 2165 }; 2569 2166 2167 + static const struct regmap_config sa8775p_nspa_noc_regmap_config = { 2168 + .reg_bits = 32, 2169 + .reg_stride = 4, 2170 + .val_bits = 32, 2171 + .max_register = 0x16080, 2172 + .fast_io = true, 2173 + }; 2174 + 2570 2175 static const struct qcom_icc_desc sa8775p_nspa_noc = { 2176 + .config = &sa8775p_nspa_noc_regmap_config, 2571 2177 .nodes = nspa_noc_nodes, 2572 2178 .num_nodes = ARRAY_SIZE(nspa_noc_nodes), 2573 2179 .bcms = nspa_noc_bcms, ··· 2589 2177 &bcm_nsb1, 2590 2178 }; 2591 2179 2180 + static const struct regmap_config sa8775p_nspb_noc_regmap_config = { 2181 + .reg_bits = 32, 2182 + .reg_stride = 4, 2183 + .val_bits = 32, 2184 + .max_register = 0x16080, 2185 + .fast_io = true, 2186 + }; 2187 + 2592 2188 static struct qcom_icc_node * const nspb_noc_nodes[] = { 2593 2189 [MASTER_CDSPB_NOC_CFG] = &qhm_nspb_noc_config, 2594 2190 [MASTER_CDSP_PROC_B] = &qxm_nspb, ··· 2606 2186 }; 2607 2187 2608 2188 static const struct qcom_icc_desc sa8775p_nspb_noc = { 2189 + .config = &sa8775p_nspb_noc_regmap_config, 2609 2190 .nodes = nspb_noc_nodes, 2610 2191 .num_nodes = ARRAY_SIZE(nspb_noc_nodes), 2611 2192 .bcms = nspb_noc_bcms, ··· 2624 2203 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, 2625 2204 }; 2626 2205 2206 + static const struct regmap_config sa8775p_pcie_anoc_regmap_config = { 2207 + .reg_bits = 32, 2208 + .reg_stride = 4, 2209 + .val_bits = 32, 2210 + .max_register = 0xc080, 2211 + .fast_io = true, 2212 + }; 2213 + 2627 2214 static const struct qcom_icc_desc sa8775p_pcie_anoc = { 2215 + .config = &sa8775p_pcie_anoc_regmap_config, 2628 2216 .nodes = pcie_anoc_nodes, 2629 2217 .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), 2630 2218 .bcms = pcie_anoc_bcms, ··· 2662 2232 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 2663 2233 }; 2664 2234 2235 + static const struct regmap_config sa8775p_system_noc_regmap_config = { 2236 + .reg_bits = 32, 2237 + .reg_stride = 4, 2238 + .val_bits = 32, 2239 + .max_register = 0x15080, 2240 + .fast_io = true, 2241 + }; 2242 + 2665 2243 static const struct qcom_icc_desc sa8775p_system_noc = { 2244 + .config = &sa8775p_system_noc_regmap_config, 2666 2245 .nodes = system_noc_nodes, 2667 2246 .num_nodes = ARRAY_SIZE(system_noc_nodes), 2668 2247 .bcms = system_noc_bcms,