drm/amdgpu: Delete some cgs functions · tjh.dev/kernel@10b3f45

-336

2 changed files

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drivers

gpu

drm

amd

amdgpu

amdgpu_cgs.c

include

cgs_common.h

-197

drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c

··· 23 23 */ 24 24 #include <linux/list.h> 25 25 #include <linux/slab.h> 26 - #include <linux/pci.h> 27 26 #include <drm/drmP.h> 28 27 #include <linux/firmware.h> 29 28 #include <drm/amdgpu_drm.h> ··· 108 109 WARN(1, "Invalid indirect register space"); 109 110 } 110 111 111 - static int amdgpu_cgs_get_pci_resource(struct cgs_device *cgs_device, 112 - enum cgs_resource_type resource_type, 113 - uint64_t size, 114 - uint64_t offset, 115 - uint64_t *resource_base) 116 - { 117 - CGS_FUNC_ADEV; 118 - 119 - if (resource_base == NULL) 120 - return -EINVAL; 121 - 122 - switch (resource_type) { 123 - case CGS_RESOURCE_TYPE_MMIO: 124 - if (adev->rmmio_size == 0) 125 - return -ENOENT; 126 - if ((offset + size) > adev->rmmio_size) 127 - return -EINVAL; 128 - *resource_base = adev->rmmio_base; 129 - return 0; 130 - case CGS_RESOURCE_TYPE_DOORBELL: 131 - if (adev->doorbell.size == 0) 132 - return -ENOENT; 133 - if ((offset + size) > adev->doorbell.size) 134 - return -EINVAL; 135 - *resource_base = adev->doorbell.base; 136 - return 0; 137 - case CGS_RESOURCE_TYPE_FB: 138 - case CGS_RESOURCE_TYPE_IO: 139 - case CGS_RESOURCE_TYPE_ROM: 140 - default: 141 - return -EINVAL; 142 - } 143 - } 144 - 145 - static const void *amdgpu_cgs_atom_get_data_table(struct cgs_device *cgs_device, 146 - unsigned table, uint16_t *size, 147 - uint8_t *frev, uint8_t *crev) 148 - { 149 - CGS_FUNC_ADEV; 150 - uint16_t data_start; 151 - 152 - if (amdgpu_atom_parse_data_header( 153 - adev->mode_info.atom_context, table, size, 154 - frev, crev, &data_start)) 155 - return (uint8_t*)adev->mode_info.atom_context->bios + 156 - data_start; 157 - 158 - return NULL; 159 - } 160 - 161 - static int amdgpu_cgs_atom_get_cmd_table_revs(struct cgs_device *cgs_device, unsigned table, 162 - uint8_t *frev, uint8_t *crev) 163 - { 164 - CGS_FUNC_ADEV; 165 - 166 - if (amdgpu_atom_parse_cmd_header( 167 - adev->mode_info.atom_context, table, 168 - frev, crev)) 169 - return 0; 170 - 171 - return -EINVAL; 172 - } 173 - 174 - static int amdgpu_cgs_atom_exec_cmd_table(struct cgs_device *cgs_device, unsigned table, 175 - void *args) 176 - { 177 - CGS_FUNC_ADEV; 178 - 179 - return amdgpu_atom_execute_table( 180 - adev->mode_info.atom_context, table, args); 181 - } 182 - 183 112 static int amdgpu_cgs_set_clockgating_state(struct cgs_device *cgs_device, 184 113 enum amd_ip_block_type block_type, 185 114 enum amd_clockgating_state state) ··· 149 222 } 150 223 return r; 151 224 } 152 - 153 225 154 226 static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type) 155 227 { ··· 197 271 return result; 198 272 } 199 273 200 - static int amdgpu_cgs_rel_firmware(struct cgs_device *cgs_device, enum cgs_ucode_id type) 201 - { 202 - CGS_FUNC_ADEV; 203 - if ((CGS_UCODE_ID_SMU == type) || (CGS_UCODE_ID_SMU_SK == type)) { 204 - release_firmware(adev->pm.fw); 205 - adev->pm.fw = NULL; 206 - return 0; 207 - } 208 - /* cannot release other firmware because they are not created by cgs */ 209 - return -EINVAL; 210 - } 211 - 212 274 static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device, 213 275 enum cgs_ucode_id type) 214 276 { ··· 238 324 break; 239 325 } 240 326 return fw_version; 241 - } 242 - 243 - static int amdgpu_cgs_enter_safe_mode(struct cgs_device *cgs_device, 244 - bool en) 245 - { 246 - CGS_FUNC_ADEV; 247 - 248 - if (adev->gfx.rlc.funcs->enter_safe_mode == NULL || 249 - adev->gfx.rlc.funcs->exit_safe_mode == NULL) 250 - return 0; 251 - 252 - if (en) 253 - adev->gfx.rlc.funcs->enter_safe_mode(adev); 254 - else 255 - adev->gfx.rlc.funcs->exit_safe_mode(adev); 256 - 257 - return 0; 258 - } 259 - 260 - static void amdgpu_cgs_lock_grbm_idx(struct cgs_device *cgs_device, 261 - bool lock) 262 - { 263 - CGS_FUNC_ADEV; 264 - 265 - if (lock) 266 - mutex_lock(&adev->grbm_idx_mutex); 267 - else 268 - mutex_unlock(&adev->grbm_idx_mutex); 269 327 } 270 328 271 329 static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, ··· 484 598 return 0; 485 599 } 486 600 487 - static int amdgpu_cgs_is_virtualization_enabled(void *cgs_device) 488 - { 489 - CGS_FUNC_ADEV; 490 - return amdgpu_sriov_vf(adev); 491 - } 492 - 493 - static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device, 494 - struct cgs_display_info *info) 495 - { 496 - CGS_FUNC_ADEV; 497 - struct cgs_mode_info *mode_info; 498 - 499 - if (info == NULL) 500 - return -EINVAL; 501 - 502 - mode_info = info->mode_info; 503 - if (mode_info) 504 - /* if the displays are off, vblank time is max */ 505 - mode_info->vblank_time_us = 0xffffffff; 506 - 507 - if (!amdgpu_device_has_dc_support(adev)) { 508 - struct amdgpu_crtc *amdgpu_crtc; 509 - struct drm_device *ddev = adev->ddev; 510 - struct drm_crtc *crtc; 511 - uint32_t line_time_us, vblank_lines; 512 - 513 - if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) { 514 - list_for_each_entry(crtc, 515 - &ddev->mode_config.crtc_list, head) { 516 - amdgpu_crtc = to_amdgpu_crtc(crtc); 517 - if (crtc->enabled) { 518 - info->active_display_mask |= (1 << amdgpu_crtc->crtc_id); 519 - info->display_count++; 520 - } 521 - if (mode_info != NULL && 522 - crtc->enabled && amdgpu_crtc->enabled && 523 - amdgpu_crtc->hw_mode.clock) { 524 - line_time_us = (amdgpu_crtc->hw_mode.crtc_htotal * 1000) / 525 - amdgpu_crtc->hw_mode.clock; 526 - vblank_lines = amdgpu_crtc->hw_mode.crtc_vblank_end - 527 - amdgpu_crtc->hw_mode.crtc_vdisplay + 528 - (amdgpu_crtc->v_border * 2); 529 - mode_info->vblank_time_us = vblank_lines * line_time_us; 530 - mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode); 531 - /* we have issues with mclk switching with refresh rates 532 - * over 120 hz on the non-DC code. 533 - */ 534 - if (mode_info->refresh_rate > 120) 535 - mode_info->vblank_time_us = 0; 536 - mode_info = NULL; 537 - } 538 - } 539 - } 540 - } else { 541 - info->display_count = adev->pm.pm_display_cfg.num_display; 542 - if (mode_info != NULL) { 543 - mode_info->vblank_time_us = adev->pm.pm_display_cfg.min_vblank_time; 544 - mode_info->refresh_rate = adev->pm.pm_display_cfg.vrefresh; 545 - } 546 - } 547 - return 0; 548 - } 549 - 550 - 551 - static int amdgpu_cgs_notify_dpm_enabled(struct cgs_device *cgs_device, bool enabled) 552 - { 553 - CGS_FUNC_ADEV; 554 - 555 - adev->pm.dpm_enabled = enabled; 556 - 557 - return 0; 558 - } 559 - 560 601 static const struct cgs_ops amdgpu_cgs_ops = { 561 602 .read_register = amdgpu_cgs_read_register, 562 603 .write_register = amdgpu_cgs_write_register, 563 604 .read_ind_register = amdgpu_cgs_read_ind_register, 564 605 .write_ind_register = amdgpu_cgs_write_ind_register, 565 - .get_pci_resource = amdgpu_cgs_get_pci_resource, 566 - .atom_get_data_table = amdgpu_cgs_atom_get_data_table, 567 - .atom_get_cmd_table_revs = amdgpu_cgs_atom_get_cmd_table_revs, 568 - .atom_exec_cmd_table = amdgpu_cgs_atom_exec_cmd_table, 569 606 .get_firmware_info = amdgpu_cgs_get_firmware_info, 570 - .rel_firmware = amdgpu_cgs_rel_firmware, 571 607 .set_powergating_state = amdgpu_cgs_set_powergating_state, 572 608 .set_clockgating_state = amdgpu_cgs_set_clockgating_state, 573 - .get_active_displays_info = amdgpu_cgs_get_active_displays_info, 574 - .notify_dpm_enabled = amdgpu_cgs_notify_dpm_enabled, 575 - .is_virtualization_enabled = amdgpu_cgs_is_virtualization_enabled, 576 - .enter_safe_mode = amdgpu_cgs_enter_safe_mode, 577 - .lock_grbm_idx = amdgpu_cgs_lock_grbm_idx, 578 609 }; 579 610 580 611 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev)

-139

drivers/gpu/drm/amd/include/cgs_common.h

··· 76 76 CGS_UCODE_ID_MAXIMUM, 77 77 }; 78 78 79 - /* 80 - * enum cgs_resource_type - GPU resource type 81 - */ 82 - enum cgs_resource_type { 83 - CGS_RESOURCE_TYPE_MMIO = 0, 84 - CGS_RESOURCE_TYPE_FB, 85 - CGS_RESOURCE_TYPE_IO, 86 - CGS_RESOURCE_TYPE_DOORBELL, 87 - CGS_RESOURCE_TYPE_ROM, 88 - }; 89 - 90 79 /** 91 80 * struct cgs_firmware_info - Firmware information 92 81 */ ··· 91 102 92 103 void *kptr; 93 104 bool is_kicker; 94 - }; 95 - 96 - struct cgs_mode_info { 97 - uint32_t refresh_rate; 98 - uint32_t vblank_time_us; 99 - }; 100 - 101 - struct cgs_display_info { 102 - uint32_t display_count; 103 - uint32_t active_display_mask; 104 - struct cgs_mode_info *mode_info; 105 105 }; 106 106 107 107 typedef unsigned long cgs_handle_t; ··· 148 170 #define CGS_WREG32_FIELD_IND(device, space, reg, field, val) \ 149 171 cgs_write_ind_register(device, space, ix##reg, (cgs_read_ind_register(device, space, ix##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field)) 150 172 151 - /** 152 - * cgs_get_pci_resource() - provide access to a device resource (PCI BAR) 153 - * @cgs_device: opaque device handle 154 - * @resource_type: Type of Resource (MMIO, IO, ROM, FB, DOORBELL) 155 - * @size: size of the region 156 - * @offset: offset from the start of the region 157 - * @resource_base: base address (not including offset) returned 158 - * 159 - * Return: 0 on success, -errno otherwise 160 - */ 161 - typedef int (*cgs_get_pci_resource_t)(struct cgs_device *cgs_device, 162 - enum cgs_resource_type resource_type, 163 - uint64_t size, 164 - uint64_t offset, 165 - uint64_t *resource_base); 166 - 167 - /** 168 - * cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table 169 - * @cgs_device: opaque device handle 170 - * @table: data table index 171 - * @size: size of the table (output, may be NULL) 172 - * @frev: table format revision (output, may be NULL) 173 - * @crev: table content revision (output, may be NULL) 174 - * 175 - * Return: Pointer to start of the table, or NULL on failure 176 - */ 177 - typedef const void *(*cgs_atom_get_data_table_t)( 178 - struct cgs_device *cgs_device, unsigned table, 179 - uint16_t *size, uint8_t *frev, uint8_t *crev); 180 - 181 - /** 182 - * cgs_atom_get_cmd_table_revs() - Get ATOM BIOS command table revisions 183 - * @cgs_device: opaque device handle 184 - * @table: data table index 185 - * @frev: table format revision (output, may be NULL) 186 - * @crev: table content revision (output, may be NULL) 187 - * 188 - * Return: 0 on success, -errno otherwise 189 - */ 190 - typedef int (*cgs_atom_get_cmd_table_revs_t)(struct cgs_device *cgs_device, unsigned table, 191 - uint8_t *frev, uint8_t *crev); 192 - 193 - /** 194 - * cgs_atom_exec_cmd_table() - Execute an ATOM BIOS command table 195 - * @cgs_device: opaque device handle 196 - * @table: command table index 197 - * @args: arguments 198 - * 199 - * Return: 0 on success, -errno otherwise 200 - */ 201 - typedef int (*cgs_atom_exec_cmd_table_t)(struct cgs_device *cgs_device, 202 - unsigned table, void *args); 203 - 204 - /** 205 - * cgs_get_firmware_info - Get the firmware information from core driver 206 - * @cgs_device: opaque device handle 207 - * @type: the firmware type 208 - * @info: returend firmware information 209 - * 210 - * Return: 0 on success, -errno otherwise 211 - */ 212 173 typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device, 213 174 enum cgs_ucode_id type, 214 175 struct cgs_firmware_info *info); 215 176 216 - typedef int (*cgs_rel_firmware)(struct cgs_device *cgs_device, 217 - enum cgs_ucode_id type); 218 177 219 178 typedef int(*cgs_set_powergating_state)(struct cgs_device *cgs_device, 220 179 enum amd_ip_block_type block_type, ··· 161 246 enum amd_ip_block_type block_type, 162 247 enum amd_clockgating_state state); 163 248 164 - typedef int(*cgs_get_active_displays_info)( 165 - struct cgs_device *cgs_device, 166 - struct cgs_display_info *info); 167 - 168 - typedef int (*cgs_notify_dpm_enabled)(struct cgs_device *cgs_device, bool enabled); 169 - 170 - typedef int (*cgs_is_virtualization_enabled_t)(void *cgs_device); 171 - 172 - typedef int (*cgs_enter_safe_mode)(struct cgs_device *cgs_device, bool en); 173 - 174 - typedef void (*cgs_lock_grbm_idx)(struct cgs_device *cgs_device, bool lock); 175 - 176 249 struct cgs_ops { 177 250 /* MMIO access */ 178 251 cgs_read_register_t read_register; 179 252 cgs_write_register_t write_register; 180 253 cgs_read_ind_register_t read_ind_register; 181 254 cgs_write_ind_register_t write_ind_register; 182 - /* PCI resources */ 183 - cgs_get_pci_resource_t get_pci_resource; 184 - /* ATOM BIOS */ 185 - cgs_atom_get_data_table_t atom_get_data_table; 186 - cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs; 187 - cgs_atom_exec_cmd_table_t atom_exec_cmd_table; 188 255 /* Firmware Info */ 189 256 cgs_get_firmware_info get_firmware_info; 190 - cgs_rel_firmware rel_firmware; 191 257 /* cg pg interface*/ 192 258 cgs_set_powergating_state set_powergating_state; 193 259 cgs_set_clockgating_state set_clockgating_state; 194 - /* display manager */ 195 - cgs_get_active_displays_info get_active_displays_info; 196 - /* notify dpm enabled */ 197 - cgs_notify_dpm_enabled notify_dpm_enabled; 198 - cgs_is_virtualization_enabled_t is_virtualization_enabled; 199 - cgs_enter_safe_mode enter_safe_mode; 200 - cgs_lock_grbm_idx lock_grbm_idx; 201 260 }; 202 261 203 262 struct cgs_os_ops; /* To be define in OS-specific CGS header */ ··· 198 309 #define cgs_write_ind_register(dev,space,index,value) \ 199 310 CGS_CALL(write_ind_register,dev,space,index,value) 200 311 201 - #define cgs_atom_get_data_table(dev,table,size,frev,crev) \ 202 - CGS_CALL(atom_get_data_table,dev,table,size,frev,crev) 203 - #define cgs_atom_get_cmd_table_revs(dev,table,frev,crev) \ 204 - CGS_CALL(atom_get_cmd_table_revs,dev,table,frev,crev) 205 - #define cgs_atom_exec_cmd_table(dev,table,args) \ 206 - CGS_CALL(atom_exec_cmd_table,dev,table,args) 207 - 208 312 #define cgs_get_firmware_info(dev, type, info) \ 209 313 CGS_CALL(get_firmware_info, dev, type, info) 210 - #define cgs_rel_firmware(dev, type) \ 211 - CGS_CALL(rel_firmware, dev, type) 212 314 #define cgs_set_powergating_state(dev, block_type, state) \ 213 315 CGS_CALL(set_powergating_state, dev, block_type, state) 214 316 #define cgs_set_clockgating_state(dev, block_type, state) \ 215 317 CGS_CALL(set_clockgating_state, dev, block_type, state) 216 - #define cgs_notify_dpm_enabled(dev, enabled) \ 217 - CGS_CALL(notify_dpm_enabled, dev, enabled) 218 - 219 - #define cgs_get_active_displays_info(dev, info) \ 220 - CGS_CALL(get_active_displays_info, dev, info) 221 - 222 - #define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \ 223 - resource_base) \ 224 - CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \ 225 - resource_base) 226 - 227 - #define cgs_is_virtualization_enabled(cgs_device) \ 228 - CGS_CALL(is_virtualization_enabled, cgs_device) 229 - 230 - #define cgs_enter_safe_mode(cgs_device, en) \ 231 - CGS_CALL(enter_safe_mode, cgs_device, en) 232 - 233 - #define cgs_lock_grbm_idx(cgs_device, lock) \ 234 - CGS_CALL(lock_grbm_idx, cgs_device, lock) 235 318 236 319 237 320 #endif /* _CGS_COMMON_H */

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