Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/pp: Not call cgs interface to get display info
DC/Non DC all will update display configuration
when the display state changed
No need to get display info through cgs interface
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Rex Zhu
and committed by
Alex Deucher
555fd70c
d91ea496
+61
-136
+1
drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+1
drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+3
-5
drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+3
-5
drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
···
265
265
if (display_config == NULL)
266
266
return -EINVAL;
267
267
268
-
hwmgr->display_config = *display_config;
269
-
270
268
if (NULL != hwmgr->hwmgr_func->set_deep_sleep_dcefclk)
271
-
hwmgr->hwmgr_func->set_deep_sleep_dcefclk(hwmgr, hwmgr->display_config.min_dcef_deep_sleep_set_clk);
269
+
hwmgr->hwmgr_func->set_deep_sleep_dcefclk(hwmgr, display_config->min_dcef_deep_sleep_set_clk);
272
270
273
-
for (index = 0; index < hwmgr->display_config.num_path_including_non_display; index++) {
274
-
if (hwmgr->display_config.displays[index].controller_id != 0)
271
+
for (index = 0; index < display_config->num_path_including_non_display; index++) {
272
+
if (display_config->displays[index].controller_id != 0)
275
273
number_of_active_display++;
276
274
}
277
275
+1
-1
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+1
-1
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
···
161
161
struct PP_Clocks clocks = {0};
162
162
struct pp_display_clock_request clock_req;
163
163
164
-
clocks.dcefClock = hwmgr->display_config.min_dcef_set_clk;
164
+
clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
165
165
clock_req.clock_type = amd_pp_dcf_clock;
166
166
clock_req.clock_freq_in_khz = clocks.dcefClock * 10;
167
167
+15
-41
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+15
-41
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
···
2777
2777
struct PP_Clocks minimum_clocks = {0};
2778
2778
bool disable_mclk_switching;
2779
2779
bool disable_mclk_switching_for_frame_lock;
2780
-
struct cgs_display_info info = {0};
2781
-
struct cgs_mode_info mode_info = {0};
2782
2780
const struct phm_clock_and_voltage_limits *max_limits;
2783
2781
uint32_t i;
2784
2782
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
···
2785
2787
int32_t count;
2786
2788
int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
2787
2789
2788
-
info.mode_info = &mode_info;
2789
2790
data->battery_state = (PP_StateUILabel_Battery ==
2790
2791
request_ps->classification.ui_label);
2791
2792
···
2806
2809
}
2807
2810
}
2808
2811
2809
-
cgs_get_active_displays_info(hwmgr->device, &info);
2810
-
2811
-
minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock;
2812
-
minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock;
2812
+
minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock;
2813
+
minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
2813
2814
2814
2815
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2815
2816
PHM_PlatformCaps_StablePState)) {
···
2838
2843
PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
2839
2844
2840
2845
2841
-
if (info.display_count == 0)
2846
+
if (hwmgr->display_config->num_display == 0)
2842
2847
disable_mclk_switching = false;
2843
2848
else
2844
-
disable_mclk_switching = ((1 < info.display_count) ||
2849
+
disable_mclk_switching = ((1 < hwmgr->display_config->num_display) ||
2845
2850
disable_mclk_switching_for_frame_lock ||
2846
-
smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us));
2851
+
smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time));
2847
2852
2848
2853
sclk = smu7_ps->performance_levels[0].engine_clock;
2849
2854
mclk = smu7_ps->performance_levels[0].memory_clock;
···
3474
3479
[smu7_ps->performance_level_count - 1].memory_clock;
3475
3480
struct PP_Clocks min_clocks = {0};
3476
3481
uint32_t i;
3477
-
struct cgs_display_info info = {0};
3478
3482
3479
3483
for (i = 0; i < sclk_table->count; i++) {
3480
3484
if (sclk == sclk_table->dpm_levels[i].value)
···
3500
3506
if (i >= mclk_table->count)
3501
3507
data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3502
3508
3503
-
cgs_get_active_displays_info(hwmgr->device, &info);
3504
3509
3505
-
if (data->display_timing.num_existing_displays != info.display_count)
3510
+
if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
3506
3511
data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3507
3512
3508
3513
return 0;
···
3900
3907
static int
3901
3908
smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
3902
3909
{
3903
-
uint32_t num_active_displays = 0;
3904
-
struct cgs_display_info info = {0};
3905
-
3906
-
info.mode_info = NULL;
3907
-
cgs_get_active_displays_info(hwmgr->device, &info);
3908
-
3909
-
num_active_displays = info.display_count;
3910
-
3911
-
if (num_active_displays > 1 && hwmgr->display_config.multi_monitor_in_sync != true)
3910
+
if (hwmgr->display_config->num_display > 1 &&
3911
+
!hwmgr->display_config->multi_monitor_in_sync)
3912
3912
smu7_notify_smc_display_change(hwmgr, false);
3913
3913
3914
3914
return 0;
···
3916
3930
static int smu7_program_display_gap(struct pp_hwmgr *hwmgr)
3917
3931
{
3918
3932
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3919
-
uint32_t num_active_displays = 0;
3920
3933
uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
3921
3934
uint32_t display_gap2;
3922
3935
uint32_t pre_vbi_time_in_us;
3923
3936
uint32_t frame_time_in_us;
3924
-
uint32_t ref_clock;
3925
-
uint32_t refresh_rate = 0;
3926
-
struct cgs_display_info info = {0};
3927
-
struct cgs_mode_info mode_info = {0};
3937
+
uint32_t ref_clock, refresh_rate;
3928
3938
3929
-
info.mode_info = &mode_info;
3930
-
cgs_get_active_displays_info(hwmgr->device, &info);
3931
-
num_active_displays = info.display_count;
3932
-
3933
-
display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
3939
+
display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (hwmgr->display_config->num_display > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
3934
3940
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
3935
3941
3936
3942
ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
3937
-
3938
-
refresh_rate = mode_info.refresh_rate;
3943
+
refresh_rate = hwmgr->display_config->vrefresh;
3939
3944
3940
3945
if (0 == refresh_rate)
3941
3946
refresh_rate = 60;
3942
3947
3943
3948
frame_time_in_us = 1000000 / refresh_rate;
3944
3949
3945
-
pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
3950
+
pre_vbi_time_in_us = frame_time_in_us - 200 - hwmgr->display_config->min_vblank_time;
3946
3951
3947
3952
data->frame_time_x2 = frame_time_in_us * 2 / 100;
3948
3953
···
4013
4036
{
4014
4037
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4015
4038
bool is_update_required = false;
4016
-
struct cgs_display_info info = {0, 0, NULL};
4017
4039
4018
-
cgs_get_active_displays_info(hwmgr->device, &info);
4019
-
4020
-
if (data->display_timing.num_existing_displays != info.display_count)
4040
+
if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
4021
4041
is_update_required = true;
4022
4042
4023
4043
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
4024
-
if (data->display_timing.min_clock_in_sr != hwmgr->display_config.min_core_set_clock_in_sr &&
4044
+
if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr &&
4025
4045
(data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK ||
4026
-
hwmgr->display_config.min_core_set_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK))
4046
+
hwmgr->display_config->min_core_set_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK))
4027
4047
is_update_required = true;
4028
4048
}
4029
4049
return is_update_required;
+5
-9
drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
+5
-9
drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
···
693
693
else
694
694
data->sclk_dpm.soft_max_clk = table->entries[table->count - 1].clk;
695
695
696
-
clock = hwmgr->display_config.min_core_set_clock;
696
+
clock = hwmgr->display_config->min_core_set_clock;
697
697
if (clock == 0)
698
698
pr_debug("min_core_set_clock not set\n");
699
699
···
748
748
{
749
749
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
750
750
PHM_PlatformCaps_SclkDeepSleep)) {
751
-
uint32_t clks = hwmgr->display_config.min_core_set_clock_in_sr;
751
+
uint32_t clks = hwmgr->display_config->min_core_set_clock_in_sr;
752
752
if (clks == 0)
753
753
clks = SMU8_MIN_DEEP_SLEEP_SCLK;
754
754
···
1040
1040
struct smu8_hwmgr *data = hwmgr->backend;
1041
1041
struct PP_Clocks clocks = {0, 0, 0, 0};
1042
1042
bool force_high;
1043
-
uint32_t num_of_active_displays = 0;
1044
-
struct cgs_display_info info = {0};
1045
1043
1046
1044
smu8_ps->need_dfs_bypass = true;
1047
1045
1048
1046
data->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
1049
1047
1050
-
clocks.memoryClock = hwmgr->display_config.min_mem_set_clock != 0 ?
1051
-
hwmgr->display_config.min_mem_set_clock :
1048
+
clocks.memoryClock = hwmgr->display_config->min_mem_set_clock != 0 ?
1049
+
hwmgr->display_config->min_mem_set_clock :
1052
1050
data->sys_info.nbp_memory_clock[1];
1053
1051
1054
-
cgs_get_active_displays_info(hwmgr->device, &info);
1055
-
num_of_active_displays = info.display_count;
1056
1052
1057
1053
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
1058
1054
clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk;
1059
1055
1060
1056
force_high = (clocks.memoryClock > data->sys_info.nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK - 1])
1061
-
|| (num_of_active_displays >= 3);
1057
+
|| (hwmgr->display_config->num_display >= 3);
1062
1058
1063
1059
smu8_ps->action = smu8_current_ps->action;
1064
1060
+14
-37
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+14
-37
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
···
3028
3028
bool disable_mclk_switching_for_frame_lock;
3029
3029
bool disable_mclk_switching_for_vr;
3030
3030
bool force_mclk_high;
3031
-
struct cgs_display_info info = {0};
3032
3031
const struct phm_clock_and_voltage_limits *max_limits;
3033
3032
uint32_t i;
3034
3033
struct vega10_hwmgr *data = hwmgr->backend;
···
3062
3063
}
3063
3064
}
3064
3065
3065
-
cgs_get_active_displays_info(hwmgr->device, &info);
3066
-
3067
3066
/* result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3068
-
minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock;
3069
-
minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock;
3067
+
minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock;
3068
+
minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
3070
3069
3071
3070
if (PP_CAP(PHM_PlatformCaps_StablePState)) {
3072
3071
stable_pstate_sclk_dpm_percentage =
···
3104
3107
PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR);
3105
3108
force_mclk_high = PP_CAP(PHM_PlatformCaps_ForceMclkHigh);
3106
3109
3107
-
if (info.display_count == 0)
3110
+
if (hwmgr->display_config->num_display == 0)
3108
3111
disable_mclk_switching = false;
3109
3112
else
3110
-
disable_mclk_switching = (info.display_count > 1) ||
3113
+
disable_mclk_switching = (hwmgr->display_config->num_display > 1) ||
3111
3114
disable_mclk_switching_for_frame_lock ||
3112
3115
disable_mclk_switching_for_vr ||
3113
3116
force_mclk_high;
···
3183
3186
[vega10_ps->performance_level_count - 1].mem_clock;
3184
3187
struct PP_Clocks min_clocks = {0};
3185
3188
uint32_t i;
3186
-
struct cgs_display_info info = {0};
3187
3189
3188
3190
data->need_update_dpm_table = 0;
3189
3191
···
3207
3211
data->need_update_dpm_table |= DPMTABLE_UPDATE_SCLK;
3208
3212
}
3209
3213
3210
-
cgs_get_active_displays_info(hwmgr->device, &info);
3211
-
3212
3214
if (data->display_timing.num_existing_displays !=
3213
-
info.display_count)
3215
+
hwmgr->display_config->num_display)
3214
3216
data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK;
3215
3217
} else {
3216
3218
for (i = 0; i < sclk_table->count; i++) {
···
3236
3242
break;
3237
3243
}
3238
3244
3239
-
cgs_get_active_displays_info(hwmgr->device, &info);
3240
-
3241
3245
if (i >= mclk_table->count)
3242
3246
data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3243
3247
3244
3248
if (data->display_timing.num_existing_displays !=
3245
-
info.display_count ||
3249
+
hwmgr->display_config->num_display ||
3246
3250
i >= mclk_table->count)
3247
3251
data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK;
3248
3252
}
···
3948
3956
(struct phm_ppt_v2_information *)hwmgr->pptable;
3949
3957
struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = table_info->vdd_dep_on_mclk;
3950
3958
uint32_t idx;
3951
-
uint32_t num_active_disps = 0;
3952
-
struct cgs_display_info info = {0};
3953
3959
struct PP_Clocks min_clocks = {0};
3954
3960
uint32_t i;
3955
3961
struct pp_display_clock_request clock_req;
3956
3962
3957
-
info.mode_info = NULL;
3958
-
3959
-
cgs_get_active_displays_info(hwmgr->device, &info);
3960
-
3961
-
num_active_disps = info.display_count;
3962
-
3963
-
if (num_active_disps > 1)
3963
+
if (hwmgr->display_config->num_display > 1)
3964
3964
vega10_notify_smc_display_change(hwmgr, false);
3965
3965
else
3966
3966
vega10_notify_smc_display_change(hwmgr, true);
3967
3967
3968
-
min_clocks.dcefClock = hwmgr->display_config.min_dcef_set_clk;
3969
-
min_clocks.dcefClockInSR = hwmgr->display_config.min_dcef_deep_sleep_set_clk;
3970
-
min_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock;
3968
+
min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
3969
+
min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
3970
+
min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
3971
3971
3972
3972
for (i = 0; i < dpm_table->count; i++) {
3973
3973
if (dpm_table->dpm_levels[i].value == min_clocks.dcefClock)
···
4485
4501
static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4486
4502
{
4487
4503
struct vega10_hwmgr *data = hwmgr->backend;
4488
-
int result = 0;
4489
-
uint32_t num_turned_on_displays = 1;
4490
4504
Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
4491
-
struct cgs_display_info info = {0};
4505
+
int result = 0;
4492
4506
4493
4507
if ((data->water_marks_bitmap & WaterMarksExist) &&
4494
4508
!(data->water_marks_bitmap & WaterMarksLoaded)) {
···
4496
4514
}
4497
4515
4498
4516
if (data->water_marks_bitmap & WaterMarksLoaded) {
4499
-
cgs_get_active_displays_info(hwmgr->device, &info);
4500
-
num_turned_on_displays = info.display_count;
4501
4517
smum_send_msg_to_smc_with_parameter(hwmgr,
4502
-
PPSMC_MSG_NumOfDisplays, num_turned_on_displays);
4518
+
PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display);
4503
4519
}
4504
4520
4505
4521
return result;
···
4583
4603
{
4584
4604
struct vega10_hwmgr *data = hwmgr->backend;
4585
4605
bool is_update_required = false;
4586
-
struct cgs_display_info info = {0, 0, NULL};
4587
4606
4588
-
cgs_get_active_displays_info(hwmgr->device, &info);
4589
-
4590
-
if (data->display_timing.num_existing_displays != info.display_count)
4607
+
if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
4591
4608
is_update_required = true;
4592
4609
4593
4610
if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep)) {
4594
-
if (data->display_timing.min_clock_in_sr != hwmgr->display_config.min_core_set_clock_in_sr)
4611
+
if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr)
4595
4612
is_update_required = true;
4596
4613
}
4597
4614
+8
-21
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+8
-21
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
···
1260
1260
{
1261
1261
struct vega12_hwmgr *data =
1262
1262
(struct vega12_hwmgr *)(hwmgr->backend);
1263
-
uint32_t num_active_disps = 0;
1264
-
struct cgs_display_info info = {0};
1265
1263
struct PP_Clocks min_clocks = {0};
1266
1264
struct pp_display_clock_request clock_req;
1267
1265
uint32_t clk_request;
1268
1266
1269
-
info.mode_info = NULL;
1270
-
cgs_get_active_displays_info(hwmgr->device, &info);
1271
-
num_active_disps = info.display_count;
1272
-
if (num_active_disps > 1)
1267
+
if (hwmgr->display_config->num_display > 1)
1273
1268
vega12_notify_smc_display_change(hwmgr, false);
1274
1269
else
1275
1270
vega12_notify_smc_display_change(hwmgr, true);
1276
1271
1277
-
min_clocks.dcefClock = hwmgr->display_config.min_dcef_set_clk;
1278
-
min_clocks.dcefClockInSR = hwmgr->display_config.min_dcef_deep_sleep_set_clk;
1279
-
min_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock;
1272
+
min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
1273
+
min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
1274
+
min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
1280
1275
1281
1276
if (data->smu_features[GNLD_DPM_DCEFCLK].supported) {
1282
1277
clock_req.clock_type = amd_pp_dcef_clock;
···
1827
1832
{
1828
1833
struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1829
1834
int result = 0;
1830
-
uint32_t num_turned_on_displays = 1;
1831
1835
Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
1832
-
struct cgs_display_info info = {0};
1833
1836
1834
1837
if ((data->water_marks_bitmap & WaterMarksExist) &&
1835
1838
!(data->water_marks_bitmap & WaterMarksLoaded)) {
···
1839
1846
1840
1847
if ((data->water_marks_bitmap & WaterMarksExist) &&
1841
1848
data->smu_features[GNLD_DPM_DCEFCLK].supported &&
1842
-
data->smu_features[GNLD_DPM_SOCCLK].supported) {
1843
-
cgs_get_active_displays_info(hwmgr->device, &info);
1844
-
num_turned_on_displays = info.display_count;
1849
+
data->smu_features[GNLD_DPM_SOCCLK].supported)
1845
1850
smum_send_msg_to_smc_with_parameter(hwmgr,
1846
-
PPSMC_MSG_NumOfDisplays, num_turned_on_displays);
1847
-
}
1851
+
PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display);
1848
1852
1849
1853
return result;
1850
1854
}
···
1884
1894
{
1885
1895
struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1886
1896
bool is_update_required = false;
1887
-
struct cgs_display_info info = {0, 0, NULL};
1888
1897
1889
-
cgs_get_active_displays_info(hwmgr->device, &info);
1890
-
1891
-
if (data->display_timing.num_existing_displays != info.display_count)
1898
+
if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
1892
1899
is_update_required = true;
1893
1900
1894
1901
if (data->registry_data.gfx_clk_deep_sleep_support) {
1895
-
if (data->display_timing.min_clock_in_sr != hwmgr->display_config.min_core_set_clock_in_sr)
1902
+
if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr)
1896
1903
is_update_required = true;
1897
1904
}
1898
1905
+1
-1
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+1
-1
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
···
765
765
struct pp_power_state *request_ps;
766
766
struct pp_power_state *boot_ps;
767
767
struct pp_power_state *uvd_ps;
768
-
struct amd_pp_display_configuration display_config;
768
+
const struct amd_pp_display_configuration *display_config;
769
769
uint32_t feature_mask;
770
770
bool avfs_supported;
771
771
/* UMD Pstate */
+1
-3
drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
+1
-3
drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
···
1182
1182
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1183
1183
int result = 0;
1184
1184
bool dll_state_on;
1185
-
struct cgs_display_info info = {0};
1186
1185
uint32_t mclk_edc_wr_enable_threshold = 40000;
1187
1186
uint32_t mclk_edc_enable_threshold = 40000;
1188
1187
uint32_t mclk_strobe_mode_threshold = 40000;
···
1235
1236
/* default set to low watermark. Highest level will be set to high later.*/
1236
1237
memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1237
1238
1238
-
cgs_get_active_displays_info(hwmgr->device, &info);
1239
-
data->display_timing.num_existing_displays = info.display_count;
1239
+
data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1240
1240
1241
1241
/* stutter mode not support on ci */
1242
1242
+2
-2
drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+2
-2
drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
···
988
988
989
989
threshold = clock * data->fast_watermark_threshold / 100;
990
990
991
-
data->display_timing.min_clock_in_sr = hwmgr->display_config.min_core_set_clock_in_sr;
991
+
data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
992
992
993
993
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
994
994
level->DeepSleepDivId = smu7_get_sleep_divider_id_from_clock(clock,
995
-
hwmgr->display_config.min_core_set_clock_in_sr);
995
+
hwmgr->display_config->min_core_set_clock_in_sr);
996
996
997
997
998
998
/* Default to slow, highest DPM level will be
+2
-4
drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
+2
-4
drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
···
932
932
graphic_level->PowerThrottle = 0;
933
933
934
934
data->display_timing.min_clock_in_sr =
935
-
hwmgr->display_config.min_core_set_clock_in_sr;
935
+
hwmgr->display_config->min_core_set_clock_in_sr;
936
936
937
937
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
938
938
PHM_PlatformCaps_SclkDeepSleep))
···
1236
1236
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1237
1237
int result = 0;
1238
1238
bool dll_state_on;
1239
-
struct cgs_display_info info = {0};
1240
1239
uint32_t mclk_edc_wr_enable_threshold = 40000;
1241
1240
uint32_t mclk_edc_enable_threshold = 40000;
1242
1241
uint32_t mclk_strobe_mode_threshold = 40000;
···
1282
1283
/* default set to low watermark. Highest level will be set to high later.*/
1283
1284
memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1284
1285
1285
-
cgs_get_active_displays_info(hwmgr->device, &info);
1286
-
data->display_timing.num_existing_displays = info.display_count;
1286
+
data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1287
1287
1288
1288
/* stutter mode not support on iceland */
1289
1289
+3
-5
drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+3
-5
drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
···
942
942
level->DownHyst = data->current_profile_setting.sclk_down_hyst;
943
943
level->VoltageDownHyst = 0;
944
944
level->PowerThrottle = 0;
945
-
data->display_timing.min_clock_in_sr = hwmgr->display_config.min_core_set_clock_in_sr;
945
+
data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
946
946
947
947
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
948
948
level->DeepSleepDivId = smu7_get_sleep_divider_id_from_clock(clock,
949
-
hwmgr->display_config.min_core_set_clock_in_sr);
949
+
hwmgr->display_config->min_core_set_clock_in_sr);
950
950
951
951
/* Default to slow, highest DPM level will be
952
952
* set to PPSMC_DISPLAY_WATERMARK_LOW later.
···
1076
1076
struct phm_ppt_v1_information *table_info =
1077
1077
(struct phm_ppt_v1_information *)(hwmgr->pptable);
1078
1078
int result = 0;
1079
-
struct cgs_display_info info = {0, 0, NULL};
1080
1079
uint32_t mclk_stutter_mode_threshold = 40000;
1081
1080
phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
1082
1081
1083
-
cgs_get_active_displays_info(hwmgr->device, &info);
1084
1082
1085
1083
if (hwmgr->od_enabled)
1086
1084
vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_mclk;
···
1104
1106
mem_level->StutterEnable = false;
1105
1107
mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1106
1108
1107
-
data->display_timing.num_existing_displays = info.display_count;
1109
+
data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1108
1110
1109
1111
if (mclk_stutter_mode_threshold &&
1110
1112
(clock <= mclk_stutter_mode_threshold) &&
+5
-7
drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
+5
-7
drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
···
650
650
graphic_level->PowerThrottle = 0;
651
651
652
652
data->display_timing.min_clock_in_sr =
653
-
hwmgr->display_config.min_core_set_clock_in_sr;
653
+
hwmgr->display_config->min_core_set_clock_in_sr;
654
654
655
655
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
656
656
PHM_PlatformCaps_SclkDeepSleep))
···
956
956
SMU72_Discrete_MemoryLevel *memory_level
957
957
)
958
958
{
959
-
uint32_t mvdd = 0;
960
959
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
961
960
struct phm_ppt_v1_information *pptable_info =
962
961
(struct phm_ppt_v1_information *)(hwmgr->pptable);
963
-
int result = 0;
964
-
bool dll_state_on;
965
-
struct cgs_display_info info = {0};
966
962
uint32_t mclk_edc_wr_enable_threshold = 40000;
967
963
uint32_t mclk_stutter_mode_threshold = 30000;
968
964
uint32_t mclk_edc_enable_threshold = 40000;
969
965
uint32_t mclk_strobe_mode_threshold = 40000;
970
966
phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
967
+
int result = 0;
968
+
bool dll_state_on;
969
+
uint32_t mvdd = 0;
971
970
972
971
if (hwmgr->od_enabled)
973
972
vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_mclk;
···
1007
1008
/* default set to low watermark. Highest level will be set to high later.*/
1008
1009
memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1009
1010
1010
-
cgs_get_active_displays_info(hwmgr->device, &info);
1011
-
data->display_timing.num_existing_displays = info.display_count;
1011
+
data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1012
1012
1013
1013
if ((mclk_stutter_mode_threshold != 0) &&
1014
1014
(memory_clock <= mclk_stutter_mode_threshold) &&