Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
arm64: zynqmp: Setup clock for DP and DPDMA
Clocks are coming from shared HW design where these frequencies should be
aligned with PLL setup.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/807e22371394222f728ff7d6b190a96a12145439.1683034376.git.michal.simek@amd.com
+8
+4
arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
+4
arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
···
248
248
249
249
&zynqmp_dpdma {
250
250
clocks = <&zynqmp_clk DPDMA_REF>;
251
+
assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */
251
252
};
252
253
253
254
&zynqmp_dpsub {
254
255
clocks = <&zynqmp_clk TOPSW_LSBUS>,
255
256
<&zynqmp_clk DP_AUDIO_REF>,
256
257
<&zynqmp_clk DP_VIDEO_REF>;
258
+
assigned-clocks = <&zynqmp_clk DP_STC_REF>,
259
+
<&zynqmp_clk DP_AUDIO_REF>,
260
+
<&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */
257
261
};
+2
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
+2
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
···
98
98
status = "disabled";
99
99
phy-names = "dp-phy0", "dp-phy1";
100
100
phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
101
+
assigned-clock-rates = <27000000>, <25000000>, <300000000>;
101
102
};
102
103
103
104
&zynqmp_dpdma {
104
105
status = "okay";
106
+
assigned-clock-rates = <600000000>;
105
107
};
106
108
107
109
&usb0 {
+2
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
+2
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
···
79
79
status = "disabled";
80
80
phy-names = "dp-phy0", "dp-phy1";
81
81
phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
82
+
assigned-clock-rates = <27000000>, <25000000>, <300000000>;
82
83
};
83
84
84
85
&zynqmp_dpdma {
85
86
status = "okay";
87
+
assigned-clock-rates = <600000000>;
86
88
};
87
89
88
90
&usb0 {