Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/a6xx: Fix gpucc register block for A621
Adreno 621 has a different memory map for GPUCC block. So update
a6xx_gpu_state code to dump the correct set of gpucc registers.
Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com>
Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/640055/
Signed-off-by: Rob Clark <robdclark@chromium.org>
+19
-2
+7
-2
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
+7
-2
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
···
1226
1226
&a6xx_state->gmu_registers[0], false);
1227
1227
_a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[1],
1228
1228
&a6xx_state->gmu_registers[1], true);
1229
-
_a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gpucc_reg,
1230
-
&a6xx_state->gmu_registers[2], false);
1229
+
1230
+
if (adreno_is_a621(adreno_gpu))
1231
+
_a6xx_get_gmu_registers(gpu, a6xx_state, &a621_gpucc_reg,
1232
+
&a6xx_state->gmu_registers[2], false);
1233
+
else
1234
+
_a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gpucc_reg,
1235
+
&a6xx_state->gmu_registers[2], false);
1231
1236
1232
1237
if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu))
1233
1238
return;
+12
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
+12
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
···
376
376
0xbc00, 0xbc16, 0xbc20, 0xbc27,
377
377
};
378
378
379
+
static const u32 a621_gmu_gpucc_registers[] = {
380
+
/* GPU CC */
381
+
0x9800, 0x980e, 0x9c00, 0x9c0e, 0xb000, 0xb004, 0xb400, 0xb404,
382
+
0xb800, 0xb804, 0xbc00, 0xbc05, 0xbc14, 0xbc1d, 0xbc2a, 0xbc30,
383
+
0xbc32, 0xbc32, 0xbc41, 0xbc55, 0xbc66, 0xbc68, 0xbc78, 0xbc7a,
384
+
0xbc89, 0xbc8a, 0xbc9c, 0xbc9e, 0xbca0, 0xbca3, 0xbcb3, 0xbcb5,
385
+
0xbcc5, 0xbcc7, 0xbcd6, 0xbcd8, 0xbce8, 0xbce9, 0xbcf9, 0xbcfc,
386
+
0xbd0b, 0xbd0c, 0xbd1c, 0xbd1e, 0xbd40, 0xbd70, 0xbe00, 0xbe16,
387
+
0xbe20, 0xbe2d,
388
+
};
389
+
379
390
static const u32 a6xx_gmu_cx_rscc_registers[] = {
380
391
/* GPU RSCC */
381
392
0x008c, 0x008c, 0x0101, 0x0102, 0x0340, 0x0342, 0x0344, 0x0347,
···
401
390
};
402
391
403
392
static const struct a6xx_registers a6xx_gpucc_reg = REGS(a6xx_gmu_gpucc_registers, 0, 0);
393
+
static const struct a6xx_registers a621_gpucc_reg = REGS(a621_gmu_gpucc_registers, 0, 0);
404
394
405
395
static u32 a6xx_get_cp_roq_size(struct msm_gpu *gpu);
406
396
static u32 a7xx_get_cp_roq_size(struct msm_gpu *gpu);