drm/i915/ltphy: Program LT Phy Voltage Swing

+10 -3

drivers/gpu/drm/i915/display/intel_ddi.c

··· 1467 1467 u8 signal_levels) 1468 1468 { 1469 1469 struct intel_display *display = to_intel_display(intel_dp); 1470 + const u8 *signal_array; 1471 + size_t array_size; 1470 1472 int i; 1471 1473 1472 - for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1473 - if (index_to_dp_signal_levels[i] == signal_levels) 1474 + signal_array = index_to_dp_signal_levels; 1475 + array_size = ARRAY_SIZE(index_to_dp_signal_levels); 1476 + 1477 + for (i = 0; i < array_size; i++) { 1478 + if (signal_array[i] == signal_levels) 1474 1479 return i; 1475 1480 } 1476 1481 ··· 5306 5301 encoder->get_config = hsw_ddi_get_config; 5307 5302 } 5308 5303 5309 - if (DISPLAY_VER(display) >= 14) { 5304 + if (HAS_LT_PHY(display)) { 5305 + encoder->set_signal_levels = intel_lt_phy_set_signal_levels; 5306 + } else if (DISPLAY_VER(display) >= 14) { 5310 5307 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; 5311 5308 } else if (display->platform.dg2) { 5312 5309 encoder->set_signal_levels = intel_snps_phy_set_signal_levels;

+63

drivers/gpu/drm/i915/display/intel_lt_phy.c

··· 9 9 #include "i915_utils.h" 10 10 #include "intel_cx0_phy.h" 11 11 #include "intel_cx0_phy_regs.h" 12 + #include "intel_ddi.h" 13 + #include "intel_ddi_buf_trans.h" 12 14 #include "intel_de.h" 13 15 #include "intel_display.h" 14 16 #include "intel_display_types.h" ··· 1005 1003 intel_cx0_write(encoder, lane_mask, addr, data, committed); 1006 1004 } 1007 1005 1006 + static void intel_lt_phy_rmw(struct intel_encoder *encoder, 1007 + u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed) 1008 + { 1009 + intel_cx0_rmw(encoder, lane_mask, addr, clear, set, committed); 1010 + } 1011 + 1008 1012 static void intel_lt_phy_clear_status_p2p(struct intel_encoder *encoder, 1009 1013 int lane) 1010 1014 { ··· 1710 1702 /* 11. Program PORT_BUF_CTL5[MacCLK Reset_0] = 1 to assert MacCLK reset. */ 1711 1703 intel_de_rmw(display, XE3PLPD_PORT_BUF_CTL5(port), 1712 1704 XE3PLPD_MACCLK_RESET_0, XE3PLPD_MACCLK_RESET_0); 1705 + 1706 + intel_lt_phy_transaction_end(encoder, wakeref); 1707 + } 1708 + 1709 + void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder, 1710 + const struct intel_crtc_state *crtc_state) 1711 + { 1712 + struct intel_display *display = to_intel_display(encoder); 1713 + const struct intel_ddi_buf_trans *trans; 1714 + u8 owned_lane_mask; 1715 + intel_wakeref_t wakeref; 1716 + int n_entries, ln; 1717 + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1718 + 1719 + if (intel_tc_port_in_tbt_alt_mode(dig_port)) 1720 + return; 1721 + 1722 + owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder); 1723 + 1724 + wakeref = intel_lt_phy_transaction_begin(encoder); 1725 + 1726 + trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1727 + if (drm_WARN_ON_ONCE(display->drm, !trans)) { 1728 + intel_lt_phy_transaction_end(encoder, wakeref); 1729 + return; 1730 + } 1731 + 1732 + for (ln = 0; ln < crtc_state->lane_count; ln++) { 1733 + int level = intel_ddi_level(encoder, crtc_state, ln); 1734 + int lane = ln / 2; 1735 + int tx = ln % 2; 1736 + u8 lane_mask = lane == 0 ? INTEL_LT_PHY_LANE0 : INTEL_LT_PHY_LANE1; 1737 + 1738 + if (!(lane_mask & owned_lane_mask)) 1739 + continue; 1740 + 1741 + intel_lt_phy_rmw(encoder, lane_mask, LT_PHY_TXY_CTL8(tx), 1742 + LT_PHY_TX_SWING_LEVEL_MASK | LT_PHY_TX_SWING_MASK, 1743 + LT_PHY_TX_SWING_LEVEL(trans->entries[level].lt.txswing_level) | 1744 + LT_PHY_TX_SWING(trans->entries[level].lt.txswing), 1745 + MB_WRITE_COMMITTED); 1746 + 1747 + intel_lt_phy_rmw(encoder, lane_mask, LT_PHY_TXY_CTL2(tx), 1748 + LT_PHY_TX_CURSOR_MASK, 1749 + LT_PHY_TX_CURSOR(trans->entries[level].lt.pre_cursor), 1750 + MB_WRITE_COMMITTED); 1751 + intel_lt_phy_rmw(encoder, lane_mask, LT_PHY_TXY_CTL3(tx), 1752 + LT_PHY_TX_CURSOR_MASK, 1753 + LT_PHY_TX_CURSOR(trans->entries[level].lt.main_cursor), 1754 + MB_WRITE_COMMITTED); 1755 + intel_lt_phy_rmw(encoder, lane_mask, LT_PHY_TXY_CTL4(tx), 1756 + LT_PHY_TX_CURSOR_MASK, 1757 + LT_PHY_TX_CURSOR(trans->entries[level].lt.post_cursor), 1758 + MB_WRITE_COMMITTED); 1759 + } 1713 1760 1714 1761 intel_lt_phy_transaction_end(encoder, wakeref); 1715 1762 }

+2

drivers/gpu/drm/i915/display/intel_lt_phy.h

··· 20 20 struct intel_encoder *encoder); 21 21 int intel_lt_phy_calc_port_clock(struct intel_encoder *encoder, 22 22 const struct intel_crtc_state *crtc_state); 23 + void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder, 24 + const struct intel_crtc_state *crtc_state); 23 25 void intel_xe3plpd_pll_enable(struct intel_encoder *encoder, 24 26 const struct intel_crtc_state *crtc_state); 25 27 void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);

+13

drivers/gpu/drm/i915/display/intel_lt_phy_regs.h

··· 19 19 #define LT_PHY_MAC_VDR _MMIO(0xC00) 20 20 #define LT_PHY_PCLKIN_GATE REG_BIT8(0) 21 21 22 + /* LT Phy Pipe Spec Registers */ 23 + #define LT_PHY_TXY_CTL8(idx) (0x408 + (0x200 * (idx))) 24 + #define LT_PHY_TX_SWING_LEVEL_MASK REG_GENMASK8(7, 4) 25 + #define LT_PHY_TX_SWING_LEVEL(val) REG_FIELD_PREP8(LT_PHY_TX_SWING_LEVEL_MASK, val) 26 + #define LT_PHY_TX_SWING_MASK REG_BIT8(3) 27 + #define LT_PHY_TX_SWING(val) REG_FIELD_PREP8(LT_PHY_TX_SWING_MASK, val) 28 + 29 + #define LT_PHY_TXY_CTL2(idx) (0x402 + (0x200 * (idx))) 30 + #define LT_PHY_TXY_CTL3(idx) (0x403 + (0x200 * (idx))) 31 + #define LT_PHY_TXY_CTL4(idx) (0x404 + (0x200 * (idx))) 32 + #define LT_PHY_TX_CURSOR_MASK REG_GENMASK8(5, 0) 33 + #define LT_PHY_TX_CURSOR(val) REG_FIELD_PREP8(LT_PHY_TX_CURSOR_MASK, val) 34 + 22 35 /* LT Phy Vendor Register */ 23 36 #define LT_PHY_VDR_0_CONFIG 0xC02 24 37 #define LT_PHY_VDR_DP_PLL_ENABLE REG_BIT(7)

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