Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/ddi: Define LT Phy Swing tables
Define and initialize LT Phy Swing tables for DP 1.4, 2.1 and eDp.
HDMI TMDS is not needed since LT Phy H/w handles that.
Bspec: 74493
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-19-suraj.kandpal@intel.com
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drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
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drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
···
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#include "intel_display_types.h"
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#include "intel_display_utils.h"
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#include "intel_dp.h"
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#include "intel_lt_phy.h"
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/* HDMI/DVI modes ignore everything but the last 2 items. So we share
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* them for both DP and FDI transports, allowing those ports to
···
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.num_entries = ARRAY_SIZE(_mtl_c20_trans_uhbr),
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};
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/* DP1.4 */
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static const union intel_ddi_buf_trans_entry _xe3plpd_lt_trans_dp14[] = {
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{ .lt = { 1, 0, 0, 21, 0 } },
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{ .lt = { 1, 1, 0, 24, 3 } },
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{ .lt = { 1, 2, 0, 28, 7 } },
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{ .lt = { 0, 3, 0, 35, 13 } },
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{ .lt = { 1, 1, 0, 27, 0 } },
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{ .lt = { 1, 2, 0, 31, 4 } },
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{ .lt = { 0, 3, 0, 39, 9 } },
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{ .lt = { 1, 2, 0, 35, 0 } },
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{ .lt = { 0, 3, 0, 41, 7 } },
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{ .lt = { 0, 3, 0, 48, 0 } },
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};
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/* DP2.1 */
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static const union intel_ddi_buf_trans_entry _xe3plpd_lt_trans_uhbr[] = {
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{ .lt = { 0, 0, 0, 48, 0 } },
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{ .lt = { 0, 0, 0, 43, 5 } },
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{ .lt = { 0, 0, 0, 40, 8 } },
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{ .lt = { 0, 0, 0, 37, 11 } },
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{ .lt = { 0, 0, 0, 33, 15 } },
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{ .lt = { 0, 0, 2, 46, 0 } },
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{ .lt = { 0, 0, 2, 42, 4 } },
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{ .lt = { 0, 0, 2, 38, 8 } },
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{ .lt = { 0, 0, 2, 35, 11 } },
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{ .lt = { 0, 0, 2, 33, 13 } },
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{ .lt = { 0, 0, 4, 44, 0 } },
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{ .lt = { 0, 0, 4, 40, 4 } },
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{ .lt = { 0, 0, 4, 37, 7 } },
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{ .lt = { 0, 0, 4, 33, 11 } },
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{ .lt = { 0, 0, 8, 40, 0 } },
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{ .lt = { 1, 0, 2, 26, 2 } },
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};
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/* eDp */
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static const union intel_ddi_buf_trans_entry _xe3plpd_lt_trans_edp[] = {
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{ .lt = { 1, 0, 0, 12, 0 } },
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{ .lt = { 1, 1, 0, 13, 1 } },
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{ .lt = { 1, 2, 0, 15, 3 } },
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{ .lt = { 1, 3, 0, 19, 7 } },
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{ .lt = { 1, 1, 0, 14, 0 } },
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{ .lt = { 1, 2, 0, 16, 2 } },
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{ .lt = { 1, 3, 0, 21, 5 } },
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{ .lt = { 1, 2, 0, 18, 0 } },
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{ .lt = { 1, 3, 0, 22, 4 } },
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{ .lt = { 1, 3, 0, 26, 0 } },
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};
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static const struct intel_ddi_buf_trans xe3plpd_lt_trans_dp14 = {
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.entries = _xe3plpd_lt_trans_dp14,
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.num_entries = ARRAY_SIZE(_xe3plpd_lt_trans_dp14),
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};
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static const struct intel_ddi_buf_trans xe3plpd_lt_trans_uhbr = {
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.entries = _xe3plpd_lt_trans_uhbr,
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.num_entries = ARRAY_SIZE(_xe3plpd_lt_trans_uhbr),
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};
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static const struct intel_ddi_buf_trans xe3plpd_lt_trans_edp = {
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.entries = _xe3plpd_lt_trans_edp,
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.num_entries = ARRAY_SIZE(_xe3plpd_lt_trans_edp),
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};
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bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table)
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{
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return table == &tgl_combo_phy_trans_edp_hbr2_hobl;
···
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return intel_get_buf_trans(&mtl_c20_trans_dp14, n_entries);
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}
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static const struct intel_ddi_buf_trans *
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xe3plpd_get_lt_buf_trans(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state,
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int *n_entries)
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{
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if (intel_crtc_has_dp_encoder(crtc_state) && intel_dp_is_uhbr(crtc_state))
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return intel_get_buf_trans(&xe3plpd_lt_trans_uhbr, n_entries);
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else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
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return intel_get_buf_trans(&xe3plpd_lt_trans_edp, n_entries);
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else
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return intel_get_buf_trans(&xe3plpd_lt_trans_dp14, n_entries);
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}
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void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
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{
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struct intel_display *display = to_intel_display(encoder);
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if (DISPLAY_VER(display) >= 14) {
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if (HAS_LT_PHY(display)) {
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encoder->get_buf_trans = xe3plpd_get_lt_buf_trans;
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} else if (DISPLAY_VER(display) >= 14) {
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if (intel_encoder_is_c10phy(encoder))
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encoder->get_buf_trans = mtl_get_c10_buf_trans;
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else
+9
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
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drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
···
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u8 post_cursor;
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};
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struct xe3plpd_lt_phy_buf_trans {
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u8 txswing;
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u8 txswing_level;
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u8 pre_cursor;
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u8 main_cursor;
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u8 post_cursor;
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};
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union intel_ddi_buf_trans_entry {
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struct hsw_ddi_buf_trans hsw;
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struct bxt_ddi_buf_trans bxt;
···
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struct icl_mg_phy_ddi_buf_trans mg;
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struct tgl_dkl_phy_ddi_buf_trans dkl;
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struct dg2_snps_phy_buf_trans snps;
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struct xe3plpd_lt_phy_buf_trans lt;
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};
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struct intel_ddi_buf_trans {