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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: Program ring for vce instance 1 at its register space
We need program ring buffer on instance 1 register space domain,
when only if instance 1 available, with two instances or instance 0,
and we need only program instance 0 regsiter space domain for ring.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Leo Liu
and committed by
Alex Deucher
1410f646
cc28c4ed
+68
-27
+68
-27
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+68
-27
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
···
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static uint64_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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+
u32 v;
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+
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mutex_lock(&adev->grbm_idx_mutex);
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if (adev->vce.harvest_config == 0 ||
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adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1)
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WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
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else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0)
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WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
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if (ring == &adev->vce.ring[0])
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-
return RREG32(mmVCE_RB_RPTR);
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v = RREG32(mmVCE_RB_RPTR);
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else if (ring == &adev->vce.ring[1])
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-
return RREG32(mmVCE_RB_RPTR2);
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v = RREG32(mmVCE_RB_RPTR2);
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else
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-
return RREG32(mmVCE_RB_RPTR3);
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v = RREG32(mmVCE_RB_RPTR3);
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WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
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mutex_unlock(&adev->grbm_idx_mutex);
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return v;
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}
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/**
···
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static uint64_t vce_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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u32 v;
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+
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mutex_lock(&adev->grbm_idx_mutex);
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if (adev->vce.harvest_config == 0 ||
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adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1)
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WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
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else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0)
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WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
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if (ring == &adev->vce.ring[0])
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-
return RREG32(mmVCE_RB_WPTR);
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v = RREG32(mmVCE_RB_WPTR);
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else if (ring == &adev->vce.ring[1])
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-
return RREG32(mmVCE_RB_WPTR2);
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v = RREG32(mmVCE_RB_WPTR2);
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else
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-
return RREG32(mmVCE_RB_WPTR3);
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v = RREG32(mmVCE_RB_WPTR3);
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+
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WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
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mutex_unlock(&adev->grbm_idx_mutex);
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+
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return v;
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}
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/**
···
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{
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struct amdgpu_device *adev = ring->adev;
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mutex_lock(&adev->grbm_idx_mutex);
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if (adev->vce.harvest_config == 0 ||
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adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1)
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WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
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else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0)
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WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
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if (ring == &adev->vce.ring[0])
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WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
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else if (ring == &adev->vce.ring[1])
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WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
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else
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WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));
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WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
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mutex_unlock(&adev->grbm_idx_mutex);
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}
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static void vce_v3_0_override_vce_clock_gating(struct amdgpu_device *adev, bool override)
···
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struct amdgpu_ring *ring;
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int idx, r;
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-
ring = &adev->vce.ring[0];
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WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));
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WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
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WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
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WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
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WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
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-
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ring = &adev->vce.ring[1];
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WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr));
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WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
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WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
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WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
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WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
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-
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ring = &adev->vce.ring[2];
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WREG32(mmVCE_RB_RPTR3, lower_32_bits(ring->wptr));
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WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));
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WREG32(mmVCE_RB_BASE_LO3, ring->gpu_addr);
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WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr));
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-
WREG32(mmVCE_RB_SIZE3, ring->ring_size / 4);
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-
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mutex_lock(&adev->grbm_idx_mutex);
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for (idx = 0; idx < 2; ++idx) {
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if (adev->vce.harvest_config & (1 << idx))
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continue;
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WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx));
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/* Program instance 0 reg space for two instances or instance 0 case
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program instance 1 reg space for only instance 1 available case */
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if (idx != 1 || adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0) {
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ring = &adev->vce.ring[0];
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WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));
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WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
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WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
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WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
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WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
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ring = &adev->vce.ring[1];
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WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr));
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WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
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WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
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WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
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WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
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+
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ring = &adev->vce.ring[2];
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WREG32(mmVCE_RB_RPTR3, lower_32_bits(ring->wptr));
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WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));
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WREG32(mmVCE_RB_BASE_LO3, ring->gpu_addr);
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WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr));
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WREG32(mmVCE_RB_SIZE3, ring->ring_size / 4);
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}
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+
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vce_v3_0_mc_resume(adev, idx);
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WREG32_FIELD(VCE_STATUS, JOB_BUSY, 1);
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