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phy: cadence: salvo: decrease delay value to zero for txvalid

For USB2 L1 use cases, some hosts may start transferring less than 20us
after End of Resume, it causes the host seeing corrupt packet from the
device side. The reason is the delay time between PHY powers up and
txvalid is 20us. To fix it, we change the delay value as 0us.

Signed-off-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20230517161646.3418250-3-Frank.Li@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Peter Chen and committed by
Vinod Koul 1492498d 88bc4cda

+17
+17
drivers/phy/cadence/phy-cadence-salvo.c
··· 89 89 #define TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR 0x40f2 90 90 #define TB_ADDR_TX_RCVDETSC_CTRL 0x4124 91 91 92 + /* USB2 PHY register definition */ 93 + #define UTMI_REG15 0xaf 94 + 92 95 /* TB_ADDR_TX_RCVDETSC_CTRL */ 93 96 #define RXDET_IN_P3_32KHZ BIT(0) 97 + /* 98 + * UTMI_REG15 99 + * 100 + * Gate how many us for the txvalid signal until analog 101 + * HS/FS transmitters have powered up 102 + */ 103 + #define TXVALID_GATE_THRESHOLD_HS_MASK (BIT(4) | BIT(5)) 104 + /* 0us, txvalid is ready just after HS/FS transmitters have powered up */ 105 + #define TXVALID_GATE_THRESHOLD_HS_0US (BIT(4) | BIT(5)) 94 106 95 107 struct cdns_reg_pairs { 96 108 u16 val; ··· 241 229 value |= RXDET_IN_P3_32KHZ; 242 230 cdns_salvo_write(salvo_phy, USB3_PHY_OFFSET, TB_ADDR_TX_RCVDETSC_CTRL, 243 231 RXDET_IN_P3_32KHZ); 232 + 233 + value = cdns_salvo_read(salvo_phy, USB2_PHY_OFFSET, UTMI_REG15); 234 + value &= ~TXVALID_GATE_THRESHOLD_HS_MASK; 235 + cdns_salvo_write(salvo_phy, USB2_PHY_OFFSET, UTMI_REG15, 236 + value | TXVALID_GATE_THRESHOLD_HS_0US); 244 237 245 238 udelay(10); 246 239