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Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/amdgpu: support RS64 CP fw front door load

Support to load RS64 CP firmware front door load.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Likun Gao and committed by
Alex Deucher 14ab2924 8e070831

+57
+57
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
··· 672 672 { 673 673 const struct common_firmware_header *header = NULL; 674 674 const struct gfx_firmware_header_v1_0 *cp_hdr = NULL; 675 + const struct gfx_firmware_header_v2_0 *cpv2_hdr = NULL; 675 676 const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL; 676 677 const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL; 677 678 const struct mes_firmware_header_v1_0 *mes_hdr = NULL; ··· 691 690 692 691 header = (const struct common_firmware_header *)ucode->fw->data; 693 692 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 693 + cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)ucode->fw->data; 694 694 dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data; 695 695 dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data; 696 696 mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data; ··· 803 801 ucode_addr = (u8 *)ucode->fw->data + 804 802 le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes) + 805 803 le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes); 804 + break; 805 + case AMDGPU_UCODE_ID_CP_RS64_PFP: 806 + ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 807 + ucode_addr = (u8 *)ucode->fw->data + 808 + le32_to_cpu(header->ucode_array_offset_bytes); 809 + break; 810 + case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 811 + ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 812 + ucode_addr = (u8 *)ucode->fw->data + 813 + le32_to_cpu(cpv2_hdr->data_offset_bytes); 814 + break; 815 + case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 816 + ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 817 + ucode_addr = (u8 *)ucode->fw->data + 818 + le32_to_cpu(cpv2_hdr->data_offset_bytes); 819 + break; 820 + case AMDGPU_UCODE_ID_CP_RS64_ME: 821 + ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 822 + ucode_addr = (u8 *)ucode->fw->data + 823 + le32_to_cpu(header->ucode_array_offset_bytes); 824 + break; 825 + case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 826 + ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 827 + ucode_addr = (u8 *)ucode->fw->data + 828 + le32_to_cpu(cpv2_hdr->data_offset_bytes); 829 + break; 830 + case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 831 + ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 832 + ucode_addr = (u8 *)ucode->fw->data + 833 + le32_to_cpu(cpv2_hdr->data_offset_bytes); 834 + break; 835 + case AMDGPU_UCODE_ID_CP_RS64_MEC: 836 + ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 837 + ucode_addr = (u8 *)ucode->fw->data + 838 + le32_to_cpu(header->ucode_array_offset_bytes); 839 + break; 840 + case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 841 + ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 842 + ucode_addr = (u8 *)ucode->fw->data + 843 + le32_to_cpu(cpv2_hdr->data_offset_bytes); 844 + break; 845 + case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 846 + ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 847 + ucode_addr = (u8 *)ucode->fw->data + 848 + le32_to_cpu(cpv2_hdr->data_offset_bytes); 849 + break; 850 + case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 851 + ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 852 + ucode_addr = (u8 *)ucode->fw->data + 853 + le32_to_cpu(cpv2_hdr->data_offset_bytes); 854 + break; 855 + case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 856 + ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 857 + ucode_addr = (u8 *)ucode->fw->data + 858 + le32_to_cpu(cpv2_hdr->data_offset_bytes); 806 859 break; 807 860 default: 808 861 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);