tjh.dev / kernel
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Merge tag 'edac_updates_for_v7.0_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras

Pull EDAC updates from Borislav Petkov:

- Remove two drivers for obsolete hardware: i82443bxgx_edac and
r82600_edac

- Add support for Intel Amston Lake and Panther Lake-H SoCs to
igen6_edac

- The usual amount of fixes and cleanups

* tag 'edac_updates_for_v7.0_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras:
EDAC/r82600: Remove this obsolete driver
EDAC/i82443bxgx: Remove driver that has been marked broken since 2007
EDAC/amd64: Avoid a -Wformat-security warning
RAS/AMD/ATL: Remove an unneeded semicolon
EDAC/igen6: Add more Intel Panther Lake-H SoCs support
EDAC/igen6: Make masks of {MCHBAR, TOM, TOUUD, ECC_ERROR_LOG} configurable
EDAC/igen6: Add two Intel Amston Lake SoCs support
EDAC/i5400: Fix snprintf() limit calculation in calculate_dimm_size()
EDAC/i5000: Fix snprintf() size calculation in calculate_dimm_size()

Linus Torvalds 14c357c4 2619c62b

+86 -932
+5
CREDITS
··· 3771 3771 S: Minto, NSW, 2566 3772 3772 S: Australia 3773 3773 3774 + N: Tim Small 3775 + E: tim@buttersideup.com 3776 + D: Intel 82443BX/GX (440BX/GX chipset) EDAC driver 3777 + D: Radisys 82600 embedded chipset EDAC driver 3778 + 3774 3779 N: Stephen Smalley 3775 3780 E: sds@tycho.nsa.gov 3776 3781 D: portions of the Linux Security Module (LSM) framework and security modules
-12
MAINTAINERS
··· 9125 9125 S: Maintained 9126 9126 F: drivers/edac/i7core_edac.c 9127 9127 9128 - EDAC-I82443BXGX 9129 - M: Tim Small <tim@buttersideup.com> 9130 - L: linux-edac@vger.kernel.org 9131 - S: Maintained 9132 - F: drivers/edac/i82443bxgx_edac.c 9133 - 9134 9128 EDAC-I82975X 9135 9129 M: "Arvind R." <arvino55@gmail.com> 9136 9130 L: linux-edac@vger.kernel.org ··· 9176 9182 L: linux-edac@vger.kernel.org 9177 9183 S: Maintained 9178 9184 F: drivers/edac/qcom_edac.c 9179 - 9180 - EDAC-R82600 9181 - M: Tim Small <tim@buttersideup.com> 9182 - L: linux-edac@vger.kernel.org 9183 - S: Maintained 9184 - F: drivers/edac/r82600_edac.c 9185 9185 9186 9186 EDAC-SBRIDGE 9187 9187 M: Tony Luck <tony.luck@intel.com>
-15
drivers/edac/Kconfig
··· 150 150 Support for error detection and correction on the Intel 151 151 E7520, E7525, E7320 server chipsets. 152 152 153 - config EDAC_I82443BXGX 154 - tristate "Intel 82443BX/GX (440BX/GX)" 155 - depends on PCI && X86_32 156 - depends on BROKEN 157 - help 158 - Support for error detection and correction on the Intel 159 - 82443BX/GX memory controllers (440BX/GX chipsets). 160 - 161 153 config EDAC_I82875P 162 154 tristate "Intel 82875p (D82875P, E7210)" 163 155 depends on PCI && X86_32 ··· 214 222 help 215 223 Support for error detection and correction on the Intel 216 224 82860 chipset. 217 - 218 - config EDAC_R82600 219 - tristate "Radisys 82600 embedded chipset" 220 - depends on PCI && X86_32 221 - help 222 - Support for error detection and correction on the Radisys 223 - 82600 embedded chipset. 224 225 225 226 config EDAC_I5000 226 227 tristate "Intel Greencreek/Blackford chipset"
-2
drivers/edac/Makefile
··· 38 38 obj-$(CONFIG_EDAC_IGEN6) += igen6_edac.o 39 39 obj-$(CONFIG_EDAC_E7XXX) += e7xxx_edac.o 40 40 obj-$(CONFIG_EDAC_E752X) += e752x_edac.o 41 - obj-$(CONFIG_EDAC_I82443BXGX) += i82443bxgx_edac.o 42 41 obj-$(CONFIG_EDAC_I82875P) += i82875p_edac.o 43 42 obj-$(CONFIG_EDAC_I82975X) += i82975x_edac.o 44 43 obj-$(CONFIG_EDAC_I3000) += i3000_edac.o ··· 45 46 obj-$(CONFIG_EDAC_IE31200) += ie31200_edac.o 46 47 obj-$(CONFIG_EDAC_X38) += x38_edac.o 47 48 obj-$(CONFIG_EDAC_I82860) += i82860_edac.o 48 - obj-$(CONFIG_EDAC_R82600) += r82600_edac.o 49 49 obj-$(CONFIG_EDAC_AMD64) += amd64_edac.o 50 50 51 51 obj-$(CONFIG_EDAC_PASEMI) += pasemi_edac.o
+1 -1
drivers/edac/amd64_edac.c
··· 3911 3911 } 3912 3912 3913 3913 if (tmp_name) 3914 - scnprintf(pvt->ctl_name, sizeof(pvt->ctl_name), tmp_name); 3914 + scnprintf(pvt->ctl_name, sizeof(pvt->ctl_name), "%s", tmp_name); 3915 3915 else 3916 3916 scnprintf(pvt->ctl_name, sizeof(pvt->ctl_name), "F%02Xh_M%02Xh", 3917 3917 pvt->fam, pvt->model);
+1
drivers/edac/i5000_edac.c
··· 1111 1111 1112 1112 n = snprintf(p, space, " "); 1113 1113 p += n; 1114 + space -= n; 1114 1115 for (branch = 0; branch < MAX_BRANCHES; branch++) { 1115 1116 n = snprintf(p, space, " branch %d | ", branch); 1116 1117 p += n;
+1 -1
drivers/edac/i5400_edac.c
··· 1026 1026 space -= n; 1027 1027 } 1028 1028 1029 - space -= n; 1030 1029 edac_dbg(2, "%s\n", mem_buffer); 1031 1030 p = mem_buffer; 1032 1031 space = PAGE_SIZE; 1033 1032 1034 1033 n = snprintf(p, space, " "); 1035 1034 p += n; 1035 + space -= n; 1036 1036 for (branch = 0; branch < MAX_BRANCHES; branch++) { 1037 1037 n = snprintf(p, space, " branch %d | ", branch); 1038 1038 p += n;
-462
drivers/edac/i82443bxgx_edac.c
··· 1 - /* 2 - * Intel 82443BX/GX (440BX/GX chipset) Memory Controller EDAC kernel 3 - * module (C) 2006 Tim Small 4 - * 5 - * This file may be distributed under the terms of the GNU General 6 - * Public License. 7 - * 8 - * Written by Tim Small <tim@buttersideup.com>, based on work by Linux 9 - * Networx, Thayne Harbaugh, Dan Hollis <goemon at anime dot net> and 10 - * others. 11 - * 12 - * 440GX fix by Jason Uhlenkott <juhlenko@akamai.com>. 13 - * 14 - * Written with reference to 82443BX Host Bridge Datasheet: 15 - * http://download.intel.com/design/chipsets/datashts/29063301.pdf 16 - * references to this document given in []. 17 - * 18 - * This module doesn't support the 440LX, but it may be possible to 19 - * make it do so (the 440LX's register definitions are different, but 20 - * not completely so - I haven't studied them in enough detail to know 21 - * how easy this would be). 22 - */ 23 - 24 - #include <linux/module.h> 25 - #include <linux/init.h> 26 - 27 - #include <linux/pci.h> 28 - #include <linux/pci_ids.h> 29 - 30 - 31 - #include <linux/edac.h> 32 - #include "edac_module.h" 33 - 34 - #define EDAC_MOD_STR "i82443bxgx_edac" 35 - 36 - /* The 82443BX supports SDRAM, or EDO (EDO for mobile only), "Memory 37 - * Size: 8 MB to 512 MB (1GB with Registered DIMMs) with eight memory 38 - * rows" "The 82443BX supports multiple-bit error detection and 39 - * single-bit error correction when ECC mode is enabled and 40 - * single/multi-bit error detection when correction is disabled. 41 - * During writes to the DRAM, the 82443BX generates ECC for the data 42 - * on a QWord basis. Partial QWord writes require a read-modify-write 43 - * cycle when ECC is enabled." 44 - */ 45 - 46 - /* "Additionally, the 82443BX ensures that the data is corrected in 47 - * main memory so that accumulation of errors is prevented. Another 48 - * error within the same QWord would result in a double-bit error 49 - * which is unrecoverable. This is known as hardware scrubbing since 50 - * it requires no software intervention to correct the data in memory." 51 - */ 52 - 53 - /* [Also see page 100 (section 4.3), "DRAM Interface"] 54 - * [Also see page 112 (section 4.6.1.4), ECC] 55 - */ 56 - 57 - #define I82443BXGX_NR_CSROWS 8 58 - #define I82443BXGX_NR_CHANS 1 59 - #define I82443BXGX_NR_DIMMS 4 60 - 61 - /* 82443 PCI Device 0 */ 62 - #define I82443BXGX_NBXCFG 0x50 /* 32bit register starting at this PCI 63 - * config space offset */ 64 - #define I82443BXGX_NBXCFG_OFFSET_NON_ECCROW 24 /* Array of bits, zero if 65 - * row is non-ECC */ 66 - #define I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ 12 /* 2 bits,00=100MHz,10=66 MHz */ 67 - 68 - #define I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY 7 /* 2 bits: */ 69 - #define I82443BXGX_NBXCFG_INTEGRITY_NONE 0x0 /* 00 = Non-ECC */ 70 - #define I82443BXGX_NBXCFG_INTEGRITY_EC 0x1 /* 01 = EC (only) */ 71 - #define I82443BXGX_NBXCFG_INTEGRITY_ECC 0x2 /* 10 = ECC */ 72 - #define I82443BXGX_NBXCFG_INTEGRITY_SCRUB 0x3 /* 11 = ECC + HW Scrub */ 73 - 74 - #define I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLE 6 75 - 76 - /* 82443 PCI Device 0 */ 77 - #define I82443BXGX_EAP 0x80 /* 32bit register starting at this PCI 78 - * config space offset, Error Address 79 - * Pointer Register */ 80 - #define I82443BXGX_EAP_OFFSET_EAP 12 /* High 20 bits of error address */ 81 - #define I82443BXGX_EAP_OFFSET_MBE BIT(1) /* Err at EAP was multi-bit (W1TC) */ 82 - #define I82443BXGX_EAP_OFFSET_SBE BIT(0) /* Err at EAP was single-bit (W1TC) */ 83 - 84 - #define I82443BXGX_ERRCMD 0x90 /* 8bit register starting at this PCI 85 - * config space offset. */ 86 - #define I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE BIT(1) /* 1 = enable */ 87 - #define I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE BIT(0) /* 1 = enable */ 88 - 89 - #define I82443BXGX_ERRSTS 0x91 /* 16bit register starting at this PCI 90 - * config space offset. */ 91 - #define I82443BXGX_ERRSTS_OFFSET_MBFRE 5 /* 3 bits - first err row multibit */ 92 - #define I82443BXGX_ERRSTS_OFFSET_MEF BIT(4) /* 1 = MBE occurred */ 93 - #define I82443BXGX_ERRSTS_OFFSET_SBFRE 1 /* 3 bits - first err row singlebit */ 94 - #define I82443BXGX_ERRSTS_OFFSET_SEF BIT(0) /* 1 = SBE occurred */ 95 - 96 - #define I82443BXGX_DRAMC 0x57 /* 8bit register starting at this PCI 97 - * config space offset. */ 98 - #define I82443BXGX_DRAMC_OFFSET_DT 3 /* 2 bits, DRAM Type */ 99 - #define I82443BXGX_DRAMC_DRAM_IS_EDO 0 /* 00 = EDO */ 100 - #define I82443BXGX_DRAMC_DRAM_IS_SDRAM 1 /* 01 = SDRAM */ 101 - #define I82443BXGX_DRAMC_DRAM_IS_RSDRAM 2 /* 10 = Registered SDRAM */ 102 - 103 - #define I82443BXGX_DRB 0x60 /* 8x 8bit registers starting at this PCI 104 - * config space offset. */ 105 - 106 - /* FIXME - don't poll when ECC disabled? */ 107 - 108 - struct i82443bxgx_edacmc_error_info { 109 - u32 eap; 110 - }; 111 - 112 - static struct edac_pci_ctl_info *i82443bxgx_pci; 113 - 114 - static struct pci_dev *mci_pdev; /* init dev: in case that AGP code has 115 - * already registered driver 116 - */ 117 - 118 - static int i82443bxgx_registered = 1; 119 - 120 - static void i82443bxgx_edacmc_get_error_info(struct mem_ctl_info *mci, 121 - struct i82443bxgx_edacmc_error_info 122 - *info) 123 - { 124 - struct pci_dev *pdev; 125 - pdev = to_pci_dev(mci->pdev); 126 - pci_read_config_dword(pdev, I82443BXGX_EAP, &info->eap); 127 - if (info->eap & I82443BXGX_EAP_OFFSET_SBE) 128 - /* Clear error to allow next error to be reported [p.61] */ 129 - pci_write_bits32(pdev, I82443BXGX_EAP, 130 - I82443BXGX_EAP_OFFSET_SBE, 131 - I82443BXGX_EAP_OFFSET_SBE); 132 - 133 - if (info->eap & I82443BXGX_EAP_OFFSET_MBE) 134 - /* Clear error to allow next error to be reported [p.61] */ 135 - pci_write_bits32(pdev, I82443BXGX_EAP, 136 - I82443BXGX_EAP_OFFSET_MBE, 137 - I82443BXGX_EAP_OFFSET_MBE); 138 - } 139 - 140 - static int i82443bxgx_edacmc_process_error_info(struct mem_ctl_info *mci, 141 - struct 142 - i82443bxgx_edacmc_error_info 143 - *info, int handle_errors) 144 - { 145 - int error_found = 0; 146 - u32 eapaddr, page, pageoffset; 147 - 148 - /* bits 30:12 hold the 4kb block in which the error occurred 149 - * [p.61] */ 150 - eapaddr = (info->eap & 0xfffff000); 151 - page = eapaddr >> PAGE_SHIFT; 152 - pageoffset = eapaddr - (page << PAGE_SHIFT); 153 - 154 - if (info->eap & I82443BXGX_EAP_OFFSET_SBE) { 155 - error_found = 1; 156 - if (handle_errors) 157 - edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 158 - page, pageoffset, 0, 159 - edac_mc_find_csrow_by_page(mci, page), 160 - 0, -1, mci->ctl_name, ""); 161 - } 162 - 163 - if (info->eap & I82443BXGX_EAP_OFFSET_MBE) { 164 - error_found = 1; 165 - if (handle_errors) 166 - edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 167 - page, pageoffset, 0, 168 - edac_mc_find_csrow_by_page(mci, page), 169 - 0, -1, mci->ctl_name, ""); 170 - } 171 - 172 - return error_found; 173 - } 174 - 175 - static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci) 176 - { 177 - struct i82443bxgx_edacmc_error_info info; 178 - 179 - i82443bxgx_edacmc_get_error_info(mci, &info); 180 - i82443bxgx_edacmc_process_error_info(mci, &info, 1); 181 - } 182 - 183 - static void i82443bxgx_init_csrows(struct mem_ctl_info *mci, 184 - struct pci_dev *pdev, 185 - enum edac_type edac_mode, 186 - enum mem_type mtype) 187 - { 188 - struct csrow_info *csrow; 189 - struct dimm_info *dimm; 190 - int index; 191 - u8 drbar, dramc; 192 - u32 row_base, row_high_limit, row_high_limit_last; 193 - 194 - pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc); 195 - row_high_limit_last = 0; 196 - for (index = 0; index < mci->nr_csrows; index++) { 197 - csrow = mci->csrows[index]; 198 - dimm = csrow->channels[0]->dimm; 199 - 200 - pci_read_config_byte(pdev, I82443BXGX_DRB + index, &drbar); 201 - edac_dbg(1, "MC%d: Row=%d DRB = %#0x\n", 202 - mci->mc_idx, index, drbar); 203 - row_high_limit = ((u32) drbar << 23); 204 - /* find the DRAM Chip Select Base address and mask */ 205 - edac_dbg(1, "MC%d: Row=%d, Boundary Address=%#0x, Last = %#0x\n", 206 - mci->mc_idx, index, row_high_limit, 207 - row_high_limit_last); 208 - 209 - /* 440GX goes to 2GB, represented with a DRB of 0. */ 210 - if (row_high_limit_last && !row_high_limit) 211 - row_high_limit = 1UL << 31; 212 - 213 - /* This row is empty [p.49] */ 214 - if (row_high_limit == row_high_limit_last) 215 - continue; 216 - row_base = row_high_limit_last; 217 - csrow->first_page = row_base >> PAGE_SHIFT; 218 - csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1; 219 - dimm->nr_pages = csrow->last_page - csrow->first_page + 1; 220 - /* EAP reports in 4kilobyte granularity [61] */ 221 - dimm->grain = 1 << 12; 222 - dimm->mtype = mtype; 223 - /* I don't think 440BX can tell you device type? FIXME? */ 224 - dimm->dtype = DEV_UNKNOWN; 225 - /* Mode is global to all rows on 440BX */ 226 - dimm->edac_mode = edac_mode; 227 - row_high_limit_last = row_high_limit; 228 - } 229 - } 230 - 231 - static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) 232 - { 233 - struct mem_ctl_info *mci; 234 - struct edac_mc_layer layers[2]; 235 - u8 dramc; 236 - u32 nbxcfg, ecc_mode; 237 - enum mem_type mtype; 238 - enum edac_type edac_mode; 239 - 240 - edac_dbg(0, "MC:\n"); 241 - 242 - /* Something is really hosed if PCI config space reads from 243 - * the MC aren't working. 244 - */ 245 - if (pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg)) 246 - return -EIO; 247 - 248 - layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 249 - layers[0].size = I82443BXGX_NR_CSROWS; 250 - layers[0].is_virt_csrow = true; 251 - layers[1].type = EDAC_MC_LAYER_CHANNEL; 252 - layers[1].size = I82443BXGX_NR_CHANS; 253 - layers[1].is_virt_csrow = false; 254 - mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); 255 - if (mci == NULL) 256 - return -ENOMEM; 257 - 258 - edac_dbg(0, "MC: mci = %p\n", mci); 259 - mci->pdev = &pdev->dev; 260 - mci->mtype_cap = MEM_FLAG_EDO | MEM_FLAG_SDR | MEM_FLAG_RDR; 261 - mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; 262 - pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc); 263 - switch ((dramc >> I82443BXGX_DRAMC_OFFSET_DT) & (BIT(0) | BIT(1))) { 264 - case I82443BXGX_DRAMC_DRAM_IS_EDO: 265 - mtype = MEM_EDO; 266 - break; 267 - case I82443BXGX_DRAMC_DRAM_IS_SDRAM: 268 - mtype = MEM_SDR; 269 - break; 270 - case I82443BXGX_DRAMC_DRAM_IS_RSDRAM: 271 - mtype = MEM_RDR; 272 - break; 273 - default: 274 - edac_dbg(0, "Unknown/reserved DRAM type value in DRAMC register!\n"); 275 - mtype = -MEM_UNKNOWN; 276 - } 277 - 278 - if ((mtype == MEM_SDR) || (mtype == MEM_RDR)) 279 - mci->edac_cap = mci->edac_ctl_cap; 280 - else 281 - mci->edac_cap = EDAC_FLAG_NONE; 282 - 283 - mci->scrub_cap = SCRUB_FLAG_HW_SRC; 284 - pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg); 285 - ecc_mode = ((nbxcfg >> I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY) & 286 - (BIT(0) | BIT(1))); 287 - 288 - mci->scrub_mode = (ecc_mode == I82443BXGX_NBXCFG_INTEGRITY_SCRUB) 289 - ? SCRUB_HW_SRC : SCRUB_NONE; 290 - 291 - switch (ecc_mode) { 292 - case I82443BXGX_NBXCFG_INTEGRITY_NONE: 293 - edac_mode = EDAC_NONE; 294 - break; 295 - case I82443BXGX_NBXCFG_INTEGRITY_EC: 296 - edac_mode = EDAC_EC; 297 - break; 298 - case I82443BXGX_NBXCFG_INTEGRITY_ECC: 299 - case I82443BXGX_NBXCFG_INTEGRITY_SCRUB: 300 - edac_mode = EDAC_SECDED; 301 - break; 302 - default: 303 - edac_dbg(0, "Unknown/reserved ECC state in NBXCFG register!\n"); 304 - edac_mode = EDAC_UNKNOWN; 305 - break; 306 - } 307 - 308 - i82443bxgx_init_csrows(mci, pdev, edac_mode, mtype); 309 - 310 - /* Many BIOSes don't clear error flags on boot, so do this 311 - * here, or we get "phantom" errors occurring at module-load 312 - * time. */ 313 - pci_write_bits32(pdev, I82443BXGX_EAP, 314 - (I82443BXGX_EAP_OFFSET_SBE | 315 - I82443BXGX_EAP_OFFSET_MBE), 316 - (I82443BXGX_EAP_OFFSET_SBE | 317 - I82443BXGX_EAP_OFFSET_MBE)); 318 - 319 - mci->mod_name = EDAC_MOD_STR; 320 - mci->ctl_name = "I82443BXGX"; 321 - mci->dev_name = pci_name(pdev); 322 - mci->edac_check = i82443bxgx_edacmc_check; 323 - mci->ctl_page_to_phys = NULL; 324 - 325 - if (edac_mc_add_mc(mci)) { 326 - edac_dbg(3, "failed edac_mc_add_mc()\n"); 327 - goto fail; 328 - } 329 - 330 - /* allocating generic PCI control info */ 331 - i82443bxgx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); 332 - if (!i82443bxgx_pci) { 333 - printk(KERN_WARNING 334 - "%s(): Unable to create PCI control\n", 335 - __func__); 336 - printk(KERN_WARNING 337 - "%s(): PCI error report via EDAC not setup\n", 338 - __func__); 339 - } 340 - 341 - edac_dbg(3, "MC: success\n"); 342 - return 0; 343 - 344 - fail: 345 - edac_mc_free(mci); 346 - return -ENODEV; 347 - } 348 - 349 - /* returns count (>= 0), or negative on error */ 350 - static int i82443bxgx_edacmc_init_one(struct pci_dev *pdev, 351 - const struct pci_device_id *ent) 352 - { 353 - int rc; 354 - 355 - edac_dbg(0, "MC:\n"); 356 - 357 - /* don't need to call pci_enable_device() */ 358 - rc = i82443bxgx_edacmc_probe1(pdev, ent->driver_data); 359 - 360 - if (mci_pdev == NULL) 361 - mci_pdev = pci_dev_get(pdev); 362 - 363 - return rc; 364 - } 365 - 366 - static void i82443bxgx_edacmc_remove_one(struct pci_dev *pdev) 367 - { 368 - struct mem_ctl_info *mci; 369 - 370 - edac_dbg(0, "\n"); 371 - 372 - if (i82443bxgx_pci) 373 - edac_pci_release_generic_ctl(i82443bxgx_pci); 374 - 375 - if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) 376 - return; 377 - 378 - edac_mc_free(mci); 379 - } 380 - 381 - static const struct pci_device_id i82443bxgx_pci_tbl[] = { 382 - {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0)}, 383 - {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2)}, 384 - {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0)}, 385 - {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2)}, 386 - {0,} /* 0 terminated list. */ 387 - }; 388 - 389 - MODULE_DEVICE_TABLE(pci, i82443bxgx_pci_tbl); 390 - 391 - static struct pci_driver i82443bxgx_edacmc_driver = { 392 - .name = EDAC_MOD_STR, 393 - .probe = i82443bxgx_edacmc_init_one, 394 - .remove = i82443bxgx_edacmc_remove_one, 395 - .id_table = i82443bxgx_pci_tbl, 396 - }; 397 - 398 - static int __init i82443bxgx_edacmc_init(void) 399 - { 400 - int pci_rc; 401 - /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 402 - opstate_init(); 403 - 404 - pci_rc = pci_register_driver(&i82443bxgx_edacmc_driver); 405 - if (pci_rc < 0) 406 - goto fail0; 407 - 408 - if (mci_pdev == NULL) { 409 - const struct pci_device_id *id = &i82443bxgx_pci_tbl[0]; 410 - int i = 0; 411 - i82443bxgx_registered = 0; 412 - 413 - while (mci_pdev == NULL && id->vendor != 0) { 414 - mci_pdev = pci_get_device(id->vendor, 415 - id->device, NULL); 416 - i++; 417 - id = &i82443bxgx_pci_tbl[i]; 418 - } 419 - if (!mci_pdev) { 420 - edac_dbg(0, "i82443bxgx pci_get_device fail\n"); 421 - pci_rc = -ENODEV; 422 - goto fail1; 423 - } 424 - 425 - pci_rc = i82443bxgx_edacmc_init_one(mci_pdev, i82443bxgx_pci_tbl); 426 - 427 - if (pci_rc < 0) { 428 - edac_dbg(0, "i82443bxgx init fail\n"); 429 - pci_rc = -ENODEV; 430 - goto fail1; 431 - } 432 - } 433 - 434 - return 0; 435 - 436 - fail1: 437 - pci_unregister_driver(&i82443bxgx_edacmc_driver); 438 - 439 - fail0: 440 - pci_dev_put(mci_pdev); 441 - return pci_rc; 442 - } 443 - 444 - static void __exit i82443bxgx_edacmc_exit(void) 445 - { 446 - pci_unregister_driver(&i82443bxgx_edacmc_driver); 447 - 448 - if (!i82443bxgx_registered) 449 - i82443bxgx_edacmc_remove_one(mci_pdev); 450 - 451 - pci_dev_put(mci_pdev); 452 - } 453 - 454 - module_init(i82443bxgx_edacmc_init); 455 - module_exit(i82443bxgx_edacmc_exit); 456 - 457 - MODULE_LICENSE("GPL"); 458 - MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD"); 459 - MODULE_DESCRIPTION("EDAC MC support for Intel 82443BX/GX memory controllers"); 460 - 461 - module_param(edac_op_state, int, 0444); 462 - MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
+77 -12
drivers/edac/igen6_edac.c
··· 19 19 #include <linux/genalloc.h> 20 20 #include <linux/edac.h> 21 21 #include <linux/bits.h> 22 + #include <linux/bitfield.h> 22 23 #include <linux/io.h> 23 24 #include <asm/mach_traps.h> 24 25 #include <asm/nmi.h> ··· 80 79 #define ECC_ERROR_LOG_OFFSET (IBECC_BASE + res_cfg->ibecc_error_log_offset) 81 80 #define ECC_ERROR_LOG_CE BIT_ULL(62) 82 81 #define ECC_ERROR_LOG_UE BIT_ULL(63) 83 - #define ECC_ERROR_LOG_ADDR_SHIFT 5 84 - #define ECC_ERROR_LOG_ADDR(v) GET_BITFIELD(v, 5, 38) 85 - #define ECC_ERROR_LOG_ADDR45(v) GET_BITFIELD(v, 5, 45) 86 82 #define ECC_ERROR_LOG_SYND(v) GET_BITFIELD(v, 46, 61) 87 83 88 84 /* Host MMIO base address */ 89 85 #define MCHBAR_OFFSET 0x48 90 86 #define MCHBAR_EN BIT_ULL(0) 91 - #define MCHBAR_BASE(v) (GET_BITFIELD(v, 16, 38) << 16) 92 87 #define MCHBAR_SIZE 0x10000 93 88 94 89 /* Parameters for the channel decode stage */ ··· 126 129 bool machine_check; 127 130 /* The number of present memory controllers. */ 128 131 int num_imc; 132 + /* Host MMIO configuration */ 133 + u64 reg_mchbar_mask; 134 + /* Top of memory */ 135 + u64 reg_tom_mask; 136 + /* Top of upper usable DRAM */ 137 + u64 reg_touud_mask; 138 + /* IBECC error log */ 139 + u64 reg_eccerrlog_addr_mask; 129 140 u32 imc_base; 130 141 u32 cmf_base; 131 142 u32 cmf_size; ··· 251 246 252 247 /* Compute did IDs for Amston Lake with IBECC */ 253 248 #define DID_ASL_SKU1 0x464a 249 + #define DID_ASL_SKU2 0x4646 250 + #define DID_ASL_SKU3 0x4652 254 251 255 252 /* Compute die IDs for Raptor Lake-P with IBECC */ 256 253 #define DID_RPL_P_SKU1 0xa706 ··· 281 274 #define DID_PTL_H_SKU1 0xb000 282 275 #define DID_PTL_H_SKU2 0xb001 283 276 #define DID_PTL_H_SKU3 0xb002 277 + #define DID_PTL_H_SKU4 0xb003 278 + #define DID_PTL_H_SKU5 0xb004 279 + #define DID_PTL_H_SKU6 0xb005 280 + #define DID_PTL_H_SKU7 0xb008 281 + #define DID_PTL_H_SKU8 0xb011 282 + #define DID_PTL_H_SKU9 0xb014 283 + #define DID_PTL_H_SKU10 0xb015 284 + #define DID_PTL_H_SKU11 0xb028 285 + #define DID_PTL_H_SKU12 0xb029 286 + #define DID_PTL_H_SKU13 0xb02a 284 287 285 288 /* Compute die IDs for Wildcat Lake with IBECC */ 286 289 #define DID_WCL_SKU1 0xfd00 ··· 320 303 return -ENODEV; 321 304 } 322 305 323 - *mchbar = MCHBAR_BASE(u.v); 306 + *mchbar = u.v & res_cfg->reg_mchbar_mask; 307 + edac_dbg(2, "MCHBAR 0x%llx (reg 0x%llx)\n", *mchbar, u.v); 324 308 325 309 return 0; 326 310 } ··· 497 479 498 480 static u64 rpl_p_err_addr(u64 ecclog) 499 481 { 500 - return ECC_ERROR_LOG_ADDR45(ecclog); 482 + return field_get(res_cfg->reg_eccerrlog_addr_mask, ecclog); 501 483 } 502 484 503 485 static struct res_config ehl_cfg = { 504 486 .num_imc = 1, 487 + .reg_mchbar_mask = GENMASK_ULL(38, 16), 488 + .reg_tom_mask = GENMASK_ULL(38, 20), 489 + .reg_touud_mask = GENMASK_ULL(38, 20), 490 + .reg_eccerrlog_addr_mask = GENMASK_ULL(38, 5), 505 491 .imc_base = 0x5000, 506 492 .ibecc_base = 0xdc00, 507 493 .ibecc_available = ehl_ibecc_available, ··· 516 494 517 495 static struct res_config icl_cfg = { 518 496 .num_imc = 1, 497 + .reg_mchbar_mask = GENMASK_ULL(38, 16), 498 + .reg_tom_mask = GENMASK_ULL(38, 20), 499 + .reg_touud_mask = GENMASK_ULL(38, 20), 500 + .reg_eccerrlog_addr_mask = GENMASK_ULL(38, 5), 519 501 .imc_base = 0x5000, 520 502 .ibecc_base = 0xd800, 521 503 .ibecc_error_log_offset = 0x170, ··· 531 505 static struct res_config tgl_cfg = { 532 506 .machine_check = true, 533 507 .num_imc = 2, 508 + .reg_mchbar_mask = GENMASK_ULL(38, 17), 509 + .reg_tom_mask = GENMASK_ULL(38, 20), 510 + .reg_touud_mask = GENMASK_ULL(38, 20), 511 + .reg_eccerrlog_addr_mask = GENMASK_ULL(38, 5), 534 512 .imc_base = 0x5000, 535 513 .cmf_base = 0x11000, 536 514 .cmf_size = 0x800, ··· 549 519 static struct res_config adl_cfg = { 550 520 .machine_check = true, 551 521 .num_imc = 2, 522 + .reg_mchbar_mask = GENMASK_ULL(41, 17), 523 + .reg_tom_mask = GENMASK_ULL(41, 20), 524 + .reg_touud_mask = GENMASK_ULL(41, 20), 525 + .reg_eccerrlog_addr_mask = GENMASK_ULL(45, 5), 552 526 .imc_base = 0xd800, 553 527 .ibecc_base = 0xd400, 554 528 .ibecc_error_log_offset = 0x68, ··· 564 530 static struct res_config adl_n_cfg = { 565 531 .machine_check = true, 566 532 .num_imc = 1, 533 + .reg_mchbar_mask = GENMASK_ULL(41, 17), 534 + .reg_tom_mask = GENMASK_ULL(41, 20), 535 + .reg_touud_mask = GENMASK_ULL(41, 20), 536 + .reg_eccerrlog_addr_mask = GENMASK_ULL(45, 5), 567 537 .imc_base = 0xd800, 568 538 .ibecc_base = 0xd400, 569 539 .ibecc_error_log_offset = 0x68, ··· 579 541 static struct res_config rpl_p_cfg = { 580 542 .machine_check = true, 581 543 .num_imc = 2, 544 + .reg_mchbar_mask = GENMASK_ULL(41, 17), 545 + .reg_tom_mask = GENMASK_ULL(41, 20), 546 + .reg_touud_mask = GENMASK_ULL(41, 20), 547 + .reg_eccerrlog_addr_mask = GENMASK_ULL(45, 5), 582 548 .imc_base = 0xd800, 583 549 .ibecc_base = 0xd400, 584 550 .ibecc_error_log_offset = 0x68, ··· 595 553 static struct res_config mtl_ps_cfg = { 596 554 .machine_check = true, 597 555 .num_imc = 2, 556 + .reg_mchbar_mask = GENMASK_ULL(41, 17), 557 + .reg_tom_mask = GENMASK_ULL(41, 20), 558 + .reg_touud_mask = GENMASK_ULL(41, 20), 559 + .reg_eccerrlog_addr_mask = GENMASK_ULL(38, 5), 598 560 .imc_base = 0xd800, 599 561 .ibecc_base = 0xd400, 600 562 .ibecc_error_log_offset = 0x170, ··· 610 564 static struct res_config mtl_p_cfg = { 611 565 .machine_check = true, 612 566 .num_imc = 2, 567 + .reg_mchbar_mask = GENMASK_ULL(41, 17), 568 + .reg_tom_mask = GENMASK_ULL(41, 20), 569 + .reg_touud_mask = GENMASK_ULL(41, 20), 570 + .reg_eccerrlog_addr_mask = GENMASK_ULL(38, 5), 613 571 .imc_base = 0xd800, 614 572 .ibecc_base = 0xd400, 615 573 .ibecc_error_log_offset = 0x170, ··· 625 575 static struct res_config wcl_cfg = { 626 576 .machine_check = true, 627 577 .num_imc = 1, 578 + .reg_mchbar_mask = GENMASK_ULL(41, 17), 579 + .reg_tom_mask = GENMASK_ULL(41, 20), 580 + .reg_touud_mask = GENMASK_ULL(41, 20), 581 + .reg_eccerrlog_addr_mask = GENMASK_ULL(38, 5), 628 582 .imc_base = 0xd800, 629 583 .ibecc_base = 0xd400, 630 584 .ibecc_error_log_offset = 0x170, ··· 672 618 { PCI_VDEVICE(INTEL, DID_ADL_N_SKU12), (kernel_ulong_t)&adl_n_cfg }, 673 619 { PCI_VDEVICE(INTEL, DID_AZB_SKU1), (kernel_ulong_t)&adl_n_cfg }, 674 620 { PCI_VDEVICE(INTEL, DID_ASL_SKU1), (kernel_ulong_t)&adl_n_cfg }, 621 + { PCI_VDEVICE(INTEL, DID_ASL_SKU2), (kernel_ulong_t)&adl_n_cfg }, 622 + { PCI_VDEVICE(INTEL, DID_ASL_SKU3), (kernel_ulong_t)&adl_n_cfg }, 675 623 { PCI_VDEVICE(INTEL, DID_RPL_P_SKU1), (kernel_ulong_t)&rpl_p_cfg }, 676 624 { PCI_VDEVICE(INTEL, DID_RPL_P_SKU2), (kernel_ulong_t)&rpl_p_cfg }, 677 625 { PCI_VDEVICE(INTEL, DID_RPL_P_SKU3), (kernel_ulong_t)&rpl_p_cfg }, ··· 692 636 { PCI_VDEVICE(INTEL, DID_PTL_H_SKU1), (kernel_ulong_t)&mtl_p_cfg }, 693 637 { PCI_VDEVICE(INTEL, DID_PTL_H_SKU2), (kernel_ulong_t)&mtl_p_cfg }, 694 638 { PCI_VDEVICE(INTEL, DID_PTL_H_SKU3), (kernel_ulong_t)&mtl_p_cfg }, 639 + { PCI_VDEVICE(INTEL, DID_PTL_H_SKU4), (kernel_ulong_t)&mtl_p_cfg }, 640 + { PCI_VDEVICE(INTEL, DID_PTL_H_SKU5), (kernel_ulong_t)&mtl_p_cfg }, 641 + { PCI_VDEVICE(INTEL, DID_PTL_H_SKU6), (kernel_ulong_t)&mtl_p_cfg }, 642 + { PCI_VDEVICE(INTEL, DID_PTL_H_SKU7), (kernel_ulong_t)&mtl_p_cfg }, 643 + { PCI_VDEVICE(INTEL, DID_PTL_H_SKU8), (kernel_ulong_t)&mtl_p_cfg }, 644 + { PCI_VDEVICE(INTEL, DID_PTL_H_SKU9), (kernel_ulong_t)&mtl_p_cfg }, 645 + { PCI_VDEVICE(INTEL, DID_PTL_H_SKU10), (kernel_ulong_t)&mtl_p_cfg }, 646 + { PCI_VDEVICE(INTEL, DID_PTL_H_SKU11), (kernel_ulong_t)&mtl_p_cfg }, 647 + { PCI_VDEVICE(INTEL, DID_PTL_H_SKU12), (kernel_ulong_t)&mtl_p_cfg }, 648 + { PCI_VDEVICE(INTEL, DID_PTL_H_SKU13), (kernel_ulong_t)&mtl_p_cfg }, 695 649 { PCI_VDEVICE(INTEL, DID_WCL_SKU1), (kernel_ulong_t)&wcl_cfg }, 696 650 { }, 697 651 }; ··· 970 904 if (res_cfg->err_addr) 971 905 eaddr = res_cfg->err_addr(node->ecclog); 972 906 else 973 - eaddr = ECC_ERROR_LOG_ADDR(node->ecclog) << 974 - ECC_ERROR_LOG_ADDR_SHIFT; 907 + eaddr = node->ecclog & res_cfg->reg_eccerrlog_addr_mask; 908 + 975 909 res.mc = node->mc; 976 910 res.sys_addr = res_cfg->err_addr_to_sys_addr(eaddr, res.mc); 977 911 res.imc_addr = res_cfg->err_addr_to_imc_addr(eaddr, res.mc); ··· 1191 1125 1192 1126 pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val); 1193 1127 1194 - val >>= ECC_ERROR_LOG_ADDR_SHIFT; 1195 - ecclog = (val << ECC_ERROR_LOG_ADDR_SHIFT) | ECC_ERROR_LOG_CE; 1128 + ecclog = (val & res_cfg->reg_eccerrlog_addr_mask) | ECC_ERROR_LOG_CE; 1196 1129 1197 1130 if (!ecclog_gen_pool_add(0, ecclog)) 1198 1131 irq_work_queue(&ecclog_irq_work); ··· 1257 1192 goto fail; 1258 1193 } 1259 1194 1260 - igen6_tom = u.v & GENMASK_ULL(38, 20); 1195 + igen6_tom = u.v & res_cfg->reg_tom_mask; 1261 1196 1262 1197 if (get_mchbar(pdev, mchbar)) 1263 1198 goto fail; ··· 1268 1203 else if (pci_read_config_dword(pdev, TOUUD_OFFSET + 4, &u.v_hi)) 1269 1204 edac_dbg(2, "Failed to read upper TOUUD\n"); 1270 1205 else 1271 - igen6_touud = u.v & GENMASK_ULL(38, 20); 1206 + igen6_touud = u.v & res_cfg->reg_touud_mask; 1272 1207 #endif 1273 1208 1274 1209 return 0;
-426
drivers/edac/r82600_edac.c
··· 1 - /* 2 - * Radisys 82600 Embedded chipset Memory Controller kernel module 3 - * (C) 2005 EADS Astrium 4 - * This file may be distributed under the terms of the 5 - * GNU General Public License. 6 - * 7 - * Written by Tim Small <tim@buttersideup.com>, based on work by Thayne 8 - * Harbaugh, Dan Hollis <goemon at anime dot net> and others. 9 - * 10 - * $Id: edac_r82600.c,v 1.1.2.6 2005/10/05 00:43:44 dsp_llnl Exp $ 11 - * 12 - * Written with reference to 82600 High Integration Dual PCI System 13 - * Controller Data Book: 14 - * www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf 15 - * references to this document given in [] 16 - */ 17 - 18 - #include <linux/module.h> 19 - #include <linux/init.h> 20 - #include <linux/pci.h> 21 - #include <linux/pci_ids.h> 22 - #include <linux/edac.h> 23 - #include "edac_module.h" 24 - 25 - #define EDAC_MOD_STR "r82600_edac" 26 - 27 - #define r82600_printk(level, fmt, arg...) \ 28 - edac_printk(level, "r82600", fmt, ##arg) 29 - 30 - #define r82600_mc_printk(mci, level, fmt, arg...) \ 31 - edac_mc_chipset_printk(mci, level, "r82600", fmt, ##arg) 32 - 33 - /* Radisys say "The 82600 integrates a main memory SDRAM controller that 34 - * supports up to four banks of memory. The four banks can support a mix of 35 - * sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs, 36 - * each of which can be any size from 16MB to 512MB. Both registered (control 37 - * signals buffered) and unbuffered DIMM types are supported. Mixing of 38 - * registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs 39 - * is not allowed. The 82600 SDRAM interface operates at the same frequency as 40 - * the CPU bus, 66MHz, 100MHz or 133MHz." 41 - */ 42 - 43 - #define R82600_NR_CSROWS 4 44 - #define R82600_NR_CHANS 1 45 - #define R82600_NR_DIMMS 4 46 - 47 - #define R82600_BRIDGE_ID 0x8200 48 - 49 - /* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */ 50 - #define R82600_DRAMC 0x57 /* Various SDRAM related control bits 51 - * all bits are R/W 52 - * 53 - * 7 SDRAM ISA Hole Enable 54 - * 6 Flash Page Mode Enable 55 - * 5 ECC Enable: 1=ECC 0=noECC 56 - * 4 DRAM DIMM Type: 1= 57 - * 3 BIOS Alias Disable 58 - * 2 SDRAM BIOS Flash Write Enable 59 - * 1:0 SDRAM Refresh Rate: 00=Disabled 60 - * 01=7.8usec (256Mbit SDRAMs) 61 - * 10=15.6us 11=125usec 62 - */ 63 - 64 - #define R82600_SDRAMC 0x76 /* "SDRAM Control Register" 65 - * More SDRAM related control bits 66 - * all bits are R/W 67 - * 68 - * 15:8 Reserved. 69 - * 70 - * 7:5 Special SDRAM Mode Select 71 - * 72 - * 4 Force ECC 73 - * 74 - * 1=Drive ECC bits to 0 during 75 - * write cycles (i.e. ECC test mode) 76 - * 77 - * 0=Normal ECC functioning 78 - * 79 - * 3 Enhanced Paging Enable 80 - * 81 - * 2 CAS# Latency 0=3clks 1=2clks 82 - * 83 - * 1 RAS# to CAS# Delay 0=3 1=2 84 - * 85 - * 0 RAS# Precharge 0=3 1=2 86 - */ 87 - 88 - #define R82600_EAP 0x80 /* ECC Error Address Pointer Register 89 - * 90 - * 31 Disable Hardware Scrubbing (RW) 91 - * 0=Scrub on corrected read 92 - * 1=Don't scrub on corrected read 93 - * 94 - * 30:12 Error Address Pointer (RO) 95 - * Upper 19 bits of error address 96 - * 97 - * 11:4 Syndrome Bits (RO) 98 - * 99 - * 3 BSERR# on multibit error (RW) 100 - * 1=enable 0=disable 101 - * 102 - * 2 NMI on Single Bit Eror (RW) 103 - * 1=NMI triggered by SBE n.b. other 104 - * prerequeists 105 - * 0=NMI not triggered 106 - * 107 - * 1 MBE (R/WC) 108 - * read 1=MBE at EAP (see above) 109 - * read 0=no MBE, or SBE occurred first 110 - * write 1=Clear MBE status (must also 111 - * clear SBE) 112 - * write 0=NOP 113 - * 114 - * 1 SBE (R/WC) 115 - * read 1=SBE at EAP (see above) 116 - * read 0=no SBE, or MBE occurred first 117 - * write 1=Clear SBE status (must also 118 - * clear MBE) 119 - * write 0=NOP 120 - */ 121 - 122 - #define R82600_DRBA 0x60 /* + 0x60..0x63 SDRAM Row Boundary Address 123 - * Registers 124 - * 125 - * 7:0 Address lines 30:24 - upper limit of 126 - * each row [p57] 127 - */ 128 - 129 - struct r82600_error_info { 130 - u32 eapr; 131 - }; 132 - 133 - static bool disable_hardware_scrub; 134 - 135 - static struct edac_pci_ctl_info *r82600_pci; 136 - 137 - static void r82600_get_error_info(struct mem_ctl_info *mci, 138 - struct r82600_error_info *info) 139 - { 140 - struct pci_dev *pdev; 141 - 142 - pdev = to_pci_dev(mci->pdev); 143 - pci_read_config_dword(pdev, R82600_EAP, &info->eapr); 144 - 145 - if (info->eapr & BIT(0)) 146 - /* Clear error to allow next error to be reported [p.62] */ 147 - pci_write_bits32(pdev, R82600_EAP, 148 - ((u32) BIT(0) & (u32) BIT(1)), 149 - ((u32) BIT(0) & (u32) BIT(1))); 150 - 151 - if (info->eapr & BIT(1)) 152 - /* Clear error to allow next error to be reported [p.62] */ 153 - pci_write_bits32(pdev, R82600_EAP, 154 - ((u32) BIT(0) & (u32) BIT(1)), 155 - ((u32) BIT(0) & (u32) BIT(1))); 156 - } 157 - 158 - static int r82600_process_error_info(struct mem_ctl_info *mci, 159 - struct r82600_error_info *info, 160 - int handle_errors) 161 - { 162 - int error_found; 163 - u32 eapaddr, page; 164 - u32 syndrome; 165 - 166 - error_found = 0; 167 - 168 - /* bits 30:12 store the upper 19 bits of the 32 bit error address */ 169 - eapaddr = ((info->eapr >> 12) & 0x7FFF) << 13; 170 - /* Syndrome in bits 11:4 [p.62] */ 171 - syndrome = (info->eapr >> 4) & 0xFF; 172 - 173 - /* the R82600 reports at less than page * 174 - * granularity (upper 19 bits only) */ 175 - page = eapaddr >> PAGE_SHIFT; 176 - 177 - if (info->eapr & BIT(0)) { /* CE? */ 178 - error_found = 1; 179 - 180 - if (handle_errors) 181 - edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 182 - page, 0, syndrome, 183 - edac_mc_find_csrow_by_page(mci, page), 184 - 0, -1, 185 - mci->ctl_name, ""); 186 - } 187 - 188 - if (info->eapr & BIT(1)) { /* UE? */ 189 - error_found = 1; 190 - 191 - if (handle_errors) 192 - /* 82600 doesn't give enough info */ 193 - edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 194 - page, 0, 0, 195 - edac_mc_find_csrow_by_page(mci, page), 196 - 0, -1, 197 - mci->ctl_name, ""); 198 - } 199 - 200 - return error_found; 201 - } 202 - 203 - static void r82600_check(struct mem_ctl_info *mci) 204 - { 205 - struct r82600_error_info info; 206 - 207 - r82600_get_error_info(mci, &info); 208 - r82600_process_error_info(mci, &info, 1); 209 - } 210 - 211 - static inline int ecc_enabled(u8 dramcr) 212 - { 213 - return dramcr & BIT(5); 214 - } 215 - 216 - static void r82600_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev, 217 - u8 dramcr) 218 - { 219 - struct csrow_info *csrow; 220 - struct dimm_info *dimm; 221 - int index; 222 - u8 drbar; /* SDRAM Row Boundary Address Register */ 223 - u32 row_high_limit, row_high_limit_last; 224 - u32 reg_sdram, ecc_on, row_base; 225 - 226 - ecc_on = ecc_enabled(dramcr); 227 - reg_sdram = dramcr & BIT(4); 228 - row_high_limit_last = 0; 229 - 230 - for (index = 0; index < mci->nr_csrows; index++) { 231 - csrow = mci->csrows[index]; 232 - dimm = csrow->channels[0]->dimm; 233 - 234 - /* find the DRAM Chip Select Base address and mask */ 235 - pci_read_config_byte(pdev, R82600_DRBA + index, &drbar); 236 - 237 - edac_dbg(1, "Row=%d DRBA = %#0x\n", index, drbar); 238 - 239 - row_high_limit = ((u32) drbar << 24); 240 - /* row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */ 241 - 242 - edac_dbg(1, "Row=%d, Boundary Address=%#0x, Last = %#0x\n", 243 - index, row_high_limit, row_high_limit_last); 244 - 245 - /* Empty row [p.57] */ 246 - if (row_high_limit == row_high_limit_last) 247 - continue; 248 - 249 - row_base = row_high_limit_last; 250 - 251 - csrow->first_page = row_base >> PAGE_SHIFT; 252 - csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1; 253 - 254 - dimm->nr_pages = csrow->last_page - csrow->first_page + 1; 255 - /* Error address is top 19 bits - so granularity is * 256 - * 14 bits */ 257 - dimm->grain = 1 << 14; 258 - dimm->mtype = reg_sdram ? MEM_RDDR : MEM_DDR; 259 - /* FIXME - check that this is unknowable with this chipset */ 260 - dimm->dtype = DEV_UNKNOWN; 261 - 262 - /* Mode is global on 82600 */ 263 - dimm->edac_mode = ecc_on ? EDAC_SECDED : EDAC_NONE; 264 - row_high_limit_last = row_high_limit; 265 - } 266 - } 267 - 268 - static int r82600_probe1(struct pci_dev *pdev, int dev_idx) 269 - { 270 - struct mem_ctl_info *mci; 271 - struct edac_mc_layer layers[2]; 272 - u8 dramcr; 273 - u32 eapr; 274 - u32 scrub_disabled; 275 - u32 sdram_refresh_rate; 276 - struct r82600_error_info discard; 277 - 278 - edac_dbg(0, "\n"); 279 - pci_read_config_byte(pdev, R82600_DRAMC, &dramcr); 280 - pci_read_config_dword(pdev, R82600_EAP, &eapr); 281 - scrub_disabled = eapr & BIT(31); 282 - sdram_refresh_rate = dramcr & (BIT(0) | BIT(1)); 283 - edac_dbg(2, "sdram refresh rate = %#0x\n", sdram_refresh_rate); 284 - edac_dbg(2, "DRAMC register = %#0x\n", dramcr); 285 - layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 286 - layers[0].size = R82600_NR_CSROWS; 287 - layers[0].is_virt_csrow = true; 288 - layers[1].type = EDAC_MC_LAYER_CHANNEL; 289 - layers[1].size = R82600_NR_CHANS; 290 - layers[1].is_virt_csrow = false; 291 - mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); 292 - if (mci == NULL) 293 - return -ENOMEM; 294 - 295 - edac_dbg(0, "mci = %p\n", mci); 296 - mci->pdev = &pdev->dev; 297 - mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR; 298 - mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; 299 - /* FIXME try to work out if the chip leads have been used for COM2 300 - * instead on this board? [MA6?] MAYBE: 301 - */ 302 - 303 - /* On the R82600, the pins for memory bits 72:65 - i.e. the * 304 - * EC bits are shared with the pins for COM2 (!), so if COM2 * 305 - * is enabled, we assume COM2 is wired up, and thus no EDAC * 306 - * is possible. */ 307 - mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; 308 - 309 - if (ecc_enabled(dramcr)) { 310 - if (scrub_disabled) 311 - edac_dbg(3, "mci = %p - Scrubbing disabled! EAP: %#0x\n", 312 - mci, eapr); 313 - } else 314 - mci->edac_cap = EDAC_FLAG_NONE; 315 - 316 - mci->mod_name = EDAC_MOD_STR; 317 - mci->ctl_name = "R82600"; 318 - mci->dev_name = pci_name(pdev); 319 - mci->edac_check = r82600_check; 320 - mci->ctl_page_to_phys = NULL; 321 - r82600_init_csrows(mci, pdev, dramcr); 322 - r82600_get_error_info(mci, &discard); /* clear counters */ 323 - 324 - /* Here we assume that we will never see multiple instances of this 325 - * type of memory controller. The ID is therefore hardcoded to 0. 326 - */ 327 - if (edac_mc_add_mc(mci)) { 328 - edac_dbg(3, "failed edac_mc_add_mc()\n"); 329 - goto fail; 330 - } 331 - 332 - /* get this far and it's successful */ 333 - 334 - if (disable_hardware_scrub) { 335 - edac_dbg(3, "Disabling Hardware Scrub (scrub on error)\n"); 336 - pci_write_bits32(pdev, R82600_EAP, BIT(31), BIT(31)); 337 - } 338 - 339 - /* allocating generic PCI control info */ 340 - r82600_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); 341 - if (!r82600_pci) { 342 - printk(KERN_WARNING 343 - "%s(): Unable to create PCI control\n", 344 - __func__); 345 - printk(KERN_WARNING 346 - "%s(): PCI error report via EDAC not setup\n", 347 - __func__); 348 - } 349 - 350 - edac_dbg(3, "success\n"); 351 - return 0; 352 - 353 - fail: 354 - edac_mc_free(mci); 355 - return -ENODEV; 356 - } 357 - 358 - /* returns count (>= 0), or negative on error */ 359 - static int r82600_init_one(struct pci_dev *pdev, 360 - const struct pci_device_id *ent) 361 - { 362 - edac_dbg(0, "\n"); 363 - 364 - /* don't need to call pci_enable_device() */ 365 - return r82600_probe1(pdev, ent->driver_data); 366 - } 367 - 368 - static void r82600_remove_one(struct pci_dev *pdev) 369 - { 370 - struct mem_ctl_info *mci; 371 - 372 - edac_dbg(0, "\n"); 373 - 374 - if (r82600_pci) 375 - edac_pci_release_generic_ctl(r82600_pci); 376 - 377 - if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) 378 - return; 379 - 380 - edac_mc_free(mci); 381 - } 382 - 383 - static const struct pci_device_id r82600_pci_tbl[] = { 384 - { 385 - PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID) 386 - }, 387 - { 388 - 0, 389 - } /* 0 terminated list. */ 390 - }; 391 - 392 - MODULE_DEVICE_TABLE(pci, r82600_pci_tbl); 393 - 394 - static struct pci_driver r82600_driver = { 395 - .name = EDAC_MOD_STR, 396 - .probe = r82600_init_one, 397 - .remove = r82600_remove_one, 398 - .id_table = r82600_pci_tbl, 399 - }; 400 - 401 - static int __init r82600_init(void) 402 - { 403 - /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 404 - opstate_init(); 405 - 406 - return pci_register_driver(&r82600_driver); 407 - } 408 - 409 - static void __exit r82600_exit(void) 410 - { 411 - pci_unregister_driver(&r82600_driver); 412 - } 413 - 414 - module_init(r82600_init); 415 - module_exit(r82600_exit); 416 - 417 - MODULE_LICENSE("GPL"); 418 - MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD Ltd. on behalf of EADS Astrium"); 419 - MODULE_DESCRIPTION("MC support for Radisys 82600 memory controllers"); 420 - 421 - module_param(disable_hardware_scrub, bool, 0644); 422 - MODULE_PARM_DESC(disable_hardware_scrub, 423 - "If set, disable the chipset's automatic scrub for CEs"); 424 - 425 - module_param(edac_op_state, int, 0444); 426 - MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
+1 -1
drivers/ras/amd/atl/denormalize.c
··· 683 683 default: 684 684 atl_debug_on_bad_intlv_mode(ctx); 685 685 return -EINVAL; 686 - }; 686 + } 687 687 688 688 if (ctx->map.num_intlv_sockets == 1) { 689 689 hash_pa8 = BIT_ULL(shift_value) & ctx->ret_addr;