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drm/i915: Remove i915_reg.h from intel_fifo_underrun.c

Move GEN7_ERR_INT reg to common header to make intel_fifo_underrun.c
free from including i915_reg.h.

v2: Move GEN7_ERR_INT regs to display header (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patch.msgid.link/20260205094341.1882816-17-uma.shankar@intel.com

+23 -24
+23
drivers/gpu/drm/i915/display/intel_display_regs.h
··· 82 82 #define DERRMR_PIPEC_VBLANK (1 << 21) 83 83 #define DERRMR_PIPEC_HBLANK (1 << 22) 84 84 85 + #define GEN7_ERR_INT _MMIO(0x44040) 86 + #define ERR_INT_POISON (1 << 31) 87 + #define ERR_INT_INVALID_GTT_PTE (1 << 29) 88 + #define ERR_INT_INVALID_PTE_DATA (1 << 28) 89 + #define ERR_INT_SPRITE_C_FAULT (1 << 23) 90 + #define ERR_INT_PRIMARY_C_FAULT (1 << 22) 91 + #define ERR_INT_CURSOR_C_FAULT (1 << 21) 92 + #define ERR_INT_SPRITE_B_FAULT (1 << 20) 93 + #define ERR_INT_PRIMARY_B_FAULT (1 << 19) 94 + #define ERR_INT_CURSOR_B_FAULT (1 << 18) 95 + #define ERR_INT_SPRITE_A_FAULT (1 << 17) 96 + #define ERR_INT_PRIMARY_A_FAULT (1 << 16) 97 + #define ERR_INT_CURSOR_A_FAULT (1 << 15) 98 + #define ERR_INT_MMIO_UNCLAIMED (1 << 13) 99 + #define ERR_INT_PIPE_CRC_DONE_C (1 << 8) 100 + #define ERR_INT_FIFO_UNDERRUN_C (1 << 6) 101 + #define ERR_INT_PIPE_CRC_DONE_B (1 << 5) 102 + #define ERR_INT_FIFO_UNDERRUN_B (1 << 3) 103 + #define ERR_INT_PIPE_CRC_DONE_A (1 << 2) 104 + #define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3)) 105 + #define ERR_INT_FIFO_UNDERRUN_A (1 << 0) 106 + #define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 107 + 85 108 #define VLV_IRQ_REGS I915_IRQ_REGS(VLV_IMR, \ 86 109 VLV_IER, \ 87 110 VLV_IIR)
-1
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
··· 29 29 30 30 #include <drm/drm_print.h> 31 31 32 - #include "i915_reg.h" 33 32 #include "intel_de.h" 34 33 #include "intel_display_irq.h" 35 34 #include "intel_display_regs.h"
-23
drivers/gpu/drm/i915/i915_reg.h
··· 325 325 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070) 326 326 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074) 327 327 328 - #define GEN7_ERR_INT _MMIO(0x44040) 329 - #define ERR_INT_POISON (1 << 31) 330 - #define ERR_INT_INVALID_GTT_PTE (1 << 29) 331 - #define ERR_INT_INVALID_PTE_DATA (1 << 28) 332 - #define ERR_INT_SPRITE_C_FAULT (1 << 23) 333 - #define ERR_INT_PRIMARY_C_FAULT (1 << 22) 334 - #define ERR_INT_CURSOR_C_FAULT (1 << 21) 335 - #define ERR_INT_SPRITE_B_FAULT (1 << 20) 336 - #define ERR_INT_PRIMARY_B_FAULT (1 << 19) 337 - #define ERR_INT_CURSOR_B_FAULT (1 << 18) 338 - #define ERR_INT_SPRITE_A_FAULT (1 << 17) 339 - #define ERR_INT_PRIMARY_A_FAULT (1 << 16) 340 - #define ERR_INT_CURSOR_A_FAULT (1 << 15) 341 - #define ERR_INT_MMIO_UNCLAIMED (1 << 13) 342 - #define ERR_INT_PIPE_CRC_DONE_C (1 << 8) 343 - #define ERR_INT_FIFO_UNDERRUN_C (1 << 6) 344 - #define ERR_INT_PIPE_CRC_DONE_B (1 << 5) 345 - #define ERR_INT_FIFO_UNDERRUN_B (1 << 3) 346 - #define ERR_INT_PIPE_CRC_DONE_A (1 << 2) 347 - #define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3)) 348 - #define ERR_INT_FIFO_UNDERRUN_A (1 << 0) 349 - #define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 350 - 351 328 #define FPGA_DBG _MMIO(0x42300) 352 329 #define FPGA_DBG_RM_NOCLAIM REG_BIT(31) 353 330