Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
riscv: Implement cmpxchg8/16() using Zabha
This adds runtime support for Zabha in cmpxchg8/16() operations.
Note that in the absence of Zacas support in the toolchain, CAS
instructions from Zabha won't be used.
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Andrea Parri <parri.andrea@gmail.com>
Link: https://lore.kernel.org/r/20241103145153.105097-6-alexghiti@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
authored by
Alexandre Ghiti
and committed by
Palmer Dabbelt
1658ef43
51624ddc
+72
-29
+18
arch/riscv/Kconfig
+18
arch/riscv/Kconfig
···
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use of these instructions in the kernel when the Zawrs extension is
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detected at boot.
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config TOOLCHAIN_HAS_ZABHA
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bool
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default y
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depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zabha)
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depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zabha)
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depends on AS_HAS_OPTION_ARCH
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config RISCV_ISA_ZABHA
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bool "Zabha extension support for atomic byte/halfword operations"
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depends on TOOLCHAIN_HAS_ZABHA
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depends on RISCV_ALTERNATIVE
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default y
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help
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Enable the use of the Zabha ISA-extension to implement kernel
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byte/halfword atomic memory operations when it is detected at boot.
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If you don't know what to do here, say Y.
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config TOOLCHAIN_HAS_ZACAS
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bool
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default y
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arch/riscv/Makefile
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arch/riscv/Makefile
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# Check if the toolchain supports Zacas
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riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZACAS) := $(riscv-march-y)_zacas
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# Check if the toolchain supports Zabha
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riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZABHA) := $(riscv-march-y)_zabha
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# Remove F,D,V from isa string for all. Keep extensions between "fd" and "v" by
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# matching non-v and non-multi-letter extensions out with the filter ([^v_]*)
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KBUILD_CFLAGS += -march=$(shell echo $(riscv-march-y) | sed -E 's/(rv32ima|rv64ima)fd([^v_]*)v?/\1\2/')
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-29
arch/riscv/include/asm/cmpxchg.h
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-29
arch/riscv/include/asm/cmpxchg.h
···
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* indicated by comparing RETURN with OLD.
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*/
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#define __arch_cmpxchg_masked(sc_sfx, prepend, append, r, p, o, n) \
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({ \
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u32 *__ptr32b = (u32 *)((ulong)(p) & ~0x3); \
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ulong __s = ((ulong)(p) & (0x4 - sizeof(*p))) * BITS_PER_BYTE; \
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ulong __mask = GENMASK(((sizeof(*p)) * BITS_PER_BYTE) - 1, 0) \
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<< __s; \
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ulong __newx = (ulong)(n) << __s; \
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ulong __oldx = (ulong)(o) << __s; \
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ulong __retx; \
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ulong __rc; \
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\
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__asm__ __volatile__ ( \
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prepend \
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"0: lr.w %0, %2\n" \
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" and %1, %0, %z5\n" \
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" bne %1, %z3, 1f\n" \
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" and %1, %0, %z6\n" \
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" or %1, %1, %z4\n" \
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" sc.w" sc_sfx " %1, %1, %2\n" \
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" bnez %1, 0b\n" \
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append \
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"1:\n" \
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: "=&r" (__retx), "=&r" (__rc), "+A" (*(__ptr32b)) \
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: "rJ" ((long)__oldx), "rJ" (__newx), \
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"rJ" (__mask), "rJ" (~__mask) \
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: "memory"); \
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\
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r = (__typeof__(*(p)))((__retx & __mask) >> __s); \
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#define __arch_cmpxchg_masked(sc_sfx, cas_sfx, prepend, append, r, p, o, n) \
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({ \
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if (IS_ENABLED(CONFIG_RISCV_ISA_ZABHA) && \
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IS_ENABLED(CONFIG_RISCV_ISA_ZACAS) && \
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riscv_has_extension_unlikely(RISCV_ISA_EXT_ZABHA) && \
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riscv_has_extension_unlikely(RISCV_ISA_EXT_ZACAS)) { \
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r = o; \
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\
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__asm__ __volatile__ ( \
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prepend \
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" amocas" cas_sfx " %0, %z2, %1\n" \
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append \
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: "+&r" (r), "+A" (*(p)) \
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: "rJ" (n) \
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: "memory"); \
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} else { \
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u32 *__ptr32b = (u32 *)((ulong)(p) & ~0x3); \
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ulong __s = ((ulong)(p) & (0x4 - sizeof(*p))) * BITS_PER_BYTE; \
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ulong __mask = GENMASK(((sizeof(*p)) * BITS_PER_BYTE) - 1, 0) \
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<< __s; \
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ulong __newx = (ulong)(n) << __s; \
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ulong __oldx = (ulong)(o) << __s; \
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ulong __retx; \
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ulong __rc; \
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\
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__asm__ __volatile__ ( \
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prepend \
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"0: lr.w %0, %2\n" \
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" and %1, %0, %z5\n" \
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" bne %1, %z3, 1f\n" \
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" and %1, %0, %z6\n" \
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" or %1, %1, %z4\n" \
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" sc.w" sc_sfx " %1, %1, %2\n" \
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" bnez %1, 0b\n" \
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append \
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"1:\n" \
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: "=&r" (__retx), "=&r" (__rc), "+A" (*(__ptr32b)) \
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: "rJ" ((long)__oldx), "rJ" (__newx), \
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"rJ" (__mask), "rJ" (~__mask) \
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: "memory"); \
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\
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r = (__typeof__(*(p)))((__retx & __mask) >> __s); \
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} \
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})
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#define __arch_cmpxchg(lr_sfx, sc_cas_sfx, prepend, append, r, p, co, o, n) \
···
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\
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switch (sizeof(*__ptr)) { \
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case 1: \
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__arch_cmpxchg_masked(sc_cas_sfx, ".b" sc_cas_sfx, \
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prepend, append, \
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__ret, __ptr, __old, __new); \
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break; \
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case 2: \
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__arch_cmpxchg_masked(sc_cas_sfx, prepend, append, \
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__arch_cmpxchg_masked(sc_cas_sfx, ".h" sc_cas_sfx, \
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prepend, append, \
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__ret, __ptr, __old, __new); \
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break; \
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case 4: \
+1
arch/riscv/include/asm/hwcap.h
+1
arch/riscv/include/asm/hwcap.h
+1
arch/riscv/kernel/cpufeature.c
+1
arch/riscv/kernel/cpufeature.c
···
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__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
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__RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
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__RISCV_ISA_EXT_DATA(zimop, RISCV_ISA_EXT_ZIMOP),
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__RISCV_ISA_EXT_DATA(zabha, RISCV_ISA_EXT_ZABHA),
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__RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS),
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__RISCV_ISA_EXT_DATA(zawrs, RISCV_ISA_EXT_ZAWRS),
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__RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA),