drm/msm/dsi/phy: rename DSI_PHY_7NM_QUIRK_PRE_V4_1 to DSI_PHY_7NM_QUIRK_V4_0

The quirk flag DSI_PHY_7NM_QUIRK_PRE_V4_1 is renamed to
DSI_PHY_7NM_QUIRK_V4_0 to better reflect the actual hardware revision
it applies to. (Only SM8150 uses it, its hardware revision is 4.0)

No functional change.

Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/707416/
Link: https://lore.kernel.org/r/20260226122958.22555-3-mitltlatltl@gmail.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

authored by

Pengyu Luo and committed by

Dmitry Baryshkov 2 months ago 18417122 7fe04c7c

+8 -8

1 changed file

expand all

drivers

gpu

drm

msm

dsi

phy

dsi_phy_7nm.c

+8 -8

drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c

··· 41 41 #define VCO_REF_CLK_RATE 19200000 42 42 #define FRAC_BITS 18 43 43 44 - /* Hardware is pre V4.1 */ 45 - #define DSI_PHY_7NM_QUIRK_PRE_V4_1 BIT(0) 44 + /* Hardware is V4.0 */ 45 + #define DSI_PHY_7NM_QUIRK_V4_0 BIT(0) 46 46 /* Hardware is V4.1 */ 47 47 #define DSI_PHY_7NM_QUIRK_V4_1 BIT(1) 48 48 /* Hardware is V4.2 */ ··· 141 141 dec_multiple = div_u64(pll_freq * multiplier, divider); 142 142 dec = div_u64_rem(dec_multiple, multiplier, &frac); 143 143 144 - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) { 144 + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_0) { 145 145 config->pll_clock_inverters = 0x28; 146 146 } else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_2)) { 147 147 if (pll_freq < 163000000ULL) ··· 264 264 void __iomem *base = pll->phy->pll_base; 265 265 u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00; 266 266 267 - if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) 267 + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_0)) 268 268 if (pll->vco_current_rate >= 3100000000ULL) 269 269 analog_controls_five_1 = 0x03; 270 270 ··· 313 313 writel(0x29, base + REG_DSI_7nm_PHY_PLL_PFILT); 314 314 writel(0x2f, base + REG_DSI_7nm_PHY_PLL_PFILT); 315 315 writel(0x2a, base + REG_DSI_7nm_PHY_PLL_IFILT); 316 - writel(!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) ? 0x3f : 0x22, 316 + writel(!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_0) ? 0x3f : 0x22, 317 317 base + REG_DSI_7nm_PHY_PLL_IFILT); 318 318 319 - if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) { 319 + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_0)) { 320 320 writel(0x22, base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE); 321 321 if (pll->slave) 322 322 writel(0x22, pll->slave->phy->pll_base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE); ··· 928 928 const u8 *tx_dctrl = tx_dctrl_0; 929 929 void __iomem *lane_base = phy->lane_base; 930 930 931 - if (!(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) 931 + if (!(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_0)) 932 932 tx_dctrl = tx_dctrl_1; 933 933 934 934 /* Strength ctrl settings */ ··· 1319 1319 .max_pll_rate = 3500000000UL, 1320 1320 .io_start = { 0xae94400, 0xae96400 }, 1321 1321 .num_dsi_phy = 2, 1322 - .quirks = DSI_PHY_7NM_QUIRK_PRE_V4_1, 1322 + .quirks = DSI_PHY_7NM_QUIRK_V4_0, 1323 1323 }; 1324 1324 1325 1325 const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = {

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