Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: qcom: qmp-combo: reuse register layouts for even more registers
Instead of passing additional registers to qmp_combo_configure_dp_swing(),
reuse qphy_reg_layout and add those registers to register layout maps.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230621153317.1025914-4-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Dmitry Baryshkov
and committed by
Vinod Koul
186ad90a
8447fa7f
+76
-33
+71
-33
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+71
-33
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
···
113
113
114
114
QPHY_DP_PHY_STATUS,
115
115
116
+
QPHY_TX_TX_POL_INV,
117
+
QPHY_TX_TX_DRV_LVL,
118
+
QPHY_TX_TX_EMP_POST1_LVL,
119
+
116
120
/* Keep last to ensure regs_layout arrays are properly initialized */
117
121
QPHY_LAYOUT_SIZE
118
122
};
···
134
130
[QPHY_COM_CMN_STATUS] = QSERDES_V3_COM_CMN_STATUS,
135
131
136
132
[QPHY_DP_PHY_STATUS] = QSERDES_V3_DP_PHY_STATUS,
133
+
134
+
[QPHY_TX_TX_POL_INV] = QSERDES_V3_TX_TX_POL_INV,
135
+
[QPHY_TX_TX_DRV_LVL] = QSERDES_V3_TX_TX_DRV_LVL,
136
+
[QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V3_TX_TX_EMP_POST1_LVL,
137
137
};
138
138
139
139
static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
···
155
147
[QPHY_COM_CMN_STATUS] = QSERDES_V4_COM_CMN_STATUS,
156
148
157
149
[QPHY_DP_PHY_STATUS] = QSERDES_V4_DP_PHY_STATUS,
150
+
151
+
[QPHY_TX_TX_POL_INV] = QSERDES_V4_TX_TX_POL_INV,
152
+
[QPHY_TX_TX_DRV_LVL] = QSERDES_V4_TX_TX_DRV_LVL,
153
+
[QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V4_TX_TX_EMP_POST1_LVL,
154
+
};
155
+
156
+
static const unsigned int qmp_v5_5nm_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
157
+
[QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET,
158
+
[QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL,
159
+
[QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1,
160
+
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL,
161
+
162
+
/* In PCS_USB */
163
+
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL,
164
+
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
165
+
166
+
[QPHY_COM_RESETSM_CNTRL] = QSERDES_V5_COM_RESETSM_CNTRL,
167
+
[QPHY_COM_C_READY_STATUS] = QSERDES_V5_COM_C_READY_STATUS,
168
+
[QPHY_COM_CMN_STATUS] = QSERDES_V5_COM_CMN_STATUS,
169
+
170
+
[QPHY_DP_PHY_STATUS] = QSERDES_V5_DP_PHY_STATUS,
171
+
172
+
[QPHY_TX_TX_POL_INV] = QSERDES_V5_5NM_TX_TX_POL_INV,
173
+
[QPHY_TX_TX_DRV_LVL] = QSERDES_V5_5NM_TX_TX_DRV_LVL,
174
+
[QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL,
158
175
};
159
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160
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static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
···
197
164
[QPHY_COM_CMN_STATUS] = QSERDES_V6_COM_CMN_STATUS,
198
165
199
166
[QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS,
167
+
168
+
[QPHY_TX_TX_POL_INV] = QSERDES_V6_TX_TX_POL_INV,
169
+
[QPHY_TX_TX_DRV_LVL] = QSERDES_V6_TX_TX_DRV_LVL,
170
+
[QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V6_TX_TX_EMP_POST1_LVL,
200
171
};
201
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202
173
static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
···
1685
1648
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1686
1649
.vreg_list = qmp_phy_vreg_l,
1687
1650
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1688
-
.regs = qmp_v45_usb3phy_regs_layout,
1651
+
.regs = qmp_v5_5nm_usb3phy_regs_layout,
1689
1652
};
1690
1653
1691
1654
static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = {
···
1979
1942
qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
1980
1943
}
1981
1944
1982
-
static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp,
1983
-
unsigned int drv_lvl_reg, unsigned int emp_post_reg)
1945
+
static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp)
1984
1946
{
1985
1947
const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
1986
1948
const struct qmp_phy_cfg *cfg = qmp->cfg;
···
2008
1972
voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
2009
1973
pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
2010
1974
2011
-
writel(voltage_swing_cfg, qmp->dp_tx + drv_lvl_reg);
2012
-
writel(pre_emphasis_cfg, qmp->dp_tx + emp_post_reg);
2013
-
writel(voltage_swing_cfg, qmp->dp_tx2 + drv_lvl_reg);
2014
-
writel(pre_emphasis_cfg, qmp->dp_tx2 + emp_post_reg);
1975
+
writel(voltage_swing_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);
1976
+
writel(pre_emphasis_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
1977
+
writel(voltage_swing_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);
1978
+
writel(pre_emphasis_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2015
1979
2016
1980
return 0;
2017
1981
}
···
2021
1985
const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2022
1986
u32 bias_en, drvr_en;
2023
1987
2024
-
if (qmp_combo_configure_dp_swing(qmp, QSERDES_V3_TX_TX_DRV_LVL,
2025
-
QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
1988
+
if (qmp_combo_configure_dp_swing(qmp) < 0)
2026
1989
return;
2027
1990
2028
1991
if (dp_opts->lanes == 1) {
···
2209
2174
2210
2175
static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp)
2211
2176
{
2177
+
const struct qmp_phy_cfg *cfg = qmp->cfg;
2178
+
2212
2179
/* Program default values before writing proper values */
2213
-
writel(0x27, qmp->dp_tx + QSERDES_V4_TX_TX_DRV_LVL);
2214
-
writel(0x27, qmp->dp_tx2 + QSERDES_V4_TX_TX_DRV_LVL);
2180
+
writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2181
+
writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2215
2182
2216
-
writel(0x20, qmp->dp_tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
2217
-
writel(0x20, qmp->dp_tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
2183
+
writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2184
+
writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2218
2185
2219
-
qmp_combo_configure_dp_swing(qmp, QSERDES_V4_TX_TX_DRV_LVL,
2220
-
QSERDES_V4_TX_TX_EMP_POST1_LVL);
2186
+
qmp_combo_configure_dp_swing(qmp);
2221
2187
}
2222
2188
2223
2189
static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp)
···
2362
2326
10000))
2363
2327
return -ETIMEDOUT;
2364
2328
2365
-
writel(0x0a, qmp->dp_tx + QSERDES_V4_TX_TX_POL_INV);
2366
-
writel(0x0a, qmp->dp_tx2 + QSERDES_V4_TX_TX_POL_INV);
2329
+
writel(0x0a, qmp->dp_tx + cfg->regs[QPHY_TX_TX_POL_INV]);
2330
+
writel(0x0a, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_POL_INV]);
2367
2331
2368
-
writel(0x27, qmp->dp_tx + QSERDES_V4_TX_TX_DRV_LVL);
2369
-
writel(0x27, qmp->dp_tx2 + QSERDES_V4_TX_TX_DRV_LVL);
2332
+
writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2333
+
writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2370
2334
2371
-
writel(0x20, qmp->dp_tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
2372
-
writel(0x20, qmp->dp_tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
2335
+
writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2336
+
writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2337
+
2338
+
return 0;
2373
2339
2374
2340
return 0;
2375
2341
}
···
2422
2384
10000))
2423
2385
return -ETIMEDOUT;
2424
2386
2425
-
writel(0x0a, qmp->dp_tx + QSERDES_V5_5NM_TX_TX_POL_INV);
2426
-
writel(0x0a, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TX_POL_INV);
2387
+
writel(0x0a, qmp->dp_tx + cfg->regs[QPHY_TX_TX_POL_INV]);
2388
+
writel(0x0a, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_POL_INV]);
2427
2389
2428
-
writel(0x27, qmp->dp_tx + QSERDES_V5_5NM_TX_TX_DRV_LVL);
2429
-
writel(0x27, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TX_DRV_LVL);
2390
+
writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2391
+
writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2430
2392
2431
-
writel(0x20, qmp->dp_tx + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL);
2432
-
writel(0x20, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL);
2393
+
writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2394
+
writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2433
2395
2434
2396
return 0;
2435
2397
}
···
2480
2442
10000))
2481
2443
return -ETIMEDOUT;
2482
2444
2483
-
writel(0x0a, qmp->dp_tx + QSERDES_V4_TX_TX_POL_INV);
2484
-
writel(0x0a, qmp->dp_tx2 + QSERDES_V4_TX_TX_POL_INV);
2445
+
writel(0x0a, qmp->dp_tx + cfg->regs[QPHY_TX_TX_POL_INV]);
2446
+
writel(0x0a, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_POL_INV]);
2485
2447
2486
-
writel(0x27, qmp->dp_tx + QSERDES_V4_TX_TX_DRV_LVL);
2487
-
writel(0x27, qmp->dp_tx2 + QSERDES_V4_TX_TX_DRV_LVL);
2448
+
writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2449
+
writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2488
2450
2489
-
writel(0x20, qmp->dp_tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
2490
-
writel(0x20, qmp->dp_tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
2451
+
writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2452
+
writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2491
2453
2492
2454
return 0;
2493
2455
}
+3
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h
+3
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h
···
7
7
#define QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_
8
8
9
9
#define QSERDES_V6_TX_CLKBUF_ENABLE 0x08
10
+
#define QSERDES_V6_TX_TX_EMP_POST1_LVL 0x0c
11
+
#define QSERDES_V6_TX_TX_DRV_LVL 0x14
10
12
#define QSERDES_V6_TX_RESET_TSYNC_EN 0x1c
11
13
#define QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN 0x20
12
14
#define QSERDES_V6_TX_TX_BAND 0x24
···
17
15
#define QSERDES_V6_TX_RES_CODE_LANE_RX 0x38
18
16
#define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX 0x3c
19
17
#define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX 0x40
18
+
#define QSERDES_V6_TX_TX_POL_INV 0x5c
20
19
#define QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN 0x60
21
20
#define QSERDES_V6_TX_BIST_PATTERN7 0x7c
22
21
#define QSERDES_V6_TX_LANE_MODE_1 0x84
+2
drivers/phy/qualcomm/phy-qcom-qmp.h
+2
drivers/phy/qualcomm/phy-qcom-qmp.h
···
134
134
#define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10
135
135
#define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14
136
136
137
+
#define QSERDES_V5_DP_PHY_STATUS 0x0dc
138
+
137
139
/* Only for QMP V6 PHY - DP PHY registers */
138
140
#define QSERDES_V6_DP_PHY_AUX_INTERRUPT_STATUS 0x0e0
139
141
#define QSERDES_V6_DP_PHY_STATUS 0x0e4