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phy: qcom: qmp-combo: reuse register layouts for more registers

Instead of passing additional registers to qmp_v456_configure_dp_phy(),
reuse qphy_reg_layout and add those registers to register layout maps.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230621153317.1025914-3-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Dmitry Baryshkov and committed by
Vinod Koul 8447fa7f 6292fd92

+64 -36
+64 -36
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
··· 106 106 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 107 107 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 108 108 QPHY_PCS_POWER_DOWN_CONTROL, 109 + 110 + QPHY_COM_RESETSM_CNTRL, 111 + QPHY_COM_C_READY_STATUS, 112 + QPHY_COM_CMN_STATUS, 113 + 114 + QPHY_DP_PHY_STATUS, 115 + 109 116 /* Keep last to ensure regs_layout arrays are properly initialized */ 110 117 QPHY_LAYOUT_SIZE 111 118 }; ··· 124 117 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, 125 118 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL, 126 119 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR, 120 + 121 + [QPHY_COM_RESETSM_CNTRL] = QSERDES_V3_COM_RESETSM_CNTRL, 122 + [QPHY_COM_C_READY_STATUS] = QSERDES_V3_COM_C_READY_STATUS, 123 + [QPHY_COM_CMN_STATUS] = QSERDES_V3_COM_CMN_STATUS, 124 + 125 + [QPHY_DP_PHY_STATUS] = QSERDES_V3_DP_PHY_STATUS, 127 126 }; 128 127 129 - static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 128 + static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 130 129 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, 131 130 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, 132 131 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, ··· 141 128 /* In PCS_USB */ 142 129 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL, 143 130 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 131 + 132 + [QPHY_COM_RESETSM_CNTRL] = QSERDES_V4_COM_RESETSM_CNTRL, 133 + [QPHY_COM_C_READY_STATUS] = QSERDES_V4_COM_C_READY_STATUS, 134 + [QPHY_COM_CMN_STATUS] = QSERDES_V4_COM_CMN_STATUS, 135 + 136 + [QPHY_DP_PHY_STATUS] = QSERDES_V4_DP_PHY_STATUS, 137 + }; 138 + 139 + static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 140 + [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, 141 + [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, 142 + [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, 143 + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, 144 + 145 + /* In PCS_USB */ 146 + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL, 147 + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 148 + 149 + [QPHY_COM_RESETSM_CNTRL] = QSERDES_V6_COM_RESETSM_CNTRL, 150 + [QPHY_COM_C_READY_STATUS] = QSERDES_V6_COM_C_READY_STATUS, 151 + [QPHY_COM_CMN_STATUS] = QSERDES_V6_COM_CMN_STATUS, 152 + 153 + [QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS, 144 154 }; 145 155 146 156 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { ··· 1600 1564 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1601 1565 .vreg_list = qmp_phy_vreg_l, 1602 1566 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1603 - .regs = qmp_v4_usb3phy_regs_layout, 1567 + .regs = qmp_v45_usb3phy_regs_layout, 1604 1568 .pcs_usb_offset = 0x300, 1605 1569 1606 1570 .has_pwrdn_delay = true, ··· 1648 1612 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1649 1613 .vreg_list = qmp_phy_vreg_l, 1650 1614 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1651 - .regs = qmp_v4_usb3phy_regs_layout, 1615 + .regs = qmp_v45_usb3phy_regs_layout, 1652 1616 }; 1653 1617 1654 1618 static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = { ··· 1738 1702 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1739 1703 .vreg_list = qmp_phy_vreg_l, 1740 1704 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1741 - .regs = qmp_v4_usb3phy_regs_layout, 1705 + .regs = qmp_v45_usb3phy_regs_layout, 1742 1706 .pcs_usb_offset = 0x300, 1743 1707 1744 1708 .has_pwrdn_delay = true, ··· 1788 1752 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1789 1753 .vreg_list = qmp_phy_vreg_l, 1790 1754 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1791 - .regs = qmp_v4_usb3phy_regs_layout, 1755 + .regs = qmp_v45_usb3phy_regs_layout, 1792 1756 1793 1757 .has_pwrdn_delay = true, 1794 1758 }; ··· 1831 1795 .configure_dp_phy = qmp_v6_configure_dp_phy, 1832 1796 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1833 1797 1834 - .regs = qmp_v4_usb3phy_regs_layout, 1798 + .regs = qmp_v6_usb3phy_regs_layout, 1835 1799 .clk_list = qmp_v4_phy_clk_l, 1836 1800 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1837 1801 .reset_list = msm8996_usb3phy_reset_l, ··· 2030 1994 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp) 2031 1995 { 2032 1996 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 1997 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2033 1998 u32 phy_vco_div, status; 2034 1999 unsigned long pixel_freq; 2035 2000 ··· 2071 2034 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2072 2035 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2073 2036 2074 - writel(0x20, qmp->dp_serdes + QSERDES_V3_COM_RESETSM_CNTRL); 2037 + writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); 2075 2038 2076 - if (readl_poll_timeout(qmp->dp_serdes + QSERDES_V3_COM_C_READY_STATUS, 2039 + if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], 2077 2040 status, 2078 2041 ((status & BIT(0)) > 0), 2079 2042 500, ··· 2082 2045 2083 2046 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2084 2047 2085 - if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V3_DP_PHY_STATUS, 2048 + if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2086 2049 status, 2087 2050 ((status & BIT(1)) > 0), 2088 2051 500, ··· 2093 2056 udelay(2000); 2094 2057 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2095 2058 2096 - return readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V3_DP_PHY_STATUS, 2059 + return readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2097 2060 status, 2098 2061 ((status & BIT(1)) > 0), 2099 2062 500, ··· 2185 2148 QSERDES_V4_TX_TX_EMP_POST1_LVL); 2186 2149 } 2187 2150 2188 - static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp, 2189 - unsigned int com_resetm_ctrl_reg, 2190 - unsigned int com_c_ready_status_reg, 2191 - unsigned int com_cmn_status_reg, 2192 - unsigned int dp_phy_status_reg) 2151 + static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp) 2193 2152 { 2194 2153 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2154 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2195 2155 u32 phy_vco_div, status; 2196 2156 unsigned long pixel_freq; 2197 2157 ··· 2233 2199 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2234 2200 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2235 2201 2236 - writel(0x20, qmp->dp_serdes + com_resetm_ctrl_reg); 2202 + writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); 2237 2203 2238 - if (readl_poll_timeout(qmp->dp_serdes + com_c_ready_status_reg, 2204 + if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], 2239 2205 status, 2240 2206 ((status & BIT(0)) > 0), 2241 2207 500, 2242 2208 10000)) 2243 2209 return -ETIMEDOUT; 2244 2210 2245 - if (readl_poll_timeout(qmp->dp_serdes + com_cmn_status_reg, 2211 + if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], 2246 2212 status, 2247 2213 ((status & BIT(0)) > 0), 2248 2214 500, 2249 2215 10000)) 2250 2216 return -ETIMEDOUT; 2251 2217 2252 - if (readl_poll_timeout(qmp->dp_serdes + com_cmn_status_reg, 2218 + if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], 2253 2219 status, 2254 2220 ((status & BIT(1)) > 0), 2255 2221 500, ··· 2258 2224 2259 2225 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2260 2226 2261 - if (readl_poll_timeout(qmp->dp_dp_phy + dp_phy_status_reg, 2227 + if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2262 2228 status, 2263 2229 ((status & BIT(0)) > 0), 2264 2230 500, 2265 2231 10000)) 2266 2232 return -ETIMEDOUT; 2267 2233 2268 - if (readl_poll_timeout(qmp->dp_dp_phy + dp_phy_status_reg, 2234 + if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2269 2235 status, 2270 2236 ((status & BIT(1)) > 0), 2271 2237 500, ··· 2277 2243 2278 2244 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp) 2279 2245 { 2246 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2280 2247 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); 2281 2248 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2282 2249 u32 bias0_en, drvr0_en, bias1_en, drvr1_en; 2283 2250 u32 status; 2284 2251 int ret; 2285 2252 2286 - ret = qmp_v456_configure_dp_phy(qmp, QSERDES_V4_COM_RESETSM_CNTRL, 2287 - QSERDES_V4_COM_C_READY_STATUS, 2288 - QSERDES_V4_COM_CMN_STATUS, 2289 - QSERDES_V4_DP_PHY_STATUS); 2253 + ret = qmp_v456_configure_dp_phy(qmp); 2290 2254 if (ret < 0) 2291 2255 return ret; 2292 2256 ··· 2319 2287 udelay(2000); 2320 2288 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2321 2289 2322 - if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS, 2290 + if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2323 2291 status, 2324 2292 ((status & BIT(1)) > 0), 2325 2293 500, ··· 2340 2308 2341 2309 static int qmp_v5_configure_dp_phy(struct qmp_combo *qmp) 2342 2310 { 2311 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2343 2312 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); 2344 2313 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2345 2314 u32 bias0_en, drvr0_en, bias1_en, drvr1_en; 2346 2315 u32 status; 2347 2316 int ret; 2348 2317 2349 - ret = qmp_v456_configure_dp_phy(qmp, QSERDES_V4_COM_RESETSM_CNTRL, 2350 - QSERDES_V4_COM_C_READY_STATUS, 2351 - QSERDES_V4_COM_CMN_STATUS, 2352 - QSERDES_V4_DP_PHY_STATUS); 2318 + ret = qmp_v456_configure_dp_phy(qmp); 2353 2319 if (ret < 0) 2354 2320 return ret; 2355 2321 ··· 2377 2347 udelay(2000); 2378 2348 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2379 2349 2380 - if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS, 2350 + if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2381 2351 status, 2382 2352 ((status & BIT(1)) > 0), 2383 2353 500, ··· 2398 2368 2399 2369 static int qmp_v6_configure_dp_phy(struct qmp_combo *qmp) 2400 2370 { 2371 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2401 2372 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); 2402 2373 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2403 2374 u32 bias0_en, drvr0_en, bias1_en, drvr1_en; 2404 2375 u32 status; 2405 2376 int ret; 2406 2377 2407 - ret = qmp_v456_configure_dp_phy(qmp, QSERDES_V6_COM_RESETSM_CNTRL, 2408 - QSERDES_V6_COM_C_READY_STATUS, 2409 - QSERDES_V6_COM_CMN_STATUS, 2410 - QSERDES_V6_DP_PHY_STATUS); 2378 + ret = qmp_v456_configure_dp_phy(qmp); 2411 2379 if (ret < 0) 2412 2380 return ret; 2413 2381 ··· 2435 2407 udelay(2000); 2436 2408 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2437 2409 2438 - if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V6_DP_PHY_STATUS, 2410 + if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2439 2411 status, 2440 2412 ((status & BIT(1)) > 0), 2441 2413 500,