Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/a6xx: Rebase GMU register offsets
GMU registers are always at a fixed offset from the GPU base address,
a consistency maintained at least within a given architecture generation.
In A8x family, the base address of the GMU has changed, but the offsets
of the gmu registers remain largely the same. To enable reuse of the gmu
code for A8x chipsets, update the gmu register offsets to be relative
to the GPU's base address instead of GMU's.
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689010/
Message-ID: <20251118-kaana-gpu-support-v4-10-86eeb8e93fb6@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
authored by
Akhil P Oommen
and committed by
Rob Clark
188db3d7
1ef05ef9
+222
-204
+58
-44
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+58
-44
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
···
610
610
writel(value, ptr + (offset << 2));
611
611
}
612
612
613
-
static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
614
-
const char *name);
615
-
616
613
static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
617
614
{
618
615
struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
619
616
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
620
617
struct platform_device *pdev = to_platform_device(gmu->dev);
621
-
void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
618
+
void __iomem *pdcptr = devm_platform_ioremap_resource_byname(pdev, "gmu_pdc");
622
619
u32 seqmem0_drv0_reg = REG_A6XX_RSCC_SEQ_MEM_0_DRV0;
623
620
void __iomem *seqptr = NULL;
624
621
uint32_t pdc_address_offset;
625
622
bool pdc_in_aop = false;
626
623
627
624
if (IS_ERR(pdcptr))
628
-
goto err;
625
+
return;
629
626
630
627
if (adreno_is_a650_family(adreno_gpu) ||
631
628
adreno_is_a7xx(adreno_gpu))
···
635
638
pdc_address_offset = 0x30080;
636
639
637
640
if (!pdc_in_aop) {
638
-
seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
641
+
seqptr = devm_platform_ioremap_resource_byname(pdev, "gmu_pdc_seq");
639
642
if (IS_ERR(seqptr))
640
-
goto err;
643
+
return;
641
644
}
642
645
643
646
/* Disable SDE clock gating */
···
727
730
728
731
/* ensure no writes happen before the uCode is fully written */
729
732
wmb();
730
-
731
-
err:
732
-
if (!IS_ERR_OR_NULL(pdcptr))
733
-
iounmap(pdcptr);
734
-
if (!IS_ERR_OR_NULL(seqptr))
735
-
iounmap(seqptr);
736
733
}
737
734
738
735
/*
···
1812
1821
return 0;
1813
1822
}
1814
1823
1815
-
static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
1816
-
const char *name)
1817
-
{
1818
-
void __iomem *ret;
1819
-
struct resource *res = platform_get_resource_byname(pdev,
1820
-
IORESOURCE_MEM, name);
1821
-
1822
-
if (!res) {
1823
-
DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name);
1824
-
return ERR_PTR(-EINVAL);
1825
-
}
1826
-
1827
-
ret = ioremap(res->start, resource_size(res));
1828
-
if (!ret) {
1829
-
DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name);
1830
-
return ERR_PTR(-EINVAL);
1831
-
}
1832
-
1833
-
return ret;
1834
-
}
1835
-
1836
1824
static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev,
1837
1825
const char *name, irq_handler_t handler)
1838
1826
{
···
1862
1892
{
1863
1893
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1864
1894
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1865
-
struct platform_device *pdev = to_platform_device(gmu->dev);
1866
1895
1867
1896
mutex_lock(&gmu->lock);
1868
1897
if (!gmu->initialized) {
···
1890
1921
qmp_put(gmu->qmp);
1891
1922
1892
1923
iounmap(gmu->mmio);
1893
-
if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
1894
-
iounmap(gmu->rscc);
1895
1924
gmu->mmio = NULL;
1896
1925
gmu->rscc = NULL;
1897
1926
···
1916
1949
return 0;
1917
1950
}
1918
1951
1952
+
static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
1953
+
const char *name, resource_size_t *start)
1954
+
{
1955
+
void __iomem *ret;
1956
+
struct resource *res = platform_get_resource_byname(pdev,
1957
+
IORESOURCE_MEM, name);
1958
+
1959
+
if (!res) {
1960
+
DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name);
1961
+
return ERR_PTR(-EINVAL);
1962
+
}
1963
+
1964
+
ret = ioremap(res->start, resource_size(res));
1965
+
if (!ret) {
1966
+
DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name);
1967
+
return ERR_PTR(-EINVAL);
1968
+
}
1969
+
1970
+
if (start)
1971
+
*start = res->start;
1972
+
1973
+
return ret;
1974
+
}
1975
+
1919
1976
int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
1920
1977
{
1921
1978
struct platform_device *pdev = of_find_device_by_node(node);
1979
+
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1980
+
struct msm_gpu *gpu = &adreno_gpu->base;
1922
1981
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1982
+
resource_size_t start;
1983
+
struct resource *res;
1923
1984
int ret;
1924
1985
1925
1986
if (!pdev)
···
1972
1977
gmu->nr_clocks = ret;
1973
1978
1974
1979
/* Map the GMU registers */
1975
-
gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu");
1980
+
gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu", &start);
1976
1981
if (IS_ERR(gmu->mmio)) {
1977
1982
ret = PTR_ERR(gmu->mmio);
1978
1983
goto err_mmio;
1979
1984
}
1985
+
1986
+
res = platform_get_resource_byname(gpu->pdev, IORESOURCE_MEM, "kgsl_3d0_reg_memory");
1987
+
if (!res) {
1988
+
ret = -EINVAL;
1989
+
goto err_mmio;
1990
+
}
1991
+
1992
+
/* Identify gmu base offset from gpu base address */
1993
+
gmu->mmio_offset = (u32)(start - res->start);
1980
1994
1981
1995
gmu->cxpd = dev_pm_domain_attach_by_name(gmu->dev, "cx");
1982
1996
if (IS_ERR(gmu->cxpd)) {
···
2028
2024
2029
2025
int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
2030
2026
{
2031
-
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
2032
-
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
2033
2027
struct platform_device *pdev = of_find_device_by_node(node);
2028
+
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
2029
+
struct msm_gpu *gpu = &adreno_gpu->base;
2030
+
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
2034
2031
struct device_link *link;
2032
+
resource_size_t start;
2033
+
struct resource *res;
2035
2034
int ret;
2036
2035
2037
2036
if (!pdev)
···
2129
2122
goto err_memory;
2130
2123
2131
2124
/* Map the GMU registers */
2132
-
gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu");
2125
+
gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu", &start);
2133
2126
if (IS_ERR(gmu->mmio)) {
2134
2127
ret = PTR_ERR(gmu->mmio);
2135
2128
goto err_memory;
2136
2129
}
2137
2130
2131
+
res = platform_get_resource_byname(gpu->pdev, IORESOURCE_MEM, "kgsl_3d0_reg_memory");
2132
+
if (!res) {
2133
+
ret = -EINVAL;
2134
+
goto err_mmio;
2135
+
}
2136
+
2137
+
/* Identify gmu base offset from gpu base address */
2138
+
gmu->mmio_offset = (u32)(start - res->start);
2139
+
2138
2140
if (adreno_is_a650_family(adreno_gpu) ||
2139
2141
adreno_is_a7xx(adreno_gpu)) {
2140
-
gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc");
2142
+
gmu->rscc = devm_platform_ioremap_resource_byname(pdev, "rscc");
2141
2143
if (IS_ERR(gmu->rscc)) {
2142
2144
ret = -ENODEV;
2143
2145
goto err_mmio;
···
2224
2208
2225
2209
err_mmio:
2226
2210
iounmap(gmu->mmio);
2227
-
if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
2228
-
iounmap(gmu->rscc);
2229
2211
free_irq(gmu->gmu_irq, gmu);
2230
2212
free_irq(gmu->hfi_irq, gmu);
2231
2213
+12
-8
drivers/gpu/drm/msm/adreno/a6xx_gmu.h
+12
-8
drivers/gpu/drm/msm/adreno/a6xx_gmu.h
···
68
68
struct drm_gpuvm *vm;
69
69
70
70
void __iomem *mmio;
71
+
u32 mmio_offset;
71
72
void __iomem *rscc;
72
73
73
74
int hfi_irq;
···
131
130
unsigned long status;
132
131
};
133
132
133
+
#define GMU_BYTE_OFFSET(gmu, offset) (((offset) << 2) - (gmu)->mmio_offset)
134
+
134
135
static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)
135
136
{
136
-
return readl(gmu->mmio + (offset << 2));
137
+
/* The 'offset' is based on GPU's start address. Adjust it */
138
+
return readl(gmu->mmio + GMU_BYTE_OFFSET(gmu, offset));
137
139
}
138
140
139
141
static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value)
140
142
{
141
-
writel(value, gmu->mmio + (offset << 2));
143
+
writel(value, gmu->mmio + GMU_BYTE_OFFSET(gmu, offset));
142
144
}
143
145
144
146
static inline void
145
147
gmu_write_bulk(struct a6xx_gmu *gmu, u32 offset, const u32 *data, u32 size)
146
148
{
147
-
memcpy_toio(gmu->mmio + (offset << 2), data, size);
149
+
memcpy_toio(gmu->mmio + GMU_BYTE_OFFSET(gmu, offset), data, size);
148
150
wmb();
149
151
}
150
152
···
164
160
{
165
161
u64 val;
166
162
167
-
val = (u64) readl(gmu->mmio + (lo << 2));
168
-
val |= ((u64) readl(gmu->mmio + (hi << 2)) << 32);
163
+
val = gmu_read(gmu, lo);
164
+
val |= ((u64) gmu_read(gmu, hi) << 32);
169
165
170
166
return val;
171
167
}
172
168
173
169
#define gmu_poll_timeout(gmu, addr, val, cond, interval, timeout) \
174
-
readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \
175
-
interval, timeout)
170
+
readl_poll_timeout((gmu)->mmio + (GMU_BYTE_OFFSET(gmu, addr)), val, \
171
+
cond, interval, timeout)
176
172
#define gmu_poll_timeout_atomic(gmu, addr, val, cond, interval, timeout) \
177
-
readl_poll_timeout_atomic((gmu)->mmio + ((addr) << 2), val, cond, \
173
+
readl_poll_timeout_atomic((gmu)->mmio + (GMU_BYTE_OFFSET(gmu, addr)), val, cond, \
178
174
interval, timeout)
179
175
180
176
static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset)
+28
-28
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
+28
-28
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
···
343
343
344
344
static const u32 a6xx_gmu_gx_registers[] = {
345
345
/* GMU GX */
346
-
0x0000, 0x0000, 0x0010, 0x0013, 0x0016, 0x0016, 0x0018, 0x001b,
347
-
0x001e, 0x001e, 0x0020, 0x0023, 0x0026, 0x0026, 0x0028, 0x002b,
348
-
0x002e, 0x002e, 0x0030, 0x0033, 0x0036, 0x0036, 0x0038, 0x003b,
349
-
0x003e, 0x003e, 0x0040, 0x0043, 0x0046, 0x0046, 0x0080, 0x0084,
350
-
0x0100, 0x012b, 0x0140, 0x0140,
346
+
0x1a800, 0x1a800, 0x1a810, 0x1a813, 0x1a816, 0x1a816, 0x1a818, 0x1a81b,
347
+
0x1a81e, 0x1a81e, 0x1a820, 0x1a823, 0x1a826, 0x1a826, 0x1a828, 0x1a82b,
348
+
0x1a82e, 0x1a82e, 0x1a830, 0x1a833, 0x1a836, 0x1a836, 0x1a838, 0x1a83b,
349
+
0x1a83e, 0x1a83e, 0x1a840, 0x1a843, 0x1a846, 0x1a846, 0x1a880, 0x1a884,
350
+
0x1a900, 0x1a92b, 0x1a940, 0x1a940,
351
351
};
352
352
353
353
static const u32 a6xx_gmu_cx_registers[] = {
354
354
/* GMU CX */
355
-
0x4c00, 0x4c07, 0x4c10, 0x4c12, 0x4d00, 0x4d00, 0x4d07, 0x4d0a,
356
-
0x5000, 0x5004, 0x5007, 0x5008, 0x500b, 0x500c, 0x500f, 0x501c,
357
-
0x5024, 0x502a, 0x502d, 0x5030, 0x5040, 0x5053, 0x5087, 0x5089,
358
-
0x50a0, 0x50a2, 0x50a4, 0x50af, 0x50c0, 0x50c3, 0x50d0, 0x50d0,
359
-
0x50e4, 0x50e4, 0x50e8, 0x50ec, 0x5100, 0x5103, 0x5140, 0x5140,
360
-
0x5142, 0x5144, 0x514c, 0x514d, 0x514f, 0x5151, 0x5154, 0x5154,
361
-
0x5157, 0x5158, 0x515d, 0x515d, 0x5162, 0x5162, 0x5164, 0x5165,
362
-
0x5180, 0x5186, 0x5190, 0x519e, 0x51c0, 0x51c0, 0x51c5, 0x51cc,
363
-
0x51e0, 0x51e2, 0x51f0, 0x51f0, 0x5200, 0x5201,
355
+
0x1f400, 0x1f407, 0x1f410, 0x1f412, 0x1f500, 0x1f500, 0x1f507, 0x1f50a,
356
+
0x1f800, 0x1f804, 0x1f807, 0x1f808, 0x1f80b, 0x1f80c, 0x1f80f, 0x1f81c,
357
+
0x1f824, 0x1f82a, 0x1f82d, 0x1f830, 0x1f840, 0x1f853, 0x1f887, 0x1f889,
358
+
0x1f8a0, 0x1f8a2, 0x1f8a4, 0x1f8af, 0x1f8c0, 0x1f8c3, 0x1f8d0, 0x1f8d0,
359
+
0x1f8e4, 0x1f8e4, 0x1f8e8, 0x1f8ec, 0x1f900, 0x1f903, 0x1f940, 0x1f940,
360
+
0x1f942, 0x1f944, 0x1f94c, 0x1f94d, 0x1f94f, 0x1f951, 0x1f954, 0x1f954,
361
+
0x1f957, 0x1f958, 0x1f95d, 0x1f95d, 0x1f962, 0x1f962, 0x1f964, 0x1f965,
362
+
0x1f980, 0x1f986, 0x1f990, 0x1f99e, 0x1f9c0, 0x1f9c0, 0x1f9c5, 0x1f9cc,
363
+
0x1f9e0, 0x1f9e2, 0x1f9f0, 0x1f9f0, 0x1fa00, 0x1fa01,
364
364
/* GMU AO */
365
-
0x9300, 0x9316, 0x9400, 0x9400,
365
+
0x23b00, 0x23b16, 0x23c00, 0x23c00,
366
366
};
367
367
368
368
static const u32 a6xx_gmu_gpucc_registers[] = {
369
369
/* GPU CC */
370
-
0x9800, 0x9812, 0x9840, 0x9852, 0x9c00, 0x9c04, 0x9c07, 0x9c0b,
371
-
0x9c15, 0x9c1c, 0x9c1e, 0x9c2d, 0x9c3c, 0x9c3d, 0x9c3f, 0x9c40,
372
-
0x9c42, 0x9c49, 0x9c58, 0x9c5a, 0x9d40, 0x9d5e, 0xa000, 0xa002,
373
-
0xa400, 0xa402, 0xac00, 0xac02, 0xb000, 0xb002, 0xb400, 0xb402,
374
-
0xb800, 0xb802,
370
+
0x24000, 0x24012, 0x24040, 0x24052, 0x24400, 0x24404, 0x24407, 0x2440b,
371
+
0x24415, 0x2441c, 0x2441e, 0x2442d, 0x2443c, 0x2443d, 0x2443f, 0x24440,
372
+
0x24442, 0x24449, 0x24458, 0x2445a, 0x24540, 0x2455e, 0x24800, 0x24802,
373
+
0x24c00, 0x24c02, 0x25400, 0x25402, 0x25800, 0x25802, 0x25c00, 0x25c02,
374
+
0x26000, 0x26002,
375
375
/* GPU CC ACD */
376
-
0xbc00, 0xbc16, 0xbc20, 0xbc27,
376
+
0x26400, 0x26416, 0x26420, 0x26427,
377
377
};
378
378
379
379
static const u32 a621_gmu_gpucc_registers[] = {
380
380
/* GPU CC */
381
-
0x9800, 0x980e, 0x9c00, 0x9c0e, 0xb000, 0xb004, 0xb400, 0xb404,
382
-
0xb800, 0xb804, 0xbc00, 0xbc05, 0xbc14, 0xbc1d, 0xbc2a, 0xbc30,
383
-
0xbc32, 0xbc32, 0xbc41, 0xbc55, 0xbc66, 0xbc68, 0xbc78, 0xbc7a,
384
-
0xbc89, 0xbc8a, 0xbc9c, 0xbc9e, 0xbca0, 0xbca3, 0xbcb3, 0xbcb5,
385
-
0xbcc5, 0xbcc7, 0xbcd6, 0xbcd8, 0xbce8, 0xbce9, 0xbcf9, 0xbcfc,
386
-
0xbd0b, 0xbd0c, 0xbd1c, 0xbd1e, 0xbd40, 0xbd70, 0xbe00, 0xbe16,
387
-
0xbe20, 0xbe2d,
381
+
0x24000, 0x2400e, 0x24400, 0x2440e, 0x25800, 0x25804, 0x25c00, 0x25c04,
382
+
0x26000, 0x26004, 0x26400, 0x26405, 0x26414, 0x2641d, 0x2642a, 0x26430,
383
+
0x26432, 0x26432, 0x26441, 0x26455, 0x26466, 0x26468, 0x26478, 0x2647a,
384
+
0x26489, 0x2648a, 0x2649c, 0x2649e, 0x264a0, 0x264a3, 0x264b3, 0x264b5,
385
+
0x264c5, 0x264c7, 0x264d6, 0x264d8, 0x264e8, 0x264e9, 0x264f9, 0x264fc,
386
+
0x2650b, 0x2650c, 0x2651c, 0x2651e, 0x26540, 0x26570, 0x26600, 0x26616,
387
+
0x26620, 0x2662d,
388
388
};
389
389
390
390
static const u32 a6xx_gmu_cx_rscc_registers[] = {
+124
-124
drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
+124
-124
drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
···
40
40
<bitfield name="IRQ_MASK_BIT" pos="0" />
41
41
</bitset>
42
42
43
-
<reg32 offset="0x80" name="GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL"/>
44
-
<reg32 offset="0x81" name="GMU_GX_SPTPRAC_POWER_CONTROL"/>
45
-
<reg32 offset="0xc00" name="GMU_CM3_ITCM_START"/>
46
-
<reg32 offset="0x1c00" name="GMU_CM3_DTCM_START"/>
47
-
<reg32 offset="0x23f0" name="GMU_NMI_CONTROL_STATUS"/>
48
-
<reg32 offset="0x23f8" name="GMU_BOOT_SLUMBER_OPTION"/>
49
-
<reg32 offset="0x23f9" name="GMU_GX_VOTE_IDX"/>
50
-
<reg32 offset="0x23fa" name="GMU_MX_VOTE_IDX"/>
51
-
<reg32 offset="0x23fc" name="GMU_DCVS_ACK_OPTION"/>
52
-
<reg32 offset="0x23fd" name="GMU_DCVS_PERF_SETTING"/>
53
-
<reg32 offset="0x23fe" name="GMU_DCVS_BW_SETTING"/>
54
-
<reg32 offset="0x23ff" name="GMU_DCVS_RETURN"/>
55
-
<reg32 offset="0x2bf8" name="GMU_CORE_FW_VERSION">
43
+
<reg32 offset="0x1a880" name="GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL"/>
44
+
<reg32 offset="0x1a881" name="GMU_GX_SPTPRAC_POWER_CONTROL"/>
45
+
<reg32 offset="0x1b400" name="GMU_CM3_ITCM_START"/>
46
+
<reg32 offset="0x1c400" name="GMU_CM3_DTCM_START"/>
47
+
<reg32 offset="0x1cbf0" name="GMU_NMI_CONTROL_STATUS"/>
48
+
<reg32 offset="0x1cbf8" name="GMU_BOOT_SLUMBER_OPTION"/>
49
+
<reg32 offset="0x1cbf9" name="GMU_GX_VOTE_IDX"/>
50
+
<reg32 offset="0x1cbfa" name="GMU_MX_VOTE_IDX"/>
51
+
<reg32 offset="0x1cbfc" name="GMU_DCVS_ACK_OPTION"/>
52
+
<reg32 offset="0x1cbfd" name="GMU_DCVS_PERF_SETTING"/>
53
+
<reg32 offset="0x1cbfe" name="GMU_DCVS_BW_SETTING"/>
54
+
<reg32 offset="0x1cbff" name="GMU_DCVS_RETURN"/>
55
+
<reg32 offset="0x1d3f8" name="GMU_CORE_FW_VERSION">
56
56
<bitfield name="MAJOR" low="28" high="31"/>
57
57
<bitfield name="MINOR" low="16" high="27"/>
58
58
<bitfield name="STEP" low="0" high="15"/>
59
59
</reg32>
60
-
<reg32 offset="0x4c00" name="GMU_ICACHE_CONFIG"/>
61
-
<reg32 offset="0x4c01" name="GMU_DCACHE_CONFIG"/>
62
-
<reg32 offset="0x4c0f" name="GMU_SYS_BUS_CONFIG"/>
63
-
<reg32 offset="0x5000" name="GMU_CM3_SYSRESET"/>
64
-
<reg32 offset="0x5001" name="GMU_CM3_BOOT_CONFIG"/>
65
-
<reg32 offset="0x501a" name="GMU_CM3_FW_BUSY"/>
66
-
<reg32 offset="0x501c" name="GMU_CM3_FW_INIT_RESULT"/>
67
-
<reg32 offset="0x502d" name="GMU_CM3_CFG"/>
68
-
<reg32 offset="0x5040" name="GMU_CX_GMU_POWER_COUNTER_ENABLE"/>
69
-
<reg32 offset="0x5041" name="GMU_CX_GMU_POWER_COUNTER_SELECT_0"/>
70
-
<reg32 offset="0x5042" name="GMU_CX_GMU_POWER_COUNTER_SELECT_1"/>
71
-
<reg32 offset="0x5044" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L"/>
72
-
<reg32 offset="0x5045" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H"/>
73
-
<reg32 offset="0x5046" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L"/>
74
-
<reg32 offset="0x5047" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H"/>
75
-
<reg32 offset="0x5048" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L"/>
76
-
<reg32 offset="0x5049" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H"/>
77
-
<reg32 offset="0x504a" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L"/>
78
-
<reg32 offset="0x504b" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H"/>
79
-
<reg32 offset="0x504c" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L"/>
80
-
<reg32 offset="0x504d" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H"/>
81
-
<reg32 offset="0x504e" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L"/>
82
-
<reg32 offset="0x504f" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H"/>
83
-
<reg32 offset="0x50c0" name="GMU_PWR_COL_INTER_FRAME_CTRL">
60
+
<reg32 offset="0x1f400" name="GMU_ICACHE_CONFIG"/>
61
+
<reg32 offset="0x1f401" name="GMU_DCACHE_CONFIG"/>
62
+
<reg32 offset="0x1f40f" name="GMU_SYS_BUS_CONFIG"/>
63
+
<reg32 offset="0x1f800" name="GMU_CM3_SYSRESET"/>
64
+
<reg32 offset="0x1f801" name="GMU_CM3_BOOT_CONFIG"/>
65
+
<reg32 offset="0x1f81a" name="GMU_CM3_FW_BUSY"/>
66
+
<reg32 offset="0x1f81c" name="GMU_CM3_FW_INIT_RESULT"/>
67
+
<reg32 offset="0x1f82d" name="GMU_CM3_CFG"/>
68
+
<reg32 offset="0x1f840" name="GMU_CX_GMU_POWER_COUNTER_ENABLE"/>
69
+
<reg32 offset="0x1f841" name="GMU_CX_GMU_POWER_COUNTER_SELECT_0"/>
70
+
<reg32 offset="0x1f842" name="GMU_CX_GMU_POWER_COUNTER_SELECT_1"/>
71
+
<reg32 offset="0x1f844" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L"/>
72
+
<reg32 offset="0x1f845" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H"/>
73
+
<reg32 offset="0x1f846" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L"/>
74
+
<reg32 offset="0x1f847" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H"/>
75
+
<reg32 offset="0x1f848" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L"/>
76
+
<reg32 offset="0x1f849" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H"/>
77
+
<reg32 offset="0x1f84a" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L"/>
78
+
<reg32 offset="0x1f84b" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H"/>
79
+
<reg32 offset="0x1f84c" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L"/>
80
+
<reg32 offset="0x1f84d" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H"/>
81
+
<reg32 offset="0x1f84e" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L"/>
82
+
<reg32 offset="0x1f84f" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H"/>
83
+
<reg32 offset="0x1f8c0" name="GMU_PWR_COL_INTER_FRAME_CTRL">
84
84
<bitfield name="IFPC_ENABLE" pos="0" type="boolean"/>
85
85
<bitfield name="HM_POWER_COLLAPSE_ENABLE" pos="1" type="boolean"/>
86
86
<bitfield name="SPTPRAC_POWER_CONTROL_ENABLE" pos="2" type="boolean"/>
87
87
<bitfield name="NUM_PASS_SKIPS" low="10" high="13"/>
88
88
<bitfield name="MIN_PASS_LENGTH" low="14" high="31"/>
89
89
</reg32>
90
-
<reg32 offset="0x50c1" name="GMU_PWR_COL_INTER_FRAME_HYST"/>
91
-
<reg32 offset="0x50c2" name="GMU_PWR_COL_SPTPRAC_HYST"/>
92
-
<reg32 offset="0x50d0" name="GMU_SPTPRAC_PWR_CLK_STATUS">
90
+
<reg32 offset="0x1f8c1" name="GMU_PWR_COL_INTER_FRAME_HYST"/>
91
+
<reg32 offset="0x1f8c2" name="GMU_PWR_COL_SPTPRAC_HYST"/>
92
+
<reg32 offset="0x1f8d0" name="GMU_SPTPRAC_PWR_CLK_STATUS">
93
93
<bitfield name="SPTPRAC_GDSC_POWERING_OFF" pos="0" type="boolean"/>
94
94
<bitfield name="SPTPRAC_GDSC_POWERING_ON" pos="1" type="boolean"/>
95
95
<bitfield name="SPTPRAC_GDSC_POWER_OFF" pos="2" type="boolean"/>
···
99
99
<bitfield name="GX_HM_GDSC_POWER_OFF" pos="6" type="boolean"/>
100
100
<bitfield name="GX_HM_CLK_OFF" pos="7" type="boolean"/>
101
101
</reg32>
102
-
<reg32 offset="0x50d0" name="GMU_SPTPRAC_PWR_CLK_STATUS" variants="A7XX">
102
+
<reg32 offset="0x1f8d0" name="GMU_SPTPRAC_PWR_CLK_STATUS" variants="A7XX-">
103
103
<bitfield name="GX_HM_GDSC_POWER_OFF" pos="0" type="boolean"/>
104
104
<bitfield name="GX_HM_CLK_OFF" pos="1" type="boolean"/>
105
105
</reg32>
106
-
<reg32 offset="0x50e4" name="GMU_GPU_NAP_CTRL">
106
+
<reg32 offset="0x1f8e4" name="GMU_GPU_NAP_CTRL">
107
107
<bitfield name="HW_NAP_ENABLE" pos="0"/>
108
108
<bitfield name="SID" low="4" high="8"/>
109
109
</reg32>
110
-
<reg32 offset="0x50e8" name="GMU_RPMH_CTRL">
110
+
<reg32 offset="0x1f8e8" name="GMU_RPMH_CTRL">
111
111
<bitfield name="RPMH_INTERFACE_ENABLE" pos="0" type="boolean"/>
112
112
<bitfield name="LLC_VOTE_ENABLE" pos="4" type="boolean"/>
113
113
<bitfield name="DDR_VOTE_ENABLE" pos="8" type="boolean"/>
···
119
119
<bitfield name="CX_MIN_VOTE_ENABLE" pos="14" type="boolean"/>
120
120
<bitfield name="GFX_MIN_VOTE_ENABLE" pos="15" type="boolean"/>
121
121
</reg32>
122
-
<reg32 offset="0x50e9" name="GMU_RPMH_HYST_CTRL"/>
123
-
<reg32 offset="0x50ec" name="GPU_GMU_CX_GMU_RPMH_POWER_STATE"/>
124
-
<reg32 offset="0x50f0" name="GPU_GMU_CX_GMU_CX_FAL_INTF"/>
125
-
<reg32 offset="0x50f1" name="GPU_GMU_CX_GMU_CX_FALNEXT_INTF"/>
126
-
<reg32 offset="0x5100" name="GPU_GMU_CX_GMU_PWR_COL_CP_MSG"/>
127
-
<reg32 offset="0x5101" name="GPU_GMU_CX_GMU_PWR_COL_CP_RESP"/>
128
-
<reg32 offset="0x51f0" name="GMU_BOOT_KMD_LM_HANDSHAKE"/>
129
-
<reg32 offset="0x5157" name="GMU_LLM_GLM_SLEEP_CTRL"/>
130
-
<reg32 offset="0x5158" name="GMU_LLM_GLM_SLEEP_STATUS"/>
131
-
<reg32 offset="0x5088" name="GMU_ALWAYS_ON_COUNTER_L"/>
132
-
<reg32 offset="0x5089" name="GMU_ALWAYS_ON_COUNTER_H"/>
133
-
<reg32 offset="0x50c3" name="GMU_GMU_PWR_COL_KEEPALIVE"/>
134
-
<reg32 offset="0x50c4" name="GMU_PWR_COL_PREEMPT_KEEPALIVE"/>
135
-
<reg32 offset="0x5180" name="GMU_HFI_CTRL_STATUS"/>
136
-
<reg32 offset="0x5181" name="GMU_HFI_VERSION_INFO"/>
137
-
<reg32 offset="0x5182" name="GMU_HFI_SFR_ADDR"/>
138
-
<reg32 offset="0x5183" name="GMU_HFI_MMAP_ADDR"/>
139
-
<reg32 offset="0x5184" name="GMU_HFI_QTBL_INFO"/>
140
-
<reg32 offset="0x5185" name="GMU_HFI_QTBL_ADDR"/>
141
-
<reg32 offset="0x5186" name="GMU_HFI_CTRL_INIT"/>
142
-
<reg32 offset="0x5190" name="GMU_GMU2HOST_INTR_SET"/>
143
-
<reg32 offset="0x5191" name="GMU_GMU2HOST_INTR_CLR"/>
144
-
<reg32 offset="0x5192" name="GMU_GMU2HOST_INTR_INFO">
122
+
<reg32 offset="0x1f8e9" name="GMU_RPMH_HYST_CTRL"/>
123
+
<reg32 offset="0x1f8ec" name="GPU_GMU_CX_GMU_RPMH_POWER_STATE"/>
124
+
<reg32 offset="0x1f8f0" name="GPU_GMU_CX_GMU_CX_FAL_INTF"/>
125
+
<reg32 offset="0x1f8f1" name="GPU_GMU_CX_GMU_CX_FALNEXT_INTF"/>
126
+
<reg32 offset="0x1f900" name="GPU_GMU_CX_GMU_PWR_COL_CP_MSG"/>
127
+
<reg32 offset="0x1f901" name="GPU_GMU_CX_GMU_PWR_COL_CP_RESP"/>
128
+
<reg32 offset="0x1f9f0" name="GMU_BOOT_KMD_LM_HANDSHAKE"/>
129
+
<reg32 offset="0x1f957" name="GMU_LLM_GLM_SLEEP_CTRL"/>
130
+
<reg32 offset="0x1f958" name="GMU_LLM_GLM_SLEEP_STATUS"/>
131
+
<reg32 offset="0x1f888" name="GMU_ALWAYS_ON_COUNTER_L"/>
132
+
<reg32 offset="0x1f889" name="GMU_ALWAYS_ON_COUNTER_H"/>
133
+
<reg32 offset="0x1f8c3" name="GMU_GMU_PWR_COL_KEEPALIVE"/>
134
+
<reg32 offset="0x1f8c4" name="GMU_PWR_COL_PREEMPT_KEEPALIVE"/>
135
+
<reg32 offset="0x1f980" name="GMU_HFI_CTRL_STATUS"/>
136
+
<reg32 offset="0x1f981" name="GMU_HFI_VERSION_INFO"/>
137
+
<reg32 offset="0x1f982" name="GMU_HFI_SFR_ADDR"/>
138
+
<reg32 offset="0x1f983" name="GMU_HFI_MMAP_ADDR"/>
139
+
<reg32 offset="0x1f984" name="GMU_HFI_QTBL_INFO"/>
140
+
<reg32 offset="0x1f985" name="GMU_HFI_QTBL_ADDR"/>
141
+
<reg32 offset="0x1f986" name="GMU_HFI_CTRL_INIT"/>
142
+
<reg32 offset="0x1f990" name="GMU_GMU2HOST_INTR_SET"/>
143
+
<reg32 offset="0x1f991" name="GMU_GMU2HOST_INTR_CLR"/>
144
+
<reg32 offset="0x1f992" name="GMU_GMU2HOST_INTR_INFO">
145
145
<bitfield name="MSGQ" pos="0" type="boolean"/>
146
146
<bitfield name="CM3_FAULT" pos="23" type="boolean"/>
147
147
</reg32>
148
-
<reg32 offset="0x5193" name="GMU_GMU2HOST_INTR_MASK"/>
149
-
<reg32 offset="0x5194" name="GMU_HOST2GMU_INTR_SET"/>
150
-
<reg32 offset="0x5195" name="GMU_HOST2GMU_INTR_CLR"/>
151
-
<reg32 offset="0x5196" name="GMU_HOST2GMU_INTR_RAW_INFO"/>
152
-
<reg32 offset="0x5197" name="GMU_HOST2GMU_INTR_EN_0"/>
153
-
<reg32 offset="0x5198" name="GMU_HOST2GMU_INTR_EN_1"/>
154
-
<reg32 offset="0x5199" name="GMU_HOST2GMU_INTR_EN_2"/>
155
-
<reg32 offset="0x519a" name="GMU_HOST2GMU_INTR_EN_3"/>
156
-
<reg32 offset="0x519b" name="GMU_HOST2GMU_INTR_INFO_0"/>
157
-
<reg32 offset="0x519c" name="GMU_HOST2GMU_INTR_INFO_1"/>
158
-
<reg32 offset="0x519d" name="GMU_HOST2GMU_INTR_INFO_2"/>
159
-
<reg32 offset="0x519e" name="GMU_HOST2GMU_INTR_INFO_3"/>
160
-
<reg32 offset="0x51c5" name="GMU_GENERAL_0"/>
161
-
<reg32 offset="0x51c6" name="GMU_GENERAL_1"/>
162
-
<reg32 offset="0x51cb" name="GMU_GENERAL_6"/>
163
-
<reg32 offset="0x51cc" name="GMU_GENERAL_7"/>
164
-
<reg32 offset="0x51cd" name="GMU_GENERAL_8" variants="A7XX"/>
165
-
<reg32 offset="0x51ce" name="GMU_GENERAL_9" variants="A7XX"/>
166
-
<reg32 offset="0x51cf" name="GMU_GENERAL_10" variants="A7XX"/>
167
-
<reg32 offset="0x515d" name="GMU_ISENSE_CTRL"/>
168
-
<reg32 offset="0x8920" name="GPU_CS_ENABLE_REG"/>
169
-
<reg32 offset="0x515d" name="GPU_GMU_CX_GMU_ISENSE_CTRL"/>
170
-
<reg32 offset="0x8578" name="GPU_CS_AMP_CALIBRATION_CONTROL3"/>
171
-
<reg32 offset="0x8558" name="GPU_CS_AMP_CALIBRATION_CONTROL2"/>
172
-
<reg32 offset="0x8580" name="GPU_CS_A_SENSOR_CTRL_0"/>
173
-
<reg32 offset="0x27ada" name="GPU_CS_A_SENSOR_CTRL_2"/>
174
-
<reg32 offset="0x881a" name="GPU_CS_SENSOR_GENERAL_STATUS"/>
175
-
<reg32 offset="0x8957" name="GPU_CS_AMP_CALIBRATION_CONTROL1"/>
176
-
<reg32 offset="0x881a" name="GPU_CS_SENSOR_GENERAL_STATUS"/>
177
-
<reg32 offset="0x881d" name="GPU_CS_AMP_CALIBRATION_STATUS1_0"/>
178
-
<reg32 offset="0x881f" name="GPU_CS_AMP_CALIBRATION_STATUS1_2"/>
179
-
<reg32 offset="0x8821" name="GPU_CS_AMP_CALIBRATION_STATUS1_4"/>
180
-
<reg32 offset="0x8965" name="GPU_CS_AMP_CALIBRATION_DONE"/>
181
-
<reg32 offset="0x896d" name="GPU_CS_AMP_PERIOD_CTRL"/>
182
-
<reg32 offset="0x8965" name="GPU_CS_AMP_CALIBRATION_DONE"/>
183
-
<reg32 offset="0x514d" name="GPU_GMU_CX_GMU_PWR_THRESHOLD"/>
184
-
<reg32 offset="0x9303" name="GMU_AO_INTERRUPT_EN"/>
185
-
<reg32 offset="0x9304" name="GMU_AO_HOST_INTERRUPT_CLR"/>
186
-
<reg32 offset="0x9305" name="GMU_AO_HOST_INTERRUPT_STATUS">
148
+
<reg32 offset="0x1f993" name="GMU_GMU2HOST_INTR_MASK"/>
149
+
<reg32 offset="0x1f994" name="GMU_HOST2GMU_INTR_SET"/>
150
+
<reg32 offset="0x1f995" name="GMU_HOST2GMU_INTR_CLR"/>
151
+
<reg32 offset="0x1f996" name="GMU_HOST2GMU_INTR_RAW_INFO"/>
152
+
<reg32 offset="0x1f997" name="GMU_HOST2GMU_INTR_EN_0"/>
153
+
<reg32 offset="0x1f998" name="GMU_HOST2GMU_INTR_EN_1"/>
154
+
<reg32 offset="0x1f999" name="GMU_HOST2GMU_INTR_EN_2"/>
155
+
<reg32 offset="0x1f99a" name="GMU_HOST2GMU_INTR_EN_3"/>
156
+
<reg32 offset="0x1f99b" name="GMU_HOST2GMU_INTR_INFO_0"/>
157
+
<reg32 offset="0x1f99c" name="GMU_HOST2GMU_INTR_INFO_1"/>
158
+
<reg32 offset="0x1f99d" name="GMU_HOST2GMU_INTR_INFO_2"/>
159
+
<reg32 offset="0x1f99e" name="GMU_HOST2GMU_INTR_INFO_3"/>
160
+
<reg32 offset="0x1f9c5" name="GMU_GENERAL_0"/>
161
+
<reg32 offset="0x1f9c6" name="GMU_GENERAL_1"/>
162
+
<reg32 offset="0x1f9cb" name="GMU_GENERAL_6"/>
163
+
<reg32 offset="0x1f9cc" name="GMU_GENERAL_7"/>
164
+
<reg32 offset="0x1f9cd" name="GMU_GENERAL_8" variants="A7XX"/>
165
+
<reg32 offset="0x1f9ce" name="GMU_GENERAL_9" variants="A7XX"/>
166
+
<reg32 offset="0x1f9cf" name="GMU_GENERAL_10" variants="A7XX"/>
167
+
<reg32 offset="0x1f95d" name="GMU_ISENSE_CTRL"/>
168
+
<reg32 offset="0x23120" name="GPU_CS_ENABLE_REG"/>
169
+
<reg32 offset="0x1f95d" name="GPU_GMU_CX_GMU_ISENSE_CTRL"/>
170
+
<reg32 offset="0x22d78" name="GPU_CS_AMP_CALIBRATION_CONTROL3"/>
171
+
<reg32 offset="0x22d58" name="GPU_CS_AMP_CALIBRATION_CONTROL2"/>
172
+
<reg32 offset="0x22d80" name="GPU_CS_A_SENSOR_CTRL_0"/>
173
+
<reg32 offset="0x422da" name="GPU_CS_A_SENSOR_CTRL_2"/>
174
+
<reg32 offset="0x2301a" name="GPU_CS_SENSOR_GENERAL_STATUS"/>
175
+
<reg32 offset="0x23157" name="GPU_CS_AMP_CALIBRATION_CONTROL1"/>
176
+
<reg32 offset="0x2301a" name="GPU_CS_SENSOR_GENERAL_STATUS"/>
177
+
<reg32 offset="0x2301d" name="GPU_CS_AMP_CALIBRATION_STATUS1_0"/>
178
+
<reg32 offset="0x2301f" name="GPU_CS_AMP_CALIBRATION_STATUS1_2"/>
179
+
<reg32 offset="0x23021" name="GPU_CS_AMP_CALIBRATION_STATUS1_4"/>
180
+
<reg32 offset="0x23165" name="GPU_CS_AMP_CALIBRATION_DONE"/>
181
+
<reg32 offset="0x2316d" name="GPU_CS_AMP_PERIOD_CTRL"/>
182
+
<reg32 offset="0x23165" name="GPU_CS_AMP_CALIBRATION_DONE"/>
183
+
<reg32 offset="0x1f94d" name="GPU_GMU_CX_GMU_PWR_THRESHOLD"/>
184
+
<reg32 offset="0x23b03" name="GMU_AO_INTERRUPT_EN"/>
185
+
<reg32 offset="0x23b04" name="GMU_AO_HOST_INTERRUPT_CLR"/>
186
+
<reg32 offset="0x23b05" name="GMU_AO_HOST_INTERRUPT_STATUS">
187
187
<bitfield name="WDOG_BITE" pos="0" type="boolean"/>
188
188
<bitfield name="RSCC_COMP" pos="1" type="boolean"/>
189
189
<bitfield name="VDROOP" pos="2" type="boolean"/>
···
191
191
<bitfield name="DBD_WAKEUP" pos="4" type="boolean"/>
192
192
<bitfield name="HOST_AHB_BUS_ERROR" pos="5" type="boolean"/>
193
193
</reg32>
194
-
<reg32 offset="0x9306" name="GMU_AO_HOST_INTERRUPT_MASK"/>
195
-
<reg32 offset="0x9309" name="GPU_GMU_AO_GMU_CGC_MODE_CNTL"/>
196
-
<reg32 offset="0x930a" name="GPU_GMU_AO_GMU_CGC_DELAY_CNTL"/>
197
-
<reg32 offset="0x930b" name="GPU_GMU_AO_GMU_CGC_HYST_CNTL"/>
198
-
<reg32 offset="0x930c" name="GPU_GMU_AO_GPU_CX_BUSY_STATUS">
194
+
<reg32 offset="0x23b06" name="GMU_AO_HOST_INTERRUPT_MASK"/>
195
+
<reg32 offset="0x23b09" name="GPU_GMU_AO_GMU_CGC_MODE_CNTL"/>
196
+
<reg32 offset="0x23b0a" name="GPU_GMU_AO_GMU_CGC_DELAY_CNTL"/>
197
+
<reg32 offset="0x23b0b" name="GPU_GMU_AO_GMU_CGC_HYST_CNTL"/>
198
+
<reg32 offset="0x23b0c" name="GPU_GMU_AO_GPU_CX_BUSY_STATUS">
199
199
<bitfield name = "GPUBUSYIGNAHB" pos="23" type="boolean"/>
200
200
</reg32>
201
-
<reg32 offset="0x930d" name="GPU_GMU_AO_GPU_CX_BUSY_STATUS2"/>
202
-
<reg32 offset="0x930e" name="GPU_GMU_AO_GPU_CX_BUSY_MASK"/>
203
-
<reg32 offset="0x9310" name="GMU_AO_AHB_FENCE_CTRL"/>
204
-
<reg32 offset="0x9313" name="GMU_AHB_FENCE_STATUS"/>
205
-
<reg32 offset="0x9314" name="GMU_AHB_FENCE_STATUS_CLR"/>
206
-
<reg32 offset="0x9315" name="GMU_RBBM_INT_UNMASKED_STATUS"/>
207
-
<reg32 offset="0x9316" name="GMU_AO_SPARE_CNTL"/>
208
-
<reg32 offset="0x9307" name="GMU_RSCC_CONTROL_REQ"/>
209
-
<reg32 offset="0x9308" name="GMU_RSCC_CONTROL_ACK"/>
210
-
<reg32 offset="0x9311" name="GMU_AHB_FENCE_RANGE_0"/>
211
-
<reg32 offset="0x9312" name="GMU_AHB_FENCE_RANGE_1"/>
212
-
<reg32 offset="0x9c03" name="GPU_CC_GX_GDSCR"/>
213
-
<reg32 offset="0x9d42" name="GPU_CC_GX_DOMAIN_MISC"/>
214
-
<reg32 offset="0xc001" name="GPU_CPR_FSM_CTL"/>
201
+
<reg32 offset="0x23b0d" name="GPU_GMU_AO_GPU_CX_BUSY_STATUS2"/>
202
+
<reg32 offset="0x23b0e" name="GPU_GMU_AO_GPU_CX_BUSY_MASK"/>
203
+
<reg32 offset="0x23b10" name="GMU_AO_AHB_FENCE_CTRL"/>
204
+
<reg32 offset="0x23b13" name="GMU_AHB_FENCE_STATUS"/>
205
+
<reg32 offset="0x23b14" name="GMU_AHB_FENCE_STATUS_CLR"/>
206
+
<reg32 offset="0x23b15" name="GMU_RBBM_INT_UNMASKED_STATUS"/>
207
+
<reg32 offset="0x23b16" name="GMU_AO_SPARE_CNTL"/>
208
+
<reg32 offset="0x23b07" name="GMU_RSCC_CONTROL_REQ"/>
209
+
<reg32 offset="0x23b08" name="GMU_RSCC_CONTROL_ACK"/>
210
+
<reg32 offset="0x23b11" name="GMU_AHB_FENCE_RANGE_0"/>
211
+
<reg32 offset="0x23b12" name="GMU_AHB_FENCE_RANGE_1"/>
212
+
<reg32 offset="0x24403" name="GPU_CC_GX_GDSCR"/>
213
+
<reg32 offset="0x24542" name="GPU_CC_GX_DOMAIN_MISC"/>
214
+
<reg32 offset="0x26801" name="GPU_CPR_FSM_CTL"/>
215
215
216
216
<!-- starts at offset 0x8c00 on most gpus -->
217
217
<reg32 offset="0x0004" name="GPU_RSCC_RSC_STATUS0_DRV0"/>