scsi: elx: libefc_sli: Data structures and defines for mbox commands

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drivers

scsi

elx

libefc_sli

sli4.h

+1637

drivers/scsi/elx/libefc_sli/sli4.h

··· 1990 1990 SLI4_ELS_REQUEST64_CMD_FABRIC = 0x0d, 1991 1991 }; 1992 1992 1993 + #define SLI_PAGE_SIZE SZ_4K 1994 + 1995 + #define SLI4_BMBX_TIMEOUT_MSEC 30000 1996 + #define SLI4_FW_READY_TIMEOUT_MSEC 30000 1997 + 1998 + #define SLI4_BMBX_DELAY_US 1000 /* 1 ms */ 1999 + #define SLI4_INIT_PORT_DELAY_US 10000 /* 10 ms */ 2000 + 2001 + static inline u32 2002 + sli_page_count(size_t bytes, u32 page_size) 2003 + { 2004 + if (!page_size) 2005 + return 0; 2006 + 2007 + return (bytes + (page_size - 1)) >> __ffs(page_size); 2008 + } 2009 + 2010 + /************************************************************************* 2011 + * SLI-4 mailbox command formats and definitions 2012 + */ 2013 + 2014 + struct sli4_mbox_command_header { 2015 + u8 resvd0; 2016 + u8 command; 2017 + __le16 status; /* Port writes to indicate success/fail */ 2018 + }; 2019 + 2020 + enum sli4_mbx_cmd_value { 2021 + SLI4_MBX_CMD_CONFIG_LINK = 0x07, 2022 + SLI4_MBX_CMD_DUMP = 0x17, 2023 + SLI4_MBX_CMD_DOWN_LINK = 0x06, 2024 + SLI4_MBX_CMD_INIT_LINK = 0x05, 2025 + SLI4_MBX_CMD_INIT_VFI = 0xa3, 2026 + SLI4_MBX_CMD_INIT_VPI = 0xa4, 2027 + SLI4_MBX_CMD_POST_XRI = 0xa7, 2028 + SLI4_MBX_CMD_RELEASE_XRI = 0xac, 2029 + SLI4_MBX_CMD_READ_CONFIG = 0x0b, 2030 + SLI4_MBX_CMD_READ_STATUS = 0x0e, 2031 + SLI4_MBX_CMD_READ_NVPARMS = 0x02, 2032 + SLI4_MBX_CMD_READ_REV = 0x11, 2033 + SLI4_MBX_CMD_READ_LNK_STAT = 0x12, 2034 + SLI4_MBX_CMD_READ_SPARM64 = 0x8d, 2035 + SLI4_MBX_CMD_READ_TOPOLOGY = 0x95, 2036 + SLI4_MBX_CMD_REG_FCFI = 0xa0, 2037 + SLI4_MBX_CMD_REG_FCFI_MRQ = 0xaf, 2038 + SLI4_MBX_CMD_REG_RPI = 0x93, 2039 + SLI4_MBX_CMD_REG_RX_RQ = 0xa6, 2040 + SLI4_MBX_CMD_REG_VFI = 0x9f, 2041 + SLI4_MBX_CMD_REG_VPI = 0x96, 2042 + SLI4_MBX_CMD_RQST_FEATURES = 0x9d, 2043 + SLI4_MBX_CMD_SLI_CONFIG = 0x9b, 2044 + SLI4_MBX_CMD_UNREG_FCFI = 0xa2, 2045 + SLI4_MBX_CMD_UNREG_RPI = 0x14, 2046 + SLI4_MBX_CMD_UNREG_VFI = 0xa1, 2047 + SLI4_MBX_CMD_UNREG_VPI = 0x97, 2048 + SLI4_MBX_CMD_WRITE_NVPARMS = 0x03, 2049 + SLI4_MBX_CMD_CFG_AUTO_XFER_RDY = 0xad, 2050 + }; 2051 + 2052 + enum sli4_mbx_status { 2053 + SLI4_MBX_STATUS_SUCCESS = 0x0000, 2054 + SLI4_MBX_STATUS_FAILURE = 0x0001, 2055 + SLI4_MBX_STATUS_RPI_NOT_REG = 0x1400, 2056 + }; 2057 + 2058 + /* CONFIG_LINK - configure link-oriented parameters, 2059 + * such as default N_Port_ID address and various timers 2060 + */ 2061 + enum sli4_cmd_config_link_flags { 2062 + SLI4_CFG_LINK_BBSCN = 0xf00, 2063 + SLI4_CFG_LINK_CSCN = 0x1000, 2064 + }; 2065 + 2066 + struct sli4_cmd_config_link { 2067 + struct sli4_mbox_command_header hdr; 2068 + u8 maxbbc; 2069 + u8 rsvd5; 2070 + u8 rsvd6; 2071 + u8 rsvd7; 2072 + u8 alpa; 2073 + __le16 n_port_id; 2074 + u8 rsvd11; 2075 + __le32 rsvd12; 2076 + __le32 e_d_tov; 2077 + __le32 lp_tov; 2078 + __le32 r_a_tov; 2079 + __le32 r_t_tov; 2080 + __le32 al_tov; 2081 + __le32 rsvd36; 2082 + __le32 bbscn_dword; 2083 + }; 2084 + 2085 + #define SLI4_DUMP4_TYPE 0xf 2086 + 2087 + #define SLI4_WKI_TAG_SAT_TEM 0x1040 2088 + 2089 + struct sli4_cmd_dump4 { 2090 + struct sli4_mbox_command_header hdr; 2091 + __le32 type_dword; 2092 + __le16 wki_selection; 2093 + __le16 rsvd10; 2094 + __le32 rsvd12; 2095 + __le32 returned_byte_cnt; 2096 + __le32 resp_data[59]; 2097 + }; 2098 + 2099 + /* INIT_LINK - initialize the link for a FC port */ 2100 + enum sli4_init_link_flags { 2101 + SLI4_INIT_LINK_F_LOOPBACK = 1 << 0, 2102 + 2103 + SLI4_INIT_LINK_F_P2P_ONLY = 1 << 1, 2104 + SLI4_INIT_LINK_F_FCAL_ONLY = 2 << 1, 2105 + SLI4_INIT_LINK_F_FCAL_FAIL_OVER = 0 << 1, 2106 + SLI4_INIT_LINK_F_P2P_FAIL_OVER = 1 << 1, 2107 + 2108 + SLI4_INIT_LINK_F_UNFAIR = 1 << 6, 2109 + SLI4_INIT_LINK_F_NO_LIRP = 1 << 7, 2110 + SLI4_INIT_LINK_F_LOOP_VALID_CHK = 1 << 8, 2111 + SLI4_INIT_LINK_F_NO_LISA = 1 << 9, 2112 + SLI4_INIT_LINK_F_FAIL_OVER = 1 << 10, 2113 + SLI4_INIT_LINK_F_FIXED_SPEED = 1 << 11, 2114 + SLI4_INIT_LINK_F_PICK_HI_ALPA = 1 << 15, 2115 + 2116 + }; 2117 + 2118 + enum sli4_fc_link_speed { 2119 + SLI4_LINK_SPEED_1G = 1, 2120 + SLI4_LINK_SPEED_2G, 2121 + SLI4_LINK_SPEED_AUTO_1_2, 2122 + SLI4_LINK_SPEED_4G, 2123 + SLI4_LINK_SPEED_AUTO_4_1, 2124 + SLI4_LINK_SPEED_AUTO_4_2, 2125 + SLI4_LINK_SPEED_AUTO_4_2_1, 2126 + SLI4_LINK_SPEED_8G, 2127 + SLI4_LINK_SPEED_AUTO_8_1, 2128 + SLI4_LINK_SPEED_AUTO_8_2, 2129 + SLI4_LINK_SPEED_AUTO_8_2_1, 2130 + SLI4_LINK_SPEED_AUTO_8_4, 2131 + SLI4_LINK_SPEED_AUTO_8_4_1, 2132 + SLI4_LINK_SPEED_AUTO_8_4_2, 2133 + SLI4_LINK_SPEED_10G, 2134 + SLI4_LINK_SPEED_16G, 2135 + SLI4_LINK_SPEED_AUTO_16_8_4, 2136 + SLI4_LINK_SPEED_AUTO_16_8, 2137 + SLI4_LINK_SPEED_32G, 2138 + SLI4_LINK_SPEED_AUTO_32_16_8, 2139 + SLI4_LINK_SPEED_AUTO_32_16, 2140 + SLI4_LINK_SPEED_64G, 2141 + SLI4_LINK_SPEED_AUTO_64_32_16, 2142 + SLI4_LINK_SPEED_AUTO_64_32, 2143 + SLI4_LINK_SPEED_128G, 2144 + SLI4_LINK_SPEED_AUTO_128_64_32, 2145 + SLI4_LINK_SPEED_AUTO_128_64, 2146 + }; 2147 + 2148 + struct sli4_cmd_init_link { 2149 + struct sli4_mbox_command_header hdr; 2150 + __le32 sel_reset_al_pa_dword; 2151 + __le32 flags0; 2152 + __le32 link_speed_sel_code; 2153 + }; 2154 + 2155 + /* INIT_VFI - initialize the VFI resource */ 2156 + enum sli4_init_vfi_flags { 2157 + SLI4_INIT_VFI_FLAG_VP = 0x1000, 2158 + SLI4_INIT_VFI_FLAG_VF = 0x2000, 2159 + SLI4_INIT_VFI_FLAG_VT = 0x4000, 2160 + SLI4_INIT_VFI_FLAG_VR = 0x8000, 2161 + 2162 + SLI4_INIT_VFI_VFID = 0x1fff, 2163 + SLI4_INIT_VFI_PRI = 0xe000, 2164 + 2165 + SLI4_INIT_VFI_HOP_COUNT = 0xff000000, 2166 + }; 2167 + 2168 + struct sli4_cmd_init_vfi { 2169 + struct sli4_mbox_command_header hdr; 2170 + __le16 vfi; 2171 + __le16 flags0_word; 2172 + __le16 fcfi; 2173 + __le16 vpi; 2174 + __le32 vf_id_pri_dword; 2175 + __le32 hop_cnt_dword; 2176 + }; 2177 + 2178 + /* INIT_VPI - initialize the VPI resource */ 2179 + struct sli4_cmd_init_vpi { 2180 + struct sli4_mbox_command_header hdr; 2181 + __le16 vpi; 2182 + __le16 vfi; 2183 + }; 2184 + 2185 + /* POST_XRI - post XRI resources to the SLI Port */ 2186 + enum sli4_post_xri_flags { 2187 + SLI4_POST_XRI_COUNT = 0xfff, 2188 + SLI4_POST_XRI_FLAG_ENX = 0x1000, 2189 + SLI4_POST_XRI_FLAG_DL = 0x2000, 2190 + SLI4_POST_XRI_FLAG_DI = 0x4000, 2191 + SLI4_POST_XRI_FLAG_VAL = 0x8000, 2192 + }; 2193 + 2194 + struct sli4_cmd_post_xri { 2195 + struct sli4_mbox_command_header hdr; 2196 + __le16 xri_base; 2197 + __le16 xri_count_flags; 2198 + }; 2199 + 2200 + /* RELEASE_XRI - Release XRI resources from the SLI Port */ 2201 + enum sli4_release_xri_flags { 2202 + SLI4_RELEASE_XRI_REL_XRI_CNT = 0x1f, 2203 + SLI4_RELEASE_XRI_COUNT = 0x1f, 2204 + }; 2205 + 2206 + struct sli4_cmd_release_xri { 2207 + struct sli4_mbox_command_header hdr; 2208 + __le16 rel_xri_count_word; 2209 + __le16 xri_count_word; 2210 + 2211 + struct { 2212 + __le16 xri_tag0; 2213 + __le16 xri_tag1; 2214 + } xri_tbl[62]; 2215 + }; 2216 + 2217 + /* READ_CONFIG - read SLI port configuration parameters */ 2218 + struct sli4_cmd_read_config { 2219 + struct sli4_mbox_command_header hdr; 2220 + }; 2221 + 2222 + enum sli4_read_cfg_resp_flags { 2223 + SLI4_READ_CFG_RESP_RESOURCE_EXT = 0x80000000, /* DW1 */ 2224 + SLI4_READ_CFG_RESP_TOPOLOGY = 0xff000000, /* DW2 */ 2225 + }; 2226 + 2227 + enum sli4_read_cfg_topo { 2228 + SLI4_READ_CFG_TOPO_FC = 0x1, /* FC topology unknown */ 2229 + SLI4_READ_CFG_TOPO_NON_FC_AL = 0x2, /* FC point-to-point or fabric */ 2230 + SLI4_READ_CFG_TOPO_FC_AL = 0x3, /* FC-AL topology */ 2231 + }; 2232 + 2233 + /* Link Module Type */ 2234 + enum sli4_read_cfg_lmt { 2235 + SLI4_LINK_MODULE_TYPE_1GB = 0x0004, 2236 + SLI4_LINK_MODULE_TYPE_2GB = 0x0008, 2237 + SLI4_LINK_MODULE_TYPE_4GB = 0x0040, 2238 + SLI4_LINK_MODULE_TYPE_8GB = 0x0080, 2239 + SLI4_LINK_MODULE_TYPE_16GB = 0x0200, 2240 + SLI4_LINK_MODULE_TYPE_32GB = 0x0400, 2241 + SLI4_LINK_MODULE_TYPE_64GB = 0x0800, 2242 + SLI4_LINK_MODULE_TYPE_128GB = 0x1000, 2243 + }; 2244 + 2245 + struct sli4_rsp_read_config { 2246 + struct sli4_mbox_command_header hdr; 2247 + __le32 ext_dword; 2248 + __le32 topology_dword; 2249 + __le32 resvd8; 2250 + __le16 e_d_tov; 2251 + __le16 resvd14; 2252 + __le32 resvd16; 2253 + __le16 r_a_tov; 2254 + __le16 resvd22; 2255 + __le32 resvd24; 2256 + __le32 resvd28; 2257 + __le16 lmt; 2258 + __le16 resvd34; 2259 + __le32 resvd36; 2260 + __le32 resvd40; 2261 + __le16 xri_base; 2262 + __le16 xri_count; 2263 + __le16 rpi_base; 2264 + __le16 rpi_count; 2265 + __le16 vpi_base; 2266 + __le16 vpi_count; 2267 + __le16 vfi_base; 2268 + __le16 vfi_count; 2269 + __le16 resvd60; 2270 + __le16 fcfi_count; 2271 + __le16 rq_count; 2272 + __le16 eq_count; 2273 + __le16 wq_count; 2274 + __le16 cq_count; 2275 + __le32 pad[45]; 2276 + }; 2277 + 2278 + /* READ_NVPARMS - read SLI port configuration parameters */ 2279 + enum sli4_read_nvparms_flags { 2280 + SLI4_READ_NVPARAMS_HARD_ALPA = 0xff, 2281 + SLI4_READ_NVPARAMS_PREFERRED_D_ID = 0xffffff00, 2282 + }; 2283 + 2284 + struct sli4_cmd_read_nvparms { 2285 + struct sli4_mbox_command_header hdr; 2286 + __le32 resvd0; 2287 + __le32 resvd4; 2288 + __le32 resvd8; 2289 + __le32 resvd12; 2290 + u8 wwpn[8]; 2291 + u8 wwnn[8]; 2292 + __le32 hard_alpa_d_id; 2293 + }; 2294 + 2295 + /* WRITE_NVPARMS - write SLI port configuration parameters */ 2296 + struct sli4_cmd_write_nvparms { 2297 + struct sli4_mbox_command_header hdr; 2298 + __le32 resvd0; 2299 + __le32 resvd4; 2300 + __le32 resvd8; 2301 + __le32 resvd12; 2302 + u8 wwpn[8]; 2303 + u8 wwnn[8]; 2304 + __le32 hard_alpa_d_id; 2305 + }; 2306 + 2307 + /* READ_REV - read the Port revision levels */ 2308 + enum { 2309 + SLI4_READ_REV_FLAG_SLI_LEVEL = 0xf, 2310 + SLI4_READ_REV_FLAG_FCOEM = 0x10, 2311 + SLI4_READ_REV_FLAG_CEEV = 0x60, 2312 + SLI4_READ_REV_FLAG_VPD = 0x2000, 2313 + 2314 + SLI4_READ_REV_AVAILABLE_LENGTH = 0xffffff, 2315 + }; 2316 + 2317 + struct sli4_cmd_read_rev { 2318 + struct sli4_mbox_command_header hdr; 2319 + __le16 resvd0; 2320 + __le16 flags0_word; 2321 + __le32 first_hw_rev; 2322 + __le32 second_hw_rev; 2323 + __le32 resvd12; 2324 + __le32 third_hw_rev; 2325 + u8 fc_ph_low; 2326 + u8 fc_ph_high; 2327 + u8 feature_level_low; 2328 + u8 feature_level_high; 2329 + __le32 resvd24; 2330 + __le32 first_fw_id; 2331 + u8 first_fw_name[16]; 2332 + __le32 second_fw_id; 2333 + u8 second_fw_name[16]; 2334 + __le32 rsvd18[30]; 2335 + __le32 available_length_dword; 2336 + struct sli4_dmaaddr hostbuf; 2337 + __le32 returned_vpd_length; 2338 + __le32 actual_vpd_length; 2339 + }; 2340 + 2341 + /* READ_SPARM64 - read the Port service parameters */ 2342 + #define SLI4_READ_SPARM64_WWPN_OFFSET (4 * sizeof(u32)) 2343 + #define SLI4_READ_SPARM64_WWNN_OFFSET (6 * sizeof(u32)) 2344 + 2345 + struct sli4_cmd_read_sparm64 { 2346 + struct sli4_mbox_command_header hdr; 2347 + __le32 resvd0; 2348 + __le32 resvd4; 2349 + struct sli4_bde bde_64; 2350 + __le16 vpi; 2351 + __le16 resvd22; 2352 + __le16 port_name_start; 2353 + __le16 port_name_len; 2354 + __le16 node_name_start; 2355 + __le16 node_name_len; 2356 + }; 2357 + 2358 + /* READ_TOPOLOGY - read the link event information */ 2359 + enum sli4_read_topo_e { 2360 + SLI4_READTOPO_ATTEN_TYPE = 0xff, 2361 + SLI4_READTOPO_FLAG_IL = 0x100, 2362 + SLI4_READTOPO_FLAG_PB_RECVD = 0x200, 2363 + 2364 + SLI4_READTOPO_LINKSTATE_RECV = 0x3, 2365 + SLI4_READTOPO_LINKSTATE_TRANS = 0xc, 2366 + SLI4_READTOPO_LINKSTATE_MACHINE = 0xf0, 2367 + SLI4_READTOPO_LINKSTATE_SPEED = 0xff00, 2368 + SLI4_READTOPO_LINKSTATE_TF = 0x40000000, 2369 + SLI4_READTOPO_LINKSTATE_LU = 0x80000000, 2370 + 2371 + SLI4_READTOPO_SCN_BBSCN = 0xf, 2372 + SLI4_READTOPO_SCN_CBBSCN = 0xf0, 2373 + 2374 + SLI4_READTOPO_R_T_TOV = 0x1ff, 2375 + SLI4_READTOPO_AL_TOV = 0xf000, 2376 + 2377 + SLI4_READTOPO_PB_FLAG = 0x80, 2378 + 2379 + SLI4_READTOPO_INIT_N_PORTID = 0xffffff, 2380 + }; 2381 + 2382 + #define SLI4_MIN_LOOP_MAP_BYTES 128 2383 + 2384 + struct sli4_cmd_read_topology { 2385 + struct sli4_mbox_command_header hdr; 2386 + __le32 event_tag; 2387 + __le32 dw2_attentype; 2388 + u8 topology; 2389 + u8 lip_type; 2390 + u8 lip_al_ps; 2391 + u8 al_pa_granted; 2392 + struct sli4_bde bde_loop_map; 2393 + __le32 linkdown_state; 2394 + __le32 currlink_state; 2395 + u8 max_bbc; 2396 + u8 init_bbc; 2397 + u8 scn_flags; 2398 + u8 rsvd39; 2399 + __le16 dw10w0_al_rt_tov; 2400 + __le16 lp_tov; 2401 + u8 acquired_al_pa; 2402 + u8 pb_flags; 2403 + __le16 specified_al_pa; 2404 + __le32 dw12_init_n_port_id; 2405 + }; 2406 + 2407 + enum sli4_read_topo_link { 2408 + SLI4_READ_TOPOLOGY_LINK_UP = 0x1, 2409 + SLI4_READ_TOPOLOGY_LINK_DOWN, 2410 + SLI4_READ_TOPOLOGY_LINK_NO_ALPA, 2411 + }; 2412 + 2413 + enum sli4_read_topo { 2414 + SLI4_READ_TOPO_UNKNOWN = 0x0, 2415 + SLI4_READ_TOPO_NON_FC_AL, 2416 + SLI4_READ_TOPO_FC_AL, 2417 + }; 2418 + 2419 + enum sli4_read_topo_speed { 2420 + SLI4_READ_TOPOLOGY_SPEED_NONE = 0x00, 2421 + SLI4_READ_TOPOLOGY_SPEED_1G = 0x04, 2422 + SLI4_READ_TOPOLOGY_SPEED_2G = 0x08, 2423 + SLI4_READ_TOPOLOGY_SPEED_4G = 0x10, 2424 + SLI4_READ_TOPOLOGY_SPEED_8G = 0x20, 2425 + SLI4_READ_TOPOLOGY_SPEED_10G = 0x40, 2426 + SLI4_READ_TOPOLOGY_SPEED_16G = 0x80, 2427 + SLI4_READ_TOPOLOGY_SPEED_32G = 0x90, 2428 + SLI4_READ_TOPOLOGY_SPEED_64G = 0xa0, 2429 + SLI4_READ_TOPOLOGY_SPEED_128G = 0xb0, 2430 + }; 2431 + 2432 + /* REG_FCFI - activate a FC Forwarder */ 2433 + struct sli4_cmd_reg_fcfi_rq_cfg { 2434 + u8 r_ctl_mask; 2435 + u8 r_ctl_match; 2436 + u8 type_mask; 2437 + u8 type_match; 2438 + }; 2439 + 2440 + enum sli4_regfcfi_tag { 2441 + SLI4_REGFCFI_VLAN_TAG = 0xfff, 2442 + SLI4_REGFCFI_VLANTAG_VALID = 0x1000, 2443 + }; 2444 + 2445 + #define SLI4_CMD_REG_FCFI_NUM_RQ_CFG 4 2446 + struct sli4_cmd_reg_fcfi { 2447 + struct sli4_mbox_command_header hdr; 2448 + __le16 fcf_index; 2449 + __le16 fcfi; 2450 + __le16 rqid1; 2451 + __le16 rqid0; 2452 + __le16 rqid3; 2453 + __le16 rqid2; 2454 + struct sli4_cmd_reg_fcfi_rq_cfg 2455 + rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG]; 2456 + __le32 dw8_vlan; 2457 + }; 2458 + 2459 + #define SLI4_CMD_REG_FCFI_MRQ_NUM_RQ_CFG 4 2460 + #define SLI4_CMD_REG_FCFI_MRQ_MAX_NUM_RQ 32 2461 + #define SLI4_CMD_REG_FCFI_SET_FCFI_MODE 0 2462 + #define SLI4_CMD_REG_FCFI_SET_MRQ_MODE 1 2463 + 2464 + enum sli4_reg_fcfi_mrq { 2465 + SLI4_REGFCFI_MRQ_VLAN_TAG = 0xfff, 2466 + SLI4_REGFCFI_MRQ_VLANTAG_VALID = 0x1000, 2467 + SLI4_REGFCFI_MRQ_MODE = 0x2000, 2468 + 2469 + SLI4_REGFCFI_MRQ_MASK_NUM_PAIRS = 0xff, 2470 + SLI4_REGFCFI_MRQ_FILTER_BITMASK = 0xf00, 2471 + SLI4_REGFCFI_MRQ_RQ_SEL_POLICY = 0xf000, 2472 + }; 2473 + 2474 + struct sli4_cmd_reg_fcfi_mrq { 2475 + struct sli4_mbox_command_header hdr; 2476 + __le16 fcf_index; 2477 + __le16 fcfi; 2478 + __le16 rqid1; 2479 + __le16 rqid0; 2480 + __le16 rqid3; 2481 + __le16 rqid2; 2482 + struct sli4_cmd_reg_fcfi_rq_cfg 2483 + rq_cfg[SLI4_CMD_REG_FCFI_MRQ_NUM_RQ_CFG]; 2484 + __le32 dw8_vlan; 2485 + __le32 dw9_mrqflags; 2486 + }; 2487 + 2488 + struct sli4_cmd_rq_cfg { 2489 + __le16 rq_id; 2490 + u8 r_ctl_mask; 2491 + u8 r_ctl_match; 2492 + u8 type_mask; 2493 + u8 type_match; 2494 + }; 2495 + 2496 + /* REG_RPI - register a Remote Port Indicator */ 2497 + enum sli4_reg_rpi { 2498 + SLI4_REGRPI_REMOTE_N_PORTID = 0xffffff, /* DW2 */ 2499 + SLI4_REGRPI_UPD = 0x1000000, 2500 + SLI4_REGRPI_ETOW = 0x8000000, 2501 + SLI4_REGRPI_TERP = 0x20000000, 2502 + SLI4_REGRPI_CI = 0x80000000, 2503 + }; 2504 + 2505 + struct sli4_cmd_reg_rpi { 2506 + struct sli4_mbox_command_header hdr; 2507 + __le16 rpi; 2508 + __le16 rsvd2; 2509 + __le32 dw2_rportid_flags; 2510 + struct sli4_bde bde_64; 2511 + __le16 vpi; 2512 + __le16 rsvd26; 2513 + }; 2514 + 2515 + #define SLI4_REG_RPI_BUF_LEN 0x70 2516 + 2517 + /* REG_VFI - register a Virtual Fabric Indicator */ 2518 + enum sli_reg_vfi { 2519 + SLI4_REGVFI_VP = 0x1000, /* DW1 */ 2520 + SLI4_REGVFI_UPD = 0x2000, 2521 + 2522 + SLI4_REGVFI_LOCAL_N_PORTID = 0xffffff, /* DW10 */ 2523 + }; 2524 + 2525 + struct sli4_cmd_reg_vfi { 2526 + struct sli4_mbox_command_header hdr; 2527 + __le16 vfi; 2528 + __le16 dw0w1_flags; 2529 + __le16 fcfi; 2530 + __le16 vpi; 2531 + u8 wwpn[8]; 2532 + struct sli4_bde sparm; 2533 + __le32 e_d_tov; 2534 + __le32 r_a_tov; 2535 + __le32 dw10_lportid_flags; 2536 + }; 2537 + 2538 + /* REG_VPI - register a Virtual Port Indicator */ 2539 + enum sli4_reg_vpi { 2540 + SLI4_REGVPI_LOCAL_N_PORTID = 0xffffff, 2541 + SLI4_REGVPI_UPD = 0x1000000, 2542 + }; 2543 + 2544 + struct sli4_cmd_reg_vpi { 2545 + struct sli4_mbox_command_header hdr; 2546 + __le32 rsvd0; 2547 + __le32 dw2_lportid_flags; 2548 + u8 wwpn[8]; 2549 + __le32 rsvd12; 2550 + __le16 vpi; 2551 + __le16 vfi; 2552 + }; 2553 + 2554 + /* REQUEST_FEATURES - request / query SLI features */ 2555 + enum sli4_req_features_flags { 2556 + SLI4_REQFEAT_QRY = 0x1, /* Dw1 */ 2557 + 2558 + SLI4_REQFEAT_IAAB = 1 << 0, /* DW2 & DW3 */ 2559 + SLI4_REQFEAT_NPIV = 1 << 1, 2560 + SLI4_REQFEAT_DIF = 1 << 2, 2561 + SLI4_REQFEAT_VF = 1 << 3, 2562 + SLI4_REQFEAT_FCPI = 1 << 4, 2563 + SLI4_REQFEAT_FCPT = 1 << 5, 2564 + SLI4_REQFEAT_FCPC = 1 << 6, 2565 + SLI4_REQFEAT_RSVD = 1 << 7, 2566 + SLI4_REQFEAT_RQD = 1 << 8, 2567 + SLI4_REQFEAT_IAAR = 1 << 9, 2568 + SLI4_REQFEAT_HLM = 1 << 10, 2569 + SLI4_REQFEAT_PERFH = 1 << 11, 2570 + SLI4_REQFEAT_RXSEQ = 1 << 12, 2571 + SLI4_REQFEAT_RXRI = 1 << 13, 2572 + SLI4_REQFEAT_DCL2 = 1 << 14, 2573 + SLI4_REQFEAT_RSCO = 1 << 15, 2574 + SLI4_REQFEAT_MRQP = 1 << 16, 2575 + }; 2576 + 2577 + struct sli4_cmd_request_features { 2578 + struct sli4_mbox_command_header hdr; 2579 + __le32 dw1_qry; 2580 + __le32 cmd; 2581 + __le32 resp; 2582 + }; 2583 + 2584 + /* 2585 + * SLI_CONFIG - submit a configuration command to Port 2586 + * 2587 + * Command is either embedded as part of the payload (embed) or located 2588 + * in a separate memory buffer (mem) 2589 + */ 2590 + enum sli4_sli_config { 2591 + SLI4_SLICONF_EMB = 0x1, /* DW1 */ 2592 + SLI4_SLICONF_PMDCMD_SHIFT = 3, 2593 + SLI4_SLICONF_PMDCMD_MASK = 0xf8, 2594 + SLI4_SLICONF_PMDCMD_VAL_1 = 8, 2595 + SLI4_SLICONF_PMDCNT = 0xf8, 2596 + 2597 + SLI4_SLICONF_PMD_LEN = 0x00ffffff, 2598 + }; 2599 + 2600 + struct sli4_cmd_sli_config { 2601 + struct sli4_mbox_command_header hdr; 2602 + __le32 dw1_flags; 2603 + __le32 payload_len; 2604 + __le32 rsvd12[3]; 2605 + union { 2606 + u8 embed[58 * sizeof(u32)]; 2607 + struct sli4_bufptr mem; 2608 + } payload; 2609 + }; 2610 + 2611 + /* READ_STATUS - read tx/rx status of a particular port */ 2612 + #define SLI4_READSTATUS_CLEAR_COUNTERS 0x1 2613 + 2614 + struct sli4_cmd_read_status { 2615 + struct sli4_mbox_command_header hdr; 2616 + __le32 dw1_flags; 2617 + __le32 rsvd4; 2618 + __le32 trans_kbyte_cnt; 2619 + __le32 recv_kbyte_cnt; 2620 + __le32 trans_frame_cnt; 2621 + __le32 recv_frame_cnt; 2622 + __le32 trans_seq_cnt; 2623 + __le32 recv_seq_cnt; 2624 + __le32 tot_exchanges_orig; 2625 + __le32 tot_exchanges_resp; 2626 + __le32 recv_p_bsy_cnt; 2627 + __le32 recv_f_bsy_cnt; 2628 + __le32 no_rq_buf_dropped_frames_cnt; 2629 + __le32 empty_rq_timeout_cnt; 2630 + __le32 no_xri_dropped_frames_cnt; 2631 + __le32 empty_xri_pool_cnt; 2632 + }; 2633 + 2634 + /* READ_LNK_STAT - read link status of a particular port */ 2635 + enum sli4_read_link_stats_flags { 2636 + SLI4_READ_LNKSTAT_REC = 1u << 0, 2637 + SLI4_READ_LNKSTAT_GEC = 1u << 1, 2638 + SLI4_READ_LNKSTAT_W02OF = 1u << 2, 2639 + SLI4_READ_LNKSTAT_W03OF = 1u << 3, 2640 + SLI4_READ_LNKSTAT_W04OF = 1u << 4, 2641 + SLI4_READ_LNKSTAT_W05OF = 1u << 5, 2642 + SLI4_READ_LNKSTAT_W06OF = 1u << 6, 2643 + SLI4_READ_LNKSTAT_W07OF = 1u << 7, 2644 + SLI4_READ_LNKSTAT_W08OF = 1u << 8, 2645 + SLI4_READ_LNKSTAT_W09OF = 1u << 9, 2646 + SLI4_READ_LNKSTAT_W10OF = 1u << 10, 2647 + SLI4_READ_LNKSTAT_W11OF = 1u << 11, 2648 + SLI4_READ_LNKSTAT_W12OF = 1u << 12, 2649 + SLI4_READ_LNKSTAT_W13OF = 1u << 13, 2650 + SLI4_READ_LNKSTAT_W14OF = 1u << 14, 2651 + SLI4_READ_LNKSTAT_W15OF = 1u << 15, 2652 + SLI4_READ_LNKSTAT_W16OF = 1u << 16, 2653 + SLI4_READ_LNKSTAT_W17OF = 1u << 17, 2654 + SLI4_READ_LNKSTAT_W18OF = 1u << 18, 2655 + SLI4_READ_LNKSTAT_W19OF = 1u << 19, 2656 + SLI4_READ_LNKSTAT_W20OF = 1u << 20, 2657 + SLI4_READ_LNKSTAT_W21OF = 1u << 21, 2658 + SLI4_READ_LNKSTAT_CLRC = 1u << 30, 2659 + SLI4_READ_LNKSTAT_CLOF = 1u << 31, 2660 + }; 2661 + 2662 + struct sli4_cmd_read_link_stats { 2663 + struct sli4_mbox_command_header hdr; 2664 + __le32 dw1_flags; 2665 + __le32 linkfail_errcnt; 2666 + __le32 losssync_errcnt; 2667 + __le32 losssignal_errcnt; 2668 + __le32 primseq_errcnt; 2669 + __le32 inval_txword_errcnt; 2670 + __le32 crc_errcnt; 2671 + __le32 primseq_eventtimeout_cnt; 2672 + __le32 elastic_bufoverrun_errcnt; 2673 + __le32 arbit_fc_al_timeout_cnt; 2674 + __le32 adv_rx_buftor_to_buf_credit; 2675 + __le32 curr_rx_buf_to_buf_credit; 2676 + __le32 adv_tx_buf_to_buf_credit; 2677 + __le32 curr_tx_buf_to_buf_credit; 2678 + __le32 rx_eofa_cnt; 2679 + __le32 rx_eofdti_cnt; 2680 + __le32 rx_eofni_cnt; 2681 + __le32 rx_soff_cnt; 2682 + __le32 rx_dropped_no_aer_cnt; 2683 + __le32 rx_dropped_no_avail_rpi_rescnt; 2684 + __le32 rx_dropped_no_avail_xri_rescnt; 2685 + }; 2686 + 2687 + /* Format a WQE with WQ_ID Association performance hint */ 2688 + static inline void 2689 + sli_set_wq_id_association(void *entry, u16 q_id) 2690 + { 2691 + u32 *wqe = entry; 2692 + 2693 + /* 2694 + * Set Word 10, bit 0 to zero 2695 + * Set Word 10, bits 15:1 to the WQ ID 2696 + */ 2697 + wqe[10] &= ~0xffff; 2698 + wqe[10] |= q_id << 1; 2699 + } 2700 + 2701 + /* UNREG_FCFI - unregister a FCFI */ 2702 + struct sli4_cmd_unreg_fcfi { 2703 + struct sli4_mbox_command_header hdr; 2704 + __le32 rsvd0; 2705 + __le16 fcfi; 2706 + __le16 rsvd6; 2707 + }; 2708 + 2709 + /* UNREG_RPI - unregister one or more RPI */ 2710 + enum sli4_unreg_rpi { 2711 + SLI4_UNREG_RPI_DP = 0x2000, 2712 + SLI4_UNREG_RPI_II_SHIFT = 14, 2713 + SLI4_UNREG_RPI_II_MASK = 0xc000, 2714 + SLI4_UNREG_RPI_II_RPI = 0x0000, 2715 + SLI4_UNREG_RPI_II_VPI = 0x4000, 2716 + SLI4_UNREG_RPI_II_VFI = 0x8000, 2717 + SLI4_UNREG_RPI_II_FCFI = 0xc000, 2718 + 2719 + SLI4_UNREG_RPI_DEST_N_PORTID_MASK = 0x00ffffff, 2720 + }; 2721 + 2722 + struct sli4_cmd_unreg_rpi { 2723 + struct sli4_mbox_command_header hdr; 2724 + __le16 index; 2725 + __le16 dw1w1_flags; 2726 + __le32 dw2_dest_n_portid; 2727 + }; 2728 + 2729 + /* UNREG_VFI - unregister one or more VFI */ 2730 + enum sli4_unreg_vfi { 2731 + SLI4_UNREG_VFI_II_SHIFT = 14, 2732 + SLI4_UNREG_VFI_II_MASK = 0xc000, 2733 + SLI4_UNREG_VFI_II_VFI = 0x0000, 2734 + SLI4_UNREG_VFI_II_FCFI = 0xc000, 2735 + }; 2736 + 2737 + struct sli4_cmd_unreg_vfi { 2738 + struct sli4_mbox_command_header hdr; 2739 + __le32 rsvd0; 2740 + __le16 index; 2741 + __le16 dw2_flags; 2742 + }; 2743 + 2744 + enum sli4_unreg_type { 2745 + SLI4_UNREG_TYPE_PORT, 2746 + SLI4_UNREG_TYPE_DOMAIN, 2747 + SLI4_UNREG_TYPE_FCF, 2748 + SLI4_UNREG_TYPE_ALL 2749 + }; 2750 + 2751 + /* UNREG_VPI - unregister one or more VPI */ 2752 + enum sli4_unreg_vpi { 2753 + SLI4_UNREG_VPI_II_SHIFT = 14, 2754 + SLI4_UNREG_VPI_II_MASK = 0xc000, 2755 + SLI4_UNREG_VPI_II_VPI = 0x0000, 2756 + SLI4_UNREG_VPI_II_VFI = 0x8000, 2757 + SLI4_UNREG_VPI_II_FCFI = 0xc000, 2758 + }; 2759 + 2760 + struct sli4_cmd_unreg_vpi { 2761 + struct sli4_mbox_command_header hdr; 2762 + __le32 rsvd0; 2763 + __le16 index; 2764 + __le16 dw2w0_flags; 2765 + }; 2766 + 2767 + /* AUTO_XFER_RDY - Configure the auto-generate XFER-RDY feature */ 2768 + struct sli4_cmd_config_auto_xfer_rdy { 2769 + struct sli4_mbox_command_header hdr; 2770 + __le32 rsvd0; 2771 + __le32 max_burst_len; 2772 + }; 2773 + 2774 + #define SLI4_CONFIG_AUTO_XFERRDY_BLKSIZE 0xffff 2775 + 2776 + struct sli4_cmd_config_auto_xfer_rdy_hp { 2777 + struct sli4_mbox_command_header hdr; 2778 + __le32 rsvd0; 2779 + __le32 max_burst_len; 2780 + __le32 dw3_esoc_flags; 2781 + __le16 block_size; 2782 + __le16 rsvd14; 2783 + }; 2784 + 2785 + /************************************************************************* 2786 + * SLI-4 common configuration command formats and definitions 2787 + */ 2788 + 2789 + /* 2790 + * Subsystem values. 2791 + */ 2792 + enum sli4_subsystem { 2793 + SLI4_SUBSYSTEM_COMMON = 0x01, 2794 + SLI4_SUBSYSTEM_LOWLEVEL = 0x0b, 2795 + SLI4_SUBSYSTEM_FC = 0x0c, 2796 + SLI4_SUBSYSTEM_DMTF = 0x11, 2797 + }; 2798 + 2799 + #define SLI4_OPC_LOWLEVEL_SET_WATCHDOG 0X36 2800 + 2801 + /* 2802 + * Common opcode (OPC) values. 2803 + */ 2804 + enum sli4_cmn_opcode { 2805 + SLI4_CMN_FUNCTION_RESET = 0x3d, 2806 + SLI4_CMN_CREATE_CQ = 0x0c, 2807 + SLI4_CMN_CREATE_CQ_SET = 0x1d, 2808 + SLI4_CMN_DESTROY_CQ = 0x36, 2809 + SLI4_CMN_MODIFY_EQ_DELAY = 0x29, 2810 + SLI4_CMN_CREATE_EQ = 0x0d, 2811 + SLI4_CMN_DESTROY_EQ = 0x37, 2812 + SLI4_CMN_CREATE_MQ_EXT = 0x5a, 2813 + SLI4_CMN_DESTROY_MQ = 0x35, 2814 + SLI4_CMN_GET_CNTL_ATTRIBUTES = 0x20, 2815 + SLI4_CMN_NOP = 0x21, 2816 + SLI4_CMN_GET_RSC_EXTENT_INFO = 0x9a, 2817 + SLI4_CMN_GET_SLI4_PARAMS = 0xb5, 2818 + SLI4_CMN_QUERY_FW_CONFIG = 0x3a, 2819 + SLI4_CMN_GET_PORT_NAME = 0x4d, 2820 + 2821 + SLI4_CMN_WRITE_FLASHROM = 0x07, 2822 + /* TRANSCEIVER Data */ 2823 + SLI4_CMN_READ_TRANS_DATA = 0x49, 2824 + SLI4_CMN_GET_CNTL_ADDL_ATTRS = 0x79, 2825 + SLI4_CMN_GET_FUNCTION_CFG = 0xa0, 2826 + SLI4_CMN_GET_PROFILE_CFG = 0xa4, 2827 + SLI4_CMN_SET_PROFILE_CFG = 0xa5, 2828 + SLI4_CMN_GET_PROFILE_LIST = 0xa6, 2829 + SLI4_CMN_GET_ACTIVE_PROFILE = 0xa7, 2830 + SLI4_CMN_SET_ACTIVE_PROFILE = 0xa8, 2831 + SLI4_CMN_READ_OBJECT = 0xab, 2832 + SLI4_CMN_WRITE_OBJECT = 0xac, 2833 + SLI4_CMN_DELETE_OBJECT = 0xae, 2834 + SLI4_CMN_READ_OBJECT_LIST = 0xad, 2835 + SLI4_CMN_SET_DUMP_LOCATION = 0xb8, 2836 + SLI4_CMN_SET_FEATURES = 0xbf, 2837 + SLI4_CMN_GET_RECFG_LINK_INFO = 0xc9, 2838 + SLI4_CMN_SET_RECNG_LINK_ID = 0xca, 2839 + }; 2840 + 2841 + /* DMTF opcode (OPC) values */ 2842 + #define DMTF_EXEC_CLP_CMD 0x01 2843 + 2844 + /* 2845 + * COMMON_FUNCTION_RESET 2846 + * 2847 + * Resets the Port, returning it to a power-on state. This configuration 2848 + * command does not have a payload and should set/expect the lengths to 2849 + * be zero. 2850 + */ 2851 + struct sli4_rqst_cmn_function_reset { 2852 + struct sli4_rqst_hdr hdr; 2853 + }; 2854 + 2855 + struct sli4_rsp_cmn_function_reset { 2856 + struct sli4_rsp_hdr hdr; 2857 + }; 2858 + 2859 + /* 2860 + * COMMON_GET_CNTL_ATTRIBUTES 2861 + * 2862 + * Query for information about the SLI Port 2863 + */ 2864 + enum sli4_cntrl_attr_flags { 2865 + SLI4_CNTL_ATTR_PORTNUM = 0x3f, 2866 + SLI4_CNTL_ATTR_PORTTYPE = 0xc0, 2867 + }; 2868 + 2869 + struct sli4_rsp_cmn_get_cntl_attributes { 2870 + struct sli4_rsp_hdr hdr; 2871 + u8 version_str[32]; 2872 + u8 manufacturer_name[32]; 2873 + __le32 supported_modes; 2874 + u8 eprom_version_lo; 2875 + u8 eprom_version_hi; 2876 + __le16 rsvd17; 2877 + __le32 mbx_ds_version; 2878 + __le32 ep_fw_ds_version; 2879 + u8 ncsi_version_str[12]; 2880 + __le32 def_extended_timeout; 2881 + u8 model_number[32]; 2882 + u8 description[64]; 2883 + u8 serial_number[32]; 2884 + u8 ip_version_str[32]; 2885 + u8 fw_version_str[32]; 2886 + u8 bios_version_str[32]; 2887 + u8 redboot_version_str[32]; 2888 + u8 driver_version_str[32]; 2889 + u8 fw_on_flash_version_str[32]; 2890 + __le32 functionalities_supported; 2891 + __le16 max_cdb_length; 2892 + u8 asic_revision; 2893 + u8 generational_guid0; 2894 + __le32 generational_guid1_12[3]; 2895 + __le16 generational_guid13_14; 2896 + u8 generational_guid15; 2897 + u8 hba_port_count; 2898 + __le16 default_link_down_timeout; 2899 + u8 iscsi_version_min_max; 2900 + u8 multifunctional_device; 2901 + u8 cache_valid; 2902 + u8 hba_status; 2903 + u8 max_domains_supported; 2904 + u8 port_num_type_flags; 2905 + __le32 firmware_post_status; 2906 + __le32 hba_mtu; 2907 + u8 iscsi_features; 2908 + u8 rsvd121[3]; 2909 + __le16 pci_vendor_id; 2910 + __le16 pci_device_id; 2911 + __le16 pci_sub_vendor_id; 2912 + __le16 pci_sub_system_id; 2913 + u8 pci_bus_number; 2914 + u8 pci_device_number; 2915 + u8 pci_function_number; 2916 + u8 interface_type; 2917 + __le64 unique_identifier; 2918 + u8 number_of_netfilters; 2919 + u8 rsvd122[3]; 2920 + }; 2921 + 2922 + /* 2923 + * COMMON_GET_CNTL_ATTRIBUTES 2924 + * 2925 + * This command queries the controller information from the Flash ROM. 2926 + */ 2927 + struct sli4_rqst_cmn_get_cntl_addl_attributes { 2928 + struct sli4_rqst_hdr hdr; 2929 + }; 2930 + 2931 + struct sli4_rsp_cmn_get_cntl_addl_attributes { 2932 + struct sli4_rsp_hdr hdr; 2933 + __le16 ipl_file_number; 2934 + u8 ipl_file_version; 2935 + u8 rsvd4; 2936 + u8 on_die_temperature; 2937 + u8 rsvd5[3]; 2938 + __le32 driver_advanced_features_supported; 2939 + __le32 rsvd7[4]; 2940 + char universal_bios_version[32]; 2941 + char x86_bios_version[32]; 2942 + char efi_bios_version[32]; 2943 + char fcode_version[32]; 2944 + char uefi_bios_version[32]; 2945 + char uefi_nic_version[32]; 2946 + char uefi_fcode_version[32]; 2947 + char uefi_iscsi_version[32]; 2948 + char iscsi_x86_bios_version[32]; 2949 + char pxe_x86_bios_version[32]; 2950 + u8 default_wwpn[8]; 2951 + u8 ext_phy_version[32]; 2952 + u8 fc_universal_bios_version[32]; 2953 + u8 fc_x86_bios_version[32]; 2954 + u8 fc_efi_bios_version[32]; 2955 + u8 fc_fcode_version[32]; 2956 + u8 ext_phy_crc_label[8]; 2957 + u8 ipl_file_name[16]; 2958 + u8 rsvd139[72]; 2959 + }; 2960 + 2961 + /* 2962 + * COMMON_NOP 2963 + * 2964 + * This command does not do anything; it only returns 2965 + * the payload in the completion. 2966 + */ 2967 + struct sli4_rqst_cmn_nop { 2968 + struct sli4_rqst_hdr hdr; 2969 + __le32 context[2]; 2970 + }; 2971 + 2972 + struct sli4_rsp_cmn_nop { 2973 + struct sli4_rsp_hdr hdr; 2974 + __le32 context[2]; 2975 + }; 2976 + 2977 + struct sli4_rqst_cmn_get_resource_extent_info { 2978 + struct sli4_rqst_hdr hdr; 2979 + __le16 resource_type; 2980 + __le16 rsvd16; 2981 + }; 2982 + 2983 + enum sli4_rsc_type { 2984 + SLI4_RSC_TYPE_VFI = 0x20, 2985 + SLI4_RSC_TYPE_VPI = 0x21, 2986 + SLI4_RSC_TYPE_RPI = 0x22, 2987 + SLI4_RSC_TYPE_XRI = 0x23, 2988 + }; 2989 + 2990 + struct sli4_rsp_cmn_get_resource_extent_info { 2991 + struct sli4_rsp_hdr hdr; 2992 + __le16 resource_extent_count; 2993 + __le16 resource_extent_size; 2994 + }; 2995 + 2996 + #define SLI4_128BYTE_WQE_SUPPORT 0x02 2997 + 2998 + #define GET_Q_CNT_METHOD(m) \ 2999 + (((m) & SLI4_PARAM_Q_CNT_MTHD_MASK) >> SLI4_PARAM_Q_CNT_MTHD_SHFT) 3000 + #define GET_Q_CREATE_VERSION(v) \ 3001 + (((v) & SLI4_PARAM_QV_MASK) >> SLI4_PARAM_QV_SHIFT) 3002 + 3003 + enum sli4_rsp_get_params_e { 3004 + /*GENERIC*/ 3005 + SLI4_PARAM_Q_CNT_MTHD_SHFT = 24, 3006 + SLI4_PARAM_Q_CNT_MTHD_MASK = 0xf << 24, 3007 + SLI4_PARAM_QV_SHIFT = 14, 3008 + SLI4_PARAM_QV_MASK = 3 << 14, 3009 + 3010 + /* DW4 */ 3011 + SLI4_PARAM_PROTO_TYPE_MASK = 0xff, 3012 + /* DW5 */ 3013 + SLI4_PARAM_FT = 1 << 0, 3014 + SLI4_PARAM_SLI_REV_MASK = 0xf << 4, 3015 + SLI4_PARAM_SLI_FAM_MASK = 0xf << 8, 3016 + SLI4_PARAM_IF_TYPE_MASK = 0xf << 12, 3017 + SLI4_PARAM_SLI_HINT1_MASK = 0xff << 16, 3018 + SLI4_PARAM_SLI_HINT2_MASK = 0x1f << 24, 3019 + /* DW6 */ 3020 + SLI4_PARAM_EQ_PAGE_CNT_MASK = 0xf << 0, 3021 + SLI4_PARAM_EQE_SZS_MASK = 0xf << 8, 3022 + SLI4_PARAM_EQ_PAGE_SZS_MASK = 0xff << 16, 3023 + /* DW8 */ 3024 + SLI4_PARAM_CQ_PAGE_CNT_MASK = 0xf << 0, 3025 + SLI4_PARAM_CQE_SZS_MASK = 0xf << 8, 3026 + SLI4_PARAM_CQ_PAGE_SZS_MASK = 0xff << 16, 3027 + /* DW10 */ 3028 + SLI4_PARAM_MQ_PAGE_CNT_MASK = 0xf << 0, 3029 + SLI4_PARAM_MQ_PAGE_SZS_MASK = 0xff << 16, 3030 + /* DW12 */ 3031 + SLI4_PARAM_WQ_PAGE_CNT_MASK = 0xf << 0, 3032 + SLI4_PARAM_WQE_SZS_MASK = 0xf << 8, 3033 + SLI4_PARAM_WQ_PAGE_SZS_MASK = 0xff << 16, 3034 + /* DW14 */ 3035 + SLI4_PARAM_RQ_PAGE_CNT_MASK = 0xf << 0, 3036 + SLI4_PARAM_RQE_SZS_MASK = 0xf << 8, 3037 + SLI4_PARAM_RQ_PAGE_SZS_MASK = 0xff << 16, 3038 + /* DW15W1*/ 3039 + SLI4_PARAM_RQ_DB_WINDOW_MASK = 0xf000, 3040 + /* DW16 */ 3041 + SLI4_PARAM_FC = 1 << 0, 3042 + SLI4_PARAM_EXT = 1 << 1, 3043 + SLI4_PARAM_HDRR = 1 << 2, 3044 + SLI4_PARAM_SGLR = 1 << 3, 3045 + SLI4_PARAM_FBRR = 1 << 4, 3046 + SLI4_PARAM_AREG = 1 << 5, 3047 + SLI4_PARAM_TGT = 1 << 6, 3048 + SLI4_PARAM_TERP = 1 << 7, 3049 + SLI4_PARAM_ASSI = 1 << 8, 3050 + SLI4_PARAM_WCHN = 1 << 9, 3051 + SLI4_PARAM_TCCA = 1 << 10, 3052 + SLI4_PARAM_TRTY = 1 << 11, 3053 + SLI4_PARAM_TRIR = 1 << 12, 3054 + SLI4_PARAM_PHOFF = 1 << 13, 3055 + SLI4_PARAM_PHON = 1 << 14, 3056 + SLI4_PARAM_PHWQ = 1 << 15, 3057 + SLI4_PARAM_BOUND_4GA = 1 << 16, 3058 + SLI4_PARAM_RXC = 1 << 17, 3059 + SLI4_PARAM_HLM = 1 << 18, 3060 + SLI4_PARAM_IPR = 1 << 19, 3061 + SLI4_PARAM_RXRI = 1 << 20, 3062 + SLI4_PARAM_SGLC = 1 << 21, 3063 + SLI4_PARAM_TIMM = 1 << 22, 3064 + SLI4_PARAM_TSMM = 1 << 23, 3065 + SLI4_PARAM_OAS = 1 << 25, 3066 + SLI4_PARAM_LC = 1 << 26, 3067 + SLI4_PARAM_AGXF = 1 << 27, 3068 + SLI4_PARAM_LOOPBACK_MASK = 0xf << 28, 3069 + /* DW18 */ 3070 + SLI4_PARAM_SGL_PAGE_CNT_MASK = 0xf << 0, 3071 + SLI4_PARAM_SGL_PAGE_SZS_MASK = 0xff << 8, 3072 + SLI4_PARAM_SGL_PP_ALIGN_MASK = 0xff << 16, 3073 + }; 3074 + 3075 + struct sli4_rqst_cmn_get_sli4_params { 3076 + struct sli4_rqst_hdr hdr; 3077 + }; 3078 + 3079 + struct sli4_rsp_cmn_get_sli4_params { 3080 + struct sli4_rsp_hdr hdr; 3081 + __le32 dw4_protocol_type; 3082 + __le32 dw5_sli; 3083 + __le32 dw6_eq_page_cnt; 3084 + __le16 eqe_count_mask; 3085 + __le16 rsvd26; 3086 + __le32 dw8_cq_page_cnt; 3087 + __le16 cqe_count_mask; 3088 + __le16 rsvd34; 3089 + __le32 dw10_mq_page_cnt; 3090 + __le16 mqe_count_mask; 3091 + __le16 rsvd42; 3092 + __le32 dw12_wq_page_cnt; 3093 + __le16 wqe_count_mask; 3094 + __le16 rsvd50; 3095 + __le32 dw14_rq_page_cnt; 3096 + __le16 rqe_count_mask; 3097 + __le16 dw15w1_rq_db_window; 3098 + __le32 dw16_loopback_scope; 3099 + __le32 sge_supported_length; 3100 + __le32 dw18_sgl_page_cnt; 3101 + __le16 min_rq_buffer_size; 3102 + __le16 rsvd75; 3103 + __le32 max_rq_buffer_size; 3104 + __le16 physical_xri_max; 3105 + __le16 physical_rpi_max; 3106 + __le16 physical_vpi_max; 3107 + __le16 physical_vfi_max; 3108 + __le32 rsvd88; 3109 + __le16 frag_num_field_offset; 3110 + __le16 frag_num_field_size; 3111 + __le16 sgl_index_field_offset; 3112 + __le16 sgl_index_field_size; 3113 + __le32 chain_sge_initial_value_lo; 3114 + __le32 chain_sge_initial_value_hi; 3115 + }; 3116 + 3117 + /*Port Types*/ 3118 + enum sli4_port_types { 3119 + SLI4_PORT_TYPE_ETH = 0, 3120 + SLI4_PORT_TYPE_FC = 1, 3121 + }; 3122 + 3123 + struct sli4_rqst_cmn_get_port_name { 3124 + struct sli4_rqst_hdr hdr; 3125 + u8 port_type; 3126 + u8 rsvd4[3]; 3127 + }; 3128 + 3129 + struct sli4_rsp_cmn_get_port_name { 3130 + struct sli4_rsp_hdr hdr; 3131 + char port_name[4]; 3132 + }; 3133 + 3134 + struct sli4_rqst_cmn_write_flashrom { 3135 + struct sli4_rqst_hdr hdr; 3136 + __le32 flash_rom_access_opcode; 3137 + __le32 flash_rom_access_operation_type; 3138 + __le32 data_buffer_size; 3139 + __le32 offset; 3140 + u8 data_buffer[4]; 3141 + }; 3142 + 3143 + /* 3144 + * COMMON_READ_TRANSCEIVER_DATA 3145 + * 3146 + * This command reads SFF transceiver data(Format is defined 3147 + * by the SFF-8472 specification). 3148 + */ 3149 + struct sli4_rqst_cmn_read_transceiver_data { 3150 + struct sli4_rqst_hdr hdr; 3151 + __le32 page_number; 3152 + __le32 port; 3153 + }; 3154 + 3155 + struct sli4_rsp_cmn_read_transceiver_data { 3156 + struct sli4_rsp_hdr hdr; 3157 + __le32 page_number; 3158 + __le32 port; 3159 + u8 page_data[128]; 3160 + u8 page_data_2[128]; 3161 + }; 3162 + 3163 + #define SLI4_REQ_DESIRE_READLEN 0xffffff 3164 + 3165 + struct sli4_rqst_cmn_read_object { 3166 + struct sli4_rqst_hdr hdr; 3167 + __le32 desired_read_length_dword; 3168 + __le32 read_offset; 3169 + u8 object_name[104]; 3170 + __le32 host_buffer_descriptor_count; 3171 + struct sli4_bde host_buffer_descriptor[0]; 3172 + }; 3173 + 3174 + #define RSP_COM_READ_OBJ_EOF 0x80000000 3175 + 3176 + struct sli4_rsp_cmn_read_object { 3177 + struct sli4_rsp_hdr hdr; 3178 + __le32 actual_read_length; 3179 + __le32 eof_dword; 3180 + }; 3181 + 3182 + enum sli4_rqst_write_object_flags { 3183 + SLI4_RQ_DES_WRITE_LEN = 0xffffff, 3184 + SLI4_RQ_DES_WRITE_LEN_NOC = 0x40000000, 3185 + SLI4_RQ_DES_WRITE_LEN_EOF = 0x80000000, 3186 + }; 3187 + 3188 + struct sli4_rqst_cmn_write_object { 3189 + struct sli4_rqst_hdr hdr; 3190 + __le32 desired_write_len_dword; 3191 + __le32 write_offset; 3192 + u8 object_name[104]; 3193 + __le32 host_buffer_descriptor_count; 3194 + struct sli4_bde host_buffer_descriptor[0]; 3195 + }; 3196 + 3197 + #define RSP_CHANGE_STATUS 0xff 3198 + 3199 + struct sli4_rsp_cmn_write_object { 3200 + struct sli4_rsp_hdr hdr; 3201 + __le32 actual_write_length; 3202 + __le32 change_status_dword; 3203 + }; 3204 + 3205 + struct sli4_rqst_cmn_delete_object { 3206 + struct sli4_rqst_hdr hdr; 3207 + __le32 rsvd4; 3208 + __le32 rsvd5; 3209 + u8 object_name[104]; 3210 + }; 3211 + 3212 + #define SLI4_RQ_OBJ_LIST_READ_LEN 0xffffff 3213 + 3214 + struct sli4_rqst_cmn_read_object_list { 3215 + struct sli4_rqst_hdr hdr; 3216 + __le32 desired_read_length_dword; 3217 + __le32 read_offset; 3218 + u8 object_name[104]; 3219 + __le32 host_buffer_descriptor_count; 3220 + struct sli4_bde host_buffer_descriptor[0]; 3221 + }; 3222 + 3223 + enum sli4_rqst_set_dump_flags { 3224 + SLI4_CMN_SET_DUMP_BUFFER_LEN = 0xffffff, 3225 + SLI4_CMN_SET_DUMP_FDB = 0x20000000, 3226 + SLI4_CMN_SET_DUMP_BLP = 0x40000000, 3227 + SLI4_CMN_SET_DUMP_QRY = 0x80000000, 3228 + }; 3229 + 3230 + struct sli4_rqst_cmn_set_dump_location { 3231 + struct sli4_rqst_hdr hdr; 3232 + __le32 buffer_length_dword; 3233 + __le32 buf_addr_low; 3234 + __le32 buf_addr_high; 3235 + }; 3236 + 3237 + struct sli4_rsp_cmn_set_dump_location { 3238 + struct sli4_rsp_hdr hdr; 3239 + __le32 buffer_length_dword; 3240 + }; 3241 + 3242 + enum sli4_dump_level { 3243 + SLI4_DUMP_LEVEL_NONE, 3244 + SLI4_CHIP_LEVEL_DUMP, 3245 + SLI4_FUNC_DESC_DUMP, 3246 + }; 3247 + 3248 + enum sli4_dump_state { 3249 + SLI4_DUMP_STATE_NONE, 3250 + SLI4_CHIP_DUMP_STATE_VALID, 3251 + SLI4_FUNC_DUMP_STATE_VALID, 3252 + }; 3253 + 3254 + enum sli4_dump_status { 3255 + SLI4_DUMP_READY_STATUS_NOT_READY, 3256 + SLI4_DUMP_READY_STATUS_DD_PRESENT, 3257 + SLI4_DUMP_READY_STATUS_FDB_PRESENT, 3258 + SLI4_DUMP_READY_STATUS_SKIP_DUMP, 3259 + SLI4_DUMP_READY_STATUS_FAILED = -1, 3260 + }; 3261 + 3262 + enum sli4_set_features { 3263 + SLI4_SET_FEATURES_DIF_SEED = 0x01, 3264 + SLI4_SET_FEATURES_XRI_TIMER = 0x03, 3265 + SLI4_SET_FEATURES_MAX_PCIE_SPEED = 0x04, 3266 + SLI4_SET_FEATURES_FCTL_CHECK = 0x05, 3267 + SLI4_SET_FEATURES_FEC = 0x06, 3268 + SLI4_SET_FEATURES_PCIE_RECV_DETECT = 0x07, 3269 + SLI4_SET_FEATURES_DIF_MEMORY_MODE = 0x08, 3270 + SLI4_SET_FEATURES_DISABLE_SLI_PORT_PAUSE_STATE = 0x09, 3271 + SLI4_SET_FEATURES_ENABLE_PCIE_OPTIONS = 0x0a, 3272 + SLI4_SET_FEAT_CFG_AUTO_XFER_RDY_T10PI = 0x0c, 3273 + SLI4_SET_FEATURES_ENABLE_MULTI_RECEIVE_QUEUE = 0x0d, 3274 + SLI4_SET_FEATURES_SET_FTD_XFER_HINT = 0x0f, 3275 + SLI4_SET_FEATURES_SLI_PORT_HEALTH_CHECK = 0x11, 3276 + }; 3277 + 3278 + struct sli4_rqst_cmn_set_features { 3279 + struct sli4_rqst_hdr hdr; 3280 + __le32 feature; 3281 + __le32 param_len; 3282 + __le32 params[8]; 3283 + }; 3284 + 3285 + struct sli4_rqst_cmn_set_features_dif_seed { 3286 + __le16 seed; 3287 + __le16 rsvd16; 3288 + }; 3289 + 3290 + enum sli4_rqst_set_mrq_features { 3291 + SLI4_RQ_MULTIRQ_ISR = 0x1, 3292 + SLI4_RQ_MULTIRQ_AUTOGEN_XFER_RDY = 0x2, 3293 + 3294 + SLI4_RQ_MULTIRQ_NUM_RQS = 0xff, 3295 + SLI4_RQ_MULTIRQ_RQ_SELECT = 0xf00, 3296 + }; 3297 + 3298 + struct sli4_rqst_cmn_set_features_multirq { 3299 + __le32 auto_gen_xfer_dword; 3300 + __le32 num_rqs_dword; 3301 + }; 3302 + 3303 + enum sli4_rqst_health_check_flags { 3304 + SLI4_RQ_HEALTH_CHECK_ENABLE = 0x1, 3305 + SLI4_RQ_HEALTH_CHECK_QUERY = 0x2, 3306 + }; 3307 + 3308 + struct sli4_rqst_cmn_set_features_health_check { 3309 + __le32 health_check_dword; 3310 + }; 3311 + 3312 + struct sli4_rqst_cmn_set_features_set_fdt_xfer_hint { 3313 + __le32 fdt_xfer_hint; 3314 + }; 3315 + 3316 + struct sli4_rqst_dmtf_exec_clp_cmd { 3317 + struct sli4_rqst_hdr hdr; 3318 + __le32 cmd_buf_length; 3319 + __le32 resp_buf_length; 3320 + __le32 cmd_buf_addr_low; 3321 + __le32 cmd_buf_addr_high; 3322 + __le32 resp_buf_addr_low; 3323 + __le32 resp_buf_addr_high; 3324 + }; 3325 + 3326 + struct sli4_rsp_dmtf_exec_clp_cmd { 3327 + struct sli4_rsp_hdr hdr; 3328 + __le32 rsvd4; 3329 + __le32 resp_length; 3330 + __le32 rsvd6; 3331 + __le32 rsvd7; 3332 + __le32 rsvd8; 3333 + __le32 rsvd9; 3334 + __le32 clp_status; 3335 + __le32 clp_detailed_status; 3336 + }; 3337 + 3338 + #define SLI4_PROTOCOL_FC 0x10 3339 + #define SLI4_PROTOCOL_DEFAULT 0xff 3340 + 3341 + struct sli4_rspource_descriptor_v1 { 3342 + u8 descriptor_type; 3343 + u8 descriptor_length; 3344 + __le16 rsvd16; 3345 + __le32 type_specific[0]; 3346 + }; 3347 + 3348 + enum sli4_pcie_desc_flags { 3349 + SLI4_PCIE_DESC_IMM = 0x4000, 3350 + SLI4_PCIE_DESC_NOSV = 0x8000, 3351 + 3352 + SLI4_PCIE_DESC_PF_NO = 0x3ff0000, 3353 + 3354 + SLI4_PCIE_DESC_MISSN_ROLE = 0xff, 3355 + SLI4_PCIE_DESC_PCHG = 0x8000000, 3356 + SLI4_PCIE_DESC_SCHG = 0x10000000, 3357 + SLI4_PCIE_DESC_XCHG = 0x20000000, 3358 + SLI4_PCIE_DESC_XROM = 0xc0000000 3359 + }; 3360 + 3361 + struct sli4_pcie_resource_descriptor_v1 { 3362 + u8 descriptor_type; 3363 + u8 descriptor_length; 3364 + __le16 imm_nosv_dword; 3365 + __le32 pf_number_dword; 3366 + __le32 rsvd3; 3367 + u8 sriov_state; 3368 + u8 pf_state; 3369 + u8 pf_type; 3370 + u8 rsvd4; 3371 + __le16 number_of_vfs; 3372 + __le16 rsvd5; 3373 + __le32 mission_roles_dword; 3374 + __le32 rsvd7[16]; 3375 + }; 3376 + 3377 + struct sli4_rqst_cmn_get_function_config { 3378 + struct sli4_rqst_hdr hdr; 3379 + }; 3380 + 3381 + struct sli4_rsp_cmn_get_function_config { 3382 + struct sli4_rsp_hdr hdr; 3383 + __le32 desc_count; 3384 + __le32 desc[54]; 3385 + }; 3386 + 3387 + /* Link Config Descriptor for link config functions */ 3388 + struct sli4_link_config_descriptor { 3389 + u8 link_config_id; 3390 + u8 rsvd1[3]; 3391 + __le32 config_description[8]; 3392 + }; 3393 + 3394 + #define MAX_LINK_DES 10 3395 + 3396 + struct sli4_rqst_cmn_get_reconfig_link_info { 3397 + struct sli4_rqst_hdr hdr; 3398 + }; 3399 + 3400 + struct sli4_rsp_cmn_get_reconfig_link_info { 3401 + struct sli4_rsp_hdr hdr; 3402 + u8 active_link_config_id; 3403 + u8 rsvd17; 3404 + u8 next_link_config_id; 3405 + u8 rsvd19; 3406 + __le32 link_configuration_descriptor_count; 3407 + struct sli4_link_config_descriptor 3408 + desc[MAX_LINK_DES]; 3409 + }; 3410 + 3411 + enum sli4_set_reconfig_link_flags { 3412 + SLI4_SET_RECONFIG_LINKID_NEXT = 0xff, 3413 + SLI4_SET_RECONFIG_LINKID_FD = 1u << 31, 3414 + }; 3415 + 3416 + struct sli4_rqst_cmn_set_reconfig_link_id { 3417 + struct sli4_rqst_hdr hdr; 3418 + __le32 dw4_flags; 3419 + }; 3420 + 3421 + struct sli4_rsp_cmn_set_reconfig_link_id { 3422 + struct sli4_rsp_hdr hdr; 3423 + }; 3424 + 3425 + struct sli4_rqst_lowlevel_set_watchdog { 3426 + struct sli4_rqst_hdr hdr; 3427 + __le16 watchdog_timeout; 3428 + __le16 rsvd18; 3429 + }; 3430 + 3431 + struct sli4_rsp_lowlevel_set_watchdog { 3432 + struct sli4_rsp_hdr hdr; 3433 + __le32 rsvd; 3434 + }; 3435 + 3436 + /* FC opcode (OPC) values */ 3437 + enum sli4_fc_opcodes { 3438 + SLI4_OPC_WQ_CREATE = 0x1, 3439 + SLI4_OPC_WQ_DESTROY = 0x2, 3440 + SLI4_OPC_POST_SGL_PAGES = 0x3, 3441 + SLI4_OPC_RQ_CREATE = 0x5, 3442 + SLI4_OPC_RQ_DESTROY = 0x6, 3443 + SLI4_OPC_READ_FCF_TABLE = 0x8, 3444 + SLI4_OPC_POST_HDR_TEMPLATES = 0xb, 3445 + SLI4_OPC_REDISCOVER_FCF = 0x10, 3446 + }; 3447 + 3448 + /* Use the default CQ associated with the WQ */ 3449 + #define SLI4_CQ_DEFAULT 0xffff 3450 + 3451 + /* 3452 + * POST_SGL_PAGES 3453 + * 3454 + * Register the scatter gather list (SGL) memory and 3455 + * associate it with an XRI. 3456 + */ 3457 + struct sli4_rqst_post_sgl_pages { 3458 + struct sli4_rqst_hdr hdr; 3459 + __le16 xri_start; 3460 + __le16 xri_count; 3461 + struct { 3462 + __le32 page0_low; 3463 + __le32 page0_high; 3464 + __le32 page1_low; 3465 + __le32 page1_high; 3466 + } page_set[10]; 3467 + }; 3468 + 3469 + struct sli4_rsp_post_sgl_pages { 3470 + struct sli4_rsp_hdr hdr; 3471 + }; 3472 + 3473 + struct sli4_rqst_post_hdr_templates { 3474 + struct sli4_rqst_hdr hdr; 3475 + __le16 rpi_offset; 3476 + __le16 page_count; 3477 + struct sli4_dmaaddr page_descriptor[0]; 3478 + }; 3479 + 3480 + #define SLI4_HDR_TEMPLATE_SIZE 64 3481 + 3482 + enum sli4_io_flags { 3483 + /* The XRI associated with this IO is already active */ 3484 + SLI4_IO_CONTINUATION = 1 << 0, 3485 + /* Automatically generate a good RSP frame */ 3486 + SLI4_IO_AUTO_GOOD_RESPONSE = 1 << 1, 3487 + SLI4_IO_NO_ABORT = 1 << 2, 3488 + /* Set the DNRX bit because no auto xref rdy buffer is posted */ 3489 + SLI4_IO_DNRX = 1 << 3, 3490 + }; 3491 + 3492 + enum sli4_callback { 3493 + SLI4_CB_LINK, 3494 + SLI4_CB_MAX, 3495 + }; 3496 + 3497 + enum sli4_link_status { 3498 + SLI4_LINK_STATUS_UP, 3499 + SLI4_LINK_STATUS_DOWN, 3500 + SLI4_LINK_STATUS_NO_ALPA, 3501 + SLI4_LINK_STATUS_MAX, 3502 + }; 3503 + 3504 + enum sli4_link_topology { 3505 + SLI4_LINK_TOPO_NON_FC_AL = 1, 3506 + SLI4_LINK_TOPO_FC_AL, 3507 + SLI4_LINK_TOPO_LOOPBACK_INTERNAL, 3508 + SLI4_LINK_TOPO_LOOPBACK_EXTERNAL, 3509 + SLI4_LINK_TOPO_NONE, 3510 + SLI4_LINK_TOPO_MAX, 3511 + }; 3512 + 3513 + enum sli4_link_medium { 3514 + SLI4_LINK_MEDIUM_ETHERNET, 3515 + SLI4_LINK_MEDIUM_FC, 3516 + SLI4_LINK_MEDIUM_MAX, 3517 + }; 1993 3518 /******Driver specific structures******/ 1994 3519 1995 3520 struct sli4_queue { ··· 3604 2079 u32 xmit_len; 3605 2080 u16 xri; 3606 2081 u16 tag; 2082 + }; 2083 + 2084 + struct sli4_link_event { 2085 + enum sli4_link_status status; 2086 + enum sli4_link_topology topology; 2087 + enum sli4_link_medium medium; 2088 + u32 speed; 2089 + u8 *loop_map; 2090 + u32 fc_id; 2091 + }; 2092 + 2093 + enum sli4_resource { 2094 + SLI4_RSRC_VFI, 2095 + SLI4_RSRC_VPI, 2096 + SLI4_RSRC_RPI, 2097 + SLI4_RSRC_XRI, 2098 + SLI4_RSRC_FCFI, 2099 + SLI4_RSRC_MAX, 2100 + }; 2101 + 2102 + struct sli4_extent { 2103 + u32 number; 2104 + u32 size; 2105 + u32 n_alloc; 2106 + u32 *base; 2107 + unsigned long *use_map; 2108 + u32 map_size; 2109 + }; 2110 + 2111 + struct sli4_queue_info { 2112 + u16 max_qcount[SLI4_QTYPE_MAX]; 2113 + u32 max_qentries[SLI4_QTYPE_MAX]; 2114 + u16 count_mask[SLI4_QTYPE_MAX]; 2115 + u16 count_method[SLI4_QTYPE_MAX]; 2116 + u32 qpage_count[SLI4_QTYPE_MAX]; 2117 + }; 2118 + 2119 + struct sli4_params { 2120 + u8 has_extents; 2121 + u8 auto_reg; 2122 + u8 auto_xfer_rdy; 2123 + u8 hdr_template_req; 2124 + u8 perf_hint; 2125 + u8 perf_wq_id_association; 2126 + u8 cq_create_version; 2127 + u8 mq_create_version; 2128 + u8 high_login_mode; 2129 + u8 sgl_pre_registered; 2130 + u8 sgl_pre_reg_required; 2131 + u8 t10_dif_inline_capable; 2132 + u8 t10_dif_separate_capable; 2133 + }; 2134 + 2135 + struct sli4 { 2136 + void *os; 2137 + struct pci_dev *pci; 2138 + void __iomem *reg[PCI_STD_NUM_BARS]; 2139 + 2140 + u32 sli_rev; 2141 + u32 sli_family; 2142 + u32 if_type; 2143 + 2144 + u16 asic_type; 2145 + u16 asic_rev; 2146 + 2147 + u16 e_d_tov; 2148 + u16 r_a_tov; 2149 + struct sli4_queue_info qinfo; 2150 + u16 link_module_type; 2151 + u8 rq_batch; 2152 + u8 port_number; 2153 + char port_name[2]; 2154 + u16 rq_min_buf_size; 2155 + u32 rq_max_buf_size; 2156 + u8 topology; 2157 + u8 wwpn[8]; 2158 + u8 wwnn[8]; 2159 + u32 fw_rev[2]; 2160 + u8 fw_name[2][16]; 2161 + char ipl_name[16]; 2162 + u32 hw_rev[3]; 2163 + char modeldesc[64]; 2164 + char bios_version_string[32]; 2165 + u32 wqe_size; 2166 + u32 vpd_length; 2167 + /* 2168 + * Tracks the port resources using extents metaphor. For 2169 + * devices that don't implement extents (i.e. 2170 + * has_extents == FALSE), the code models each resource as 2171 + * a single large extent. 2172 + */ 2173 + struct sli4_extent ext[SLI4_RSRC_MAX]; 2174 + u32 features; 2175 + struct sli4_params params; 2176 + u32 sge_supported_length; 2177 + u32 sgl_page_sizes; 2178 + u32 max_sgl_pages; 2179 + 2180 + /* 2181 + * Callback functions 2182 + */ 2183 + int (*link)(void *ctx, void *event); 2184 + void *link_arg; 2185 + 2186 + struct efc_dma bmbx; 2187 + 2188 + /* Save pointer to physical memory descriptor for non-embedded 2189 + * SLI_CONFIG commands for BMBX dumping purposes 2190 + */ 2191 + struct efc_dma *bmbx_non_emb_pmd; 2192 + 2193 + struct efc_dma vpd_data; 3607 2194 }; 3608 2195 3609 2196 #endif /* !_SLI4_H */

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