Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
scsi: elx: libefc_sli: SLI Descriptors and Queue entries
Continue the libefc_sli SLI-4 library population.
Add SLI-4 Data structures and defines for:
- Buffer Descriptors (BDEs)
- Scatter/Gather List elements (SGEs)
- Queues and their Entry Descriptions for: Event Queues (EQs), Completion
Queues (CQs), Receive Queues (RQs), and the Mailbox Queue (MQ).
Link: https://lore.kernel.org/r/20210601235512.20104-3-jsmart2021@gmail.com
Reviewed-by: Daniel Wagner <dwagner@suse.de>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Co-developed-by: Ram Vegesna <ram.vegesna@broadcom.com>
Signed-off-by: Ram Vegesna <ram.vegesna@broadcom.com>
Signed-off-by: James Smart <jsmart2021@gmail.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
authored by
James Smart
and committed by
Martin K. Petersen
216fc0b4
edba59f3
+1798
+22
drivers/scsi/elx/include/efc_common.h
+22
drivers/scsi/elx/include/efc_common.h
···
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2021 Broadcom. All Rights Reserved. The term
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* “Broadcom” refers to Broadcom Inc. and/or its subsidiaries.
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*/
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#ifndef __EFC_COMMON_H__
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#define __EFC_COMMON_H__
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#include <linux/pci.h>
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struct efc_dma {
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void *virt;
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void *alloc;
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dma_addr_t phys;
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size_t size;
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size_t len;
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struct pci_dev *pdev;
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};
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#endif /* __EFC_COMMON_H__ */
+1776
drivers/scsi/elx/libefc_sli/sli4.h
+1776
drivers/scsi/elx/libefc_sli/sli4.h
···
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u32 off;
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};
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struct sli4_dmaaddr {
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__le32 low;
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__le32 high;
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};
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/*
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* a 3-word Buffer Descriptor Entry with
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* address 1st 2 words, length last word
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*/
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struct sli4_bufptr {
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struct sli4_dmaaddr addr;
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__le32 length;
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};
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/* Buffer Descriptor Entry (BDE) */
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enum sli4_bde_e {
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SLI4_BDE_LEN_MASK = 0x00ffffff,
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SLI4_BDE_TYPE_MASK = 0xff000000,
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};
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struct sli4_bde {
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__le32 bde_type_buflen;
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union {
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struct sli4_dmaaddr data;
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struct {
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__le32 offset;
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__le32 rsvd2;
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} imm;
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struct sli4_dmaaddr blp;
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} u;
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};
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/* Buffer Descriptors */
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enum sli4_bde_type {
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SLI4_BDE_TYPE_SHIFT = 24,
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SLI4_BDE_TYPE_64 = 0x00, /* Generic 64-bit data */
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SLI4_BDE_TYPE_IMM = 0x01, /* Immediate data */
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SLI4_BDE_TYPE_BLP = 0x40, /* Buffer List Pointer */
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};
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#define SLI4_BDE_TYPE_VAL(type) \
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(SLI4_BDE_TYPE_##type << SLI4_BDE_TYPE_SHIFT)
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+
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/* Scatter-Gather Entry (SGE) */
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#define SLI4_SGE_MAX_RESERVED 3
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+
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enum sli4_sge_type {
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/* DW2 */
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SLI4_SGE_DATA_OFFSET_MASK = 0x07ffffff,
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/*DW2W1*/
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SLI4_SGE_TYPE_SHIFT = 27,
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SLI4_SGE_TYPE_MASK = 0x78000000,
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/*SGE Types*/
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SLI4_SGE_TYPE_DATA = 0x00,
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SLI4_SGE_TYPE_DIF = 0x04, /* Data Integrity Field */
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SLI4_SGE_TYPE_LSP = 0x05, /* List Segment Pointer */
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SLI4_SGE_TYPE_PEDIF = 0x06, /* Post Encryption Engine DIF */
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SLI4_SGE_TYPE_PESEED = 0x07, /* Post Encryption DIF Seed */
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SLI4_SGE_TYPE_DISEED = 0x08, /* DIF Seed */
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SLI4_SGE_TYPE_ENC = 0x09, /* Encryption */
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SLI4_SGE_TYPE_ATM = 0x0a, /* DIF Application Tag Mask */
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SLI4_SGE_TYPE_SKIP = 0x0c, /* SKIP */
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+
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SLI4_SGE_LAST = 1u << 31,
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};
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+
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struct sli4_sge {
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__le32 buffer_address_high;
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__le32 buffer_address_low;
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__le32 dw2_flags;
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__le32 buffer_length;
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};
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+
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/* T10 DIF Scatter-Gather Entry (SGE) */
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struct sli4_dif_sge {
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__le32 buffer_address_high;
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__le32 buffer_address_low;
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__le32 dw2_flags;
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__le32 rsvd12;
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};
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+
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/* Data Integrity Seed (DISEED) SGE */
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enum sli4_diseed_sge_flags {
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/* DW2W1 */
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SLI4_DISEED_SGE_HS = 1 << 2,
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SLI4_DISEED_SGE_WS = 1 << 3,
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SLI4_DISEED_SGE_IC = 1 << 4,
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SLI4_DISEED_SGE_ICS = 1 << 5,
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SLI4_DISEED_SGE_ATRT = 1 << 6,
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SLI4_DISEED_SGE_AT = 1 << 7,
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SLI4_DISEED_SGE_FAT = 1 << 8,
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SLI4_DISEED_SGE_NA = 1 << 9,
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SLI4_DISEED_SGE_HI = 1 << 10,
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+
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/* DW3W1 */
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SLI4_DISEED_SGE_BS_MASK = 0x0007,
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SLI4_DISEED_SGE_AI = 1 << 3,
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SLI4_DISEED_SGE_ME = 1 << 4,
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SLI4_DISEED_SGE_RE = 1 << 5,
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SLI4_DISEED_SGE_CE = 1 << 6,
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SLI4_DISEED_SGE_NR = 1 << 7,
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+
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SLI4_DISEED_SGE_OP_RX_SHIFT = 8,
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SLI4_DISEED_SGE_OP_RX_MASK = 0x0f00,
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SLI4_DISEED_SGE_OP_TX_SHIFT = 12,
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SLI4_DISEED_SGE_OP_TX_MASK = 0xf000,
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};
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/* Opcode values */
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enum sli4_diseed_sge_opcodes {
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SLI4_DISEED_SGE_OP_IN_NODIF_OUT_CRC,
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SLI4_DISEED_SGE_OP_IN_CRC_OUT_NODIF,
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SLI4_DISEED_SGE_OP_IN_NODIF_OUT_CSUM,
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SLI4_DISEED_SGE_OP_IN_CSUM_OUT_NODIF,
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SLI4_DISEED_SGE_OP_IN_CRC_OUT_CRC,
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SLI4_DISEED_SGE_OP_IN_CSUM_OUT_CSUM,
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SLI4_DISEED_SGE_OP_IN_CRC_OUT_CSUM,
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SLI4_DISEED_SGE_OP_IN_CSUM_OUT_CRC,
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SLI4_DISEED_SGE_OP_IN_RAW_OUT_RAW,
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};
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#define SLI4_DISEED_SGE_OP_RX_VALUE(stype) \
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(SLI4_DISEED_SGE_OP_##stype << SLI4_DISEED_SGE_OP_RX_SHIFT)
431
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#define SLI4_DISEED_SGE_OP_TX_VALUE(stype) \
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(SLI4_DISEED_SGE_OP_##stype << SLI4_DISEED_SGE_OP_TX_SHIFT)
433
+
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struct sli4_diseed_sge {
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__le32 ref_tag_cmp;
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__le32 ref_tag_repl;
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__le16 app_tag_repl;
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__le16 dw2w1_flags;
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__le16 app_tag_cmp;
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__le16 dw3w1_flags;
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};
442
+
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/* List Segment Pointer Scatter-Gather Entry (SGE) */
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#define SLI4_LSP_SGE_SEGLEN 0x00ffffff
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+
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struct sli4_lsp_sge {
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__le32 buffer_address_high;
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__le32 buffer_address_low;
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__le32 dw2_flags;
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__le32 dw3_seglen;
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};
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+
453
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enum sli4_eqe_e {
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SLI4_EQE_VALID = 1,
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SLI4_EQE_MJCODE = 0xe,
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SLI4_EQE_MNCODE = 0xfff0,
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};
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struct sli4_eqe {
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__le16 dw0w0_flags;
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__le16 resource_id;
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};
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+
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#define SLI4_MAJOR_CODE_STANDARD 0
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#define SLI4_MAJOR_CODE_SENTINEL 1
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+
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/* Sentinel EQE indicating the EQ is full */
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#define SLI4_EQE_STATUS_EQ_FULL 2
469
+
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enum sli4_mcqe_e {
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SLI4_MCQE_CONSUMED = 1u << 27,
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SLI4_MCQE_COMPLETED = 1u << 28,
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SLI4_MCQE_AE = 1u << 30,
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SLI4_MCQE_VALID = 1u << 31,
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};
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+
477
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/* Entry was consumed but not completed */
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#define SLI4_MCQE_STATUS_NOT_COMPLETED -2
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+
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struct sli4_mcqe {
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__le16 completion_status;
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__le16 extended_status;
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__le32 mqe_tag_low;
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__le32 mqe_tag_high;
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__le32 dw3_flags;
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};
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+
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enum sli4_acqe_e {
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SLI4_ACQE_AE = 1 << 6, /* async event - this is an ACQE */
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SLI4_ACQE_VAL = 1 << 7, /* valid - contents of CQE are valid */
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};
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+
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struct sli4_acqe {
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__le32 event_data[3];
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u8 rsvd12;
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u8 event_code;
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u8 event_type;
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u8 ae_val;
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};
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+
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enum sli4_acqe_event_code {
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SLI4_ACQE_EVENT_CODE_LINK_STATE = 0x01,
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SLI4_ACQE_EVENT_CODE_FIP = 0x02,
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SLI4_ACQE_EVENT_CODE_DCBX = 0x03,
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SLI4_ACQE_EVENT_CODE_ISCSI = 0x04,
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SLI4_ACQE_EVENT_CODE_GRP_5 = 0x05,
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SLI4_ACQE_EVENT_CODE_FC_LINK_EVENT = 0x10,
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SLI4_ACQE_EVENT_CODE_SLI_PORT_EVENT = 0x11,
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SLI4_ACQE_EVENT_CODE_VF_EVENT = 0x12,
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SLI4_ACQE_EVENT_CODE_MR_EVENT = 0x13,
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};
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+
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enum sli4_qtype {
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SLI4_QTYPE_EQ,
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SLI4_QTYPE_CQ,
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SLI4_QTYPE_MQ,
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SLI4_QTYPE_WQ,
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SLI4_QTYPE_RQ,
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SLI4_QTYPE_MAX, /* must be last */
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};
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#define SLI4_USER_MQ_COUNT 1
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#define SLI4_MAX_CQ_SET_COUNT 16
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#define SLI4_MAX_RQ_SET_COUNT 16
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+
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enum sli4_qentry {
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SLI4_QENTRY_ASYNC,
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SLI4_QENTRY_MQ,
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SLI4_QENTRY_RQ,
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SLI4_QENTRY_WQ,
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SLI4_QENTRY_WQ_RELEASE,
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SLI4_QENTRY_OPT_WRITE_CMD,
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SLI4_QENTRY_OPT_WRITE_DATA,
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SLI4_QENTRY_XABT,
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SLI4_QENTRY_MAX /* must be last */
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};
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enum sli4_queue_flags {
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SLI4_QUEUE_FLAG_MQ = 1 << 0, /* CQ has MQ/Async completion */
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SLI4_QUEUE_FLAG_HDR = 1 << 1, /* RQ for packet headers */
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SLI4_QUEUE_FLAG_RQBATCH = 1 << 2, /* RQ index increment by 8 */
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};
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/* Generic Command Request header */
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enum sli4_cmd_version {
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CMD_V0,
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CMD_V1,
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CMD_V2,
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};
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struct sli4_rqst_hdr {
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u8 opcode;
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u8 subsystem;
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__le16 rsvd2;
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__le32 timeout;
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__le32 request_length;
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__le32 dw3_version;
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};
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/* Generic Command Response header */
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struct sli4_rsp_hdr {
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u8 opcode;
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u8 subsystem;
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__le16 rsvd2;
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u8 status;
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u8 additional_status;
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__le16 rsvd6;
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__le32 response_length;
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__le32 actual_response_length;
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};
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#define SLI4_QUEUE_RQ_BATCH 8
573
+
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#define SZ_DMAADDR sizeof(struct sli4_dmaaddr)
575
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#define SLI4_RQST_CMDSZ(stype) sizeof(struct sli4_rqst_##stype)
576
+
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#define SLI4_RQST_PYLD_LEN(stype) \
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cpu_to_le32(sizeof(struct sli4_rqst_##stype) - \
579
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sizeof(struct sli4_rqst_hdr))
580
+
581
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#define SLI4_RQST_PYLD_LEN_VAR(stype, varpyld) \
582
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cpu_to_le32((sizeof(struct sli4_rqst_##stype) + \
583
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varpyld) - sizeof(struct sli4_rqst_hdr))
584
+
585
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#define SLI4_CFG_PYLD_LENGTH(stype) \
586
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max(sizeof(struct sli4_rqst_##stype), \
587
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sizeof(struct sli4_rsp_##stype))
588
+
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enum sli4_create_cqv2_e {
590
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/* DW5_flags values*/
591
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SLI4_CREATE_CQV2_CLSWM_MASK = 0x00003000,
592
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SLI4_CREATE_CQV2_NODELAY = 0x00004000,
593
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SLI4_CREATE_CQV2_AUTOVALID = 0x00008000,
594
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SLI4_CREATE_CQV2_CQECNT_MASK = 0x18000000,
595
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SLI4_CREATE_CQV2_VALID = 0x20000000,
596
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SLI4_CREATE_CQV2_EVT = 0x80000000,
597
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/* DW6W1_flags values*/
598
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SLI4_CREATE_CQV2_ARM = 0x8000,
599
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};
600
+
601
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struct sli4_rqst_cmn_create_cq_v2 {
602
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struct sli4_rqst_hdr hdr;
603
+
__le16 num_pages;
604
+
u8 page_size;
605
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u8 rsvd19;
606
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__le32 dw5_flags;
607
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__le16 eq_id;
608
+
__le16 dw6w1_arm;
609
+
__le16 cqe_count;
610
+
__le16 rsvd30;
611
+
__le32 rsvd32;
612
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struct sli4_dmaaddr page_phys_addr[0];
613
+
};
614
+
615
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enum sli4_create_cqset_e {
616
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/* DW5_flags values*/
617
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SLI4_CREATE_CQSETV0_CLSWM_MASK = 0x00003000,
618
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SLI4_CREATE_CQSETV0_NODELAY = 0x00004000,
619
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SLI4_CREATE_CQSETV0_AUTOVALID = 0x00008000,
620
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SLI4_CREATE_CQSETV0_CQECNT_MASK = 0x18000000,
621
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SLI4_CREATE_CQSETV0_VALID = 0x20000000,
622
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SLI4_CREATE_CQSETV0_EVT = 0x80000000,
623
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/* DW5W1_flags values */
624
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SLI4_CREATE_CQSETV0_CQE_COUNT = 0x7fff,
625
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SLI4_CREATE_CQSETV0_ARM = 0x8000,
626
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};
627
+
628
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struct sli4_rqst_cmn_create_cq_set_v0 {
629
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struct sli4_rqst_hdr hdr;
630
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__le16 num_pages;
631
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u8 page_size;
632
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u8 rsvd19;
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__le32 dw5_flags;
634
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__le16 num_cq_req;
635
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__le16 dw6w1_flags;
636
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__le16 eq_id[16];
637
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struct sli4_dmaaddr page_phys_addr[0];
638
+
};
639
+
640
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/* CQE count */
641
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enum sli4_cq_cnt {
642
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SLI4_CQ_CNT_256,
643
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SLI4_CQ_CNT_512,
644
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SLI4_CQ_CNT_1024,
645
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SLI4_CQ_CNT_LARGE,
646
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};
647
+
648
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#define SLI4_CQ_CNT_SHIFT 27
649
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#define SLI4_CQ_CNT_VAL(type) (SLI4_CQ_CNT_##type << SLI4_CQ_CNT_SHIFT)
650
+
651
+
#define SLI4_CQE_BYTES (4 * sizeof(u32))
652
+
653
+
#define SLI4_CREATE_CQV2_MAX_PAGES 8
654
+
655
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/* Generic Common Create EQ/CQ/MQ/WQ/RQ Queue completion */
656
+
struct sli4_rsp_cmn_create_queue {
657
+
struct sli4_rsp_hdr hdr;
658
+
__le16 q_id;
659
+
u8 rsvd18;
660
+
u8 ulp;
661
+
__le32 db_offset;
662
+
__le16 db_rs;
663
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__le16 db_fmt;
664
+
};
665
+
666
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struct sli4_rsp_cmn_create_queue_set {
667
+
struct sli4_rsp_hdr hdr;
668
+
__le16 q_id;
669
+
__le16 num_q_allocated;
670
+
};
671
+
672
+
/* Common Destroy Queue */
673
+
struct sli4_rqst_cmn_destroy_q {
674
+
struct sli4_rqst_hdr hdr;
675
+
__le16 q_id;
676
+
__le16 rsvd;
677
+
};
678
+
679
+
struct sli4_rsp_cmn_destroy_q {
680
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struct sli4_rsp_hdr hdr;
681
+
};
682
+
683
+
/* Modify the delay multiplier for EQs */
684
+
struct sli4_eqdelay_rec {
685
+
__le32 eq_id;
686
+
__le32 phase;
687
+
__le32 delay_multiplier;
688
+
};
689
+
690
+
struct sli4_rqst_cmn_modify_eq_delay {
691
+
struct sli4_rqst_hdr hdr;
692
+
__le32 num_eq;
693
+
struct sli4_eqdelay_rec eq_delay_record[8];
694
+
};
695
+
696
+
struct sli4_rsp_cmn_modify_eq_delay {
697
+
struct sli4_rsp_hdr hdr;
698
+
};
699
+
700
+
enum sli4_create_cq_e {
701
+
/* DW5 */
702
+
SLI4_CREATE_EQ_AUTOVALID = 1u << 28,
703
+
SLI4_CREATE_EQ_VALID = 1u << 29,
704
+
SLI4_CREATE_EQ_EQESZ = 1u << 31,
705
+
/* DW6 */
706
+
SLI4_CREATE_EQ_COUNT = 7 << 26,
707
+
SLI4_CREATE_EQ_ARM = 1u << 31,
708
+
/* DW7 */
709
+
SLI4_CREATE_EQ_DELAYMULTI_SHIFT = 13,
710
+
SLI4_CREATE_EQ_DELAYMULTI_MASK = 0x007fe000,
711
+
SLI4_CREATE_EQ_DELAYMULTI = 0x00040000,
712
+
};
713
+
714
+
struct sli4_rqst_cmn_create_eq {
715
+
struct sli4_rqst_hdr hdr;
716
+
__le16 num_pages;
717
+
__le16 rsvd18;
718
+
__le32 dw5_flags;
719
+
__le32 dw6_flags;
720
+
__le32 dw7_delaymulti;
721
+
__le32 rsvd32;
722
+
struct sli4_dmaaddr page_address[8];
723
+
};
724
+
725
+
struct sli4_rsp_cmn_create_eq {
726
+
struct sli4_rsp_cmn_create_queue q_rsp;
727
+
};
728
+
729
+
/* EQ count */
730
+
enum sli4_eq_cnt {
731
+
SLI4_EQ_CNT_256,
732
+
SLI4_EQ_CNT_512,
733
+
SLI4_EQ_CNT_1024,
734
+
SLI4_EQ_CNT_2048,
735
+
SLI4_EQ_CNT_4096 = 3,
736
+
};
737
+
738
+
#define SLI4_EQ_CNT_SHIFT 26
739
+
#define SLI4_EQ_CNT_VAL(type) (SLI4_EQ_CNT_##type << SLI4_EQ_CNT_SHIFT)
740
+
741
+
#define SLI4_EQE_SIZE_4 0
742
+
#define SLI4_EQE_SIZE_16 1
743
+
744
+
/* Create a Mailbox Queue; accommodate v0 and v1 forms. */
745
+
enum sli4_create_mq_flags {
746
+
/* DW6W1 */
747
+
SLI4_CREATE_MQEXT_RINGSIZE = 0xf,
748
+
SLI4_CREATE_MQEXT_CQID_SHIFT = 6,
749
+
SLI4_CREATE_MQEXT_CQIDV0_MASK = 0xffc0,
750
+
/* DW7 */
751
+
SLI4_CREATE_MQEXT_VAL = 1u << 31,
752
+
/* DW8 */
753
+
SLI4_CREATE_MQEXT_ACQV = 1u << 0,
754
+
SLI4_CREATE_MQEXT_ASYNC_CQIDV0 = 0x7fe,
755
+
};
756
+
757
+
struct sli4_rqst_cmn_create_mq_ext {
758
+
struct sli4_rqst_hdr hdr;
759
+
__le16 num_pages;
760
+
__le16 cq_id_v1;
761
+
__le32 async_event_bitmap;
762
+
__le16 async_cq_id_v1;
763
+
__le16 dw6w1_flags;
764
+
__le32 dw7_val;
765
+
__le32 dw8_flags;
766
+
__le32 rsvd36;
767
+
struct sli4_dmaaddr page_phys_addr[0];
768
+
};
769
+
770
+
struct sli4_rsp_cmn_create_mq_ext {
771
+
struct sli4_rsp_cmn_create_queue q_rsp;
772
+
};
773
+
774
+
enum sli4_mqe_size {
775
+
SLI4_MQE_SIZE_16 = 0x05,
776
+
SLI4_MQE_SIZE_32,
777
+
SLI4_MQE_SIZE_64,
778
+
SLI4_MQE_SIZE_128,
779
+
};
780
+
781
+
enum sli4_async_evt {
782
+
SLI4_ASYNC_EVT_LINK_STATE = 1 << 1,
783
+
SLI4_ASYNC_EVT_FIP = 1 << 2,
784
+
SLI4_ASYNC_EVT_GRP5 = 1 << 5,
785
+
SLI4_ASYNC_EVT_FC = 1 << 16,
786
+
SLI4_ASYNC_EVT_SLI_PORT = 1 << 17,
787
+
};
788
+
789
+
#define SLI4_ASYNC_EVT_FC_ALL \
790
+
(SLI4_ASYNC_EVT_LINK_STATE | \
791
+
SLI4_ASYNC_EVT_FIP | \
792
+
SLI4_ASYNC_EVT_GRP5 | \
793
+
SLI4_ASYNC_EVT_FC | \
794
+
SLI4_ASYNC_EVT_SLI_PORT)
795
+
796
+
/* Create a Completion Queue. */
797
+
struct sli4_rqst_cmn_create_cq_v0 {
798
+
struct sli4_rqst_hdr hdr;
799
+
__le16 num_pages;
800
+
__le16 rsvd18;
801
+
__le32 dw5_flags;
802
+
__le32 dw6_flags;
803
+
__le32 rsvd28;
804
+
__le32 rsvd32;
805
+
struct sli4_dmaaddr page_phys_addr[0];
806
+
};
807
+
808
+
enum sli4_create_rq_e {
809
+
SLI4_RQ_CREATE_DUA = 0x1,
810
+
SLI4_RQ_CREATE_BQU = 0x2,
811
+
812
+
SLI4_RQE_SIZE = 8,
813
+
SLI4_RQE_SIZE_8 = 0x2,
814
+
SLI4_RQE_SIZE_16 = 0x3,
815
+
SLI4_RQE_SIZE_32 = 0x4,
816
+
SLI4_RQE_SIZE_64 = 0x5,
817
+
SLI4_RQE_SIZE_128 = 0x6,
818
+
819
+
SLI4_RQ_PAGE_SIZE_4096 = 0x1,
820
+
SLI4_RQ_PAGE_SIZE_8192 = 0x2,
821
+
SLI4_RQ_PAGE_SIZE_16384 = 0x4,
822
+
SLI4_RQ_PAGE_SIZE_32768 = 0x8,
823
+
SLI4_RQ_PAGE_SIZE_64536 = 0x10,
824
+
825
+
SLI4_RQ_CREATE_V0_MAX_PAGES = 8,
826
+
SLI4_RQ_CREATE_V0_MIN_BUF_SIZE = 128,
827
+
SLI4_RQ_CREATE_V0_MAX_BUF_SIZE = 2048,
828
+
};
829
+
830
+
struct sli4_rqst_rq_create {
831
+
struct sli4_rqst_hdr hdr;
832
+
__le16 num_pages;
833
+
u8 dua_bqu_byte;
834
+
u8 ulp;
835
+
__le16 rsvd16;
836
+
u8 rqe_count_byte;
837
+
u8 rsvd19;
838
+
__le32 rsvd20;
839
+
__le16 buffer_size;
840
+
__le16 cq_id;
841
+
__le32 rsvd28;
842
+
struct sli4_dmaaddr page_phys_addr[SLI4_RQ_CREATE_V0_MAX_PAGES];
843
+
};
844
+
845
+
struct sli4_rsp_rq_create {
846
+
struct sli4_rsp_cmn_create_queue rsp;
847
+
};
848
+
849
+
enum sli4_create_rqv1_e {
850
+
SLI4_RQ_CREATE_V1_DNB = 0x80,
851
+
SLI4_RQ_CREATE_V1_MAX_PAGES = 8,
852
+
SLI4_RQ_CREATE_V1_MIN_BUF_SIZE = 64,
853
+
SLI4_RQ_CREATE_V1_MAX_BUF_SIZE = 2048,
854
+
};
855
+
856
+
struct sli4_rqst_rq_create_v1 {
857
+
struct sli4_rqst_hdr hdr;
858
+
__le16 num_pages;
859
+
u8 rsvd14;
860
+
u8 dim_dfd_dnb;
861
+
u8 page_size;
862
+
u8 rqe_size_byte;
863
+
__le16 rqe_count;
864
+
__le32 rsvd20;
865
+
__le16 rsvd24;
866
+
__le16 cq_id;
867
+
__le32 buffer_size;
868
+
struct sli4_dmaaddr page_phys_addr[SLI4_RQ_CREATE_V1_MAX_PAGES];
869
+
};
870
+
871
+
struct sli4_rsp_rq_create_v1 {
872
+
struct sli4_rsp_cmn_create_queue rsp;
873
+
};
874
+
875
+
#define SLI4_RQCREATEV2_DNB 0x80
876
+
877
+
struct sli4_rqst_rq_create_v2 {
878
+
struct sli4_rqst_hdr hdr;
879
+
__le16 num_pages;
880
+
u8 rq_count;
881
+
u8 dim_dfd_dnb;
882
+
u8 page_size;
883
+
u8 rqe_size_byte;
884
+
__le16 rqe_count;
885
+
__le16 hdr_buffer_size;
886
+
__le16 payload_buffer_size;
887
+
__le16 base_cq_id;
888
+
__le16 rsvd26;
889
+
__le32 rsvd42;
890
+
struct sli4_dmaaddr page_phys_addr[0];
891
+
};
892
+
893
+
struct sli4_rsp_rq_create_v2 {
894
+
struct sli4_rsp_cmn_create_queue rsp;
895
+
};
896
+
897
+
#define SLI4_CQE_CODE_OFFSET 14
898
+
899
+
enum sli4_cqe_code {
900
+
SLI4_CQE_CODE_WORK_REQUEST_COMPLETION = 0x01,
901
+
SLI4_CQE_CODE_RELEASE_WQE,
902
+
SLI4_CQE_CODE_RSVD,
903
+
SLI4_CQE_CODE_RQ_ASYNC,
904
+
SLI4_CQE_CODE_XRI_ABORTED,
905
+
SLI4_CQE_CODE_RQ_COALESCING,
906
+
SLI4_CQE_CODE_RQ_CONSUMPTION,
907
+
SLI4_CQE_CODE_MEASUREMENT_REPORTING,
908
+
SLI4_CQE_CODE_RQ_ASYNC_V1,
909
+
SLI4_CQE_CODE_RQ_COALESCING_V1,
910
+
SLI4_CQE_CODE_OPTIMIZED_WRITE_CMD,
911
+
SLI4_CQE_CODE_OPTIMIZED_WRITE_DATA,
912
+
};
913
+
914
+
#define SLI4_WQ_CREATE_MAX_PAGES 8
915
+
916
+
struct sli4_rqst_wq_create {
917
+
struct sli4_rqst_hdr hdr;
918
+
__le16 num_pages;
919
+
__le16 cq_id;
920
+
u8 page_size;
921
+
u8 wqe_size_byte;
922
+
__le16 wqe_count;
923
+
__le32 rsvd;
924
+
struct sli4_dmaaddr page_phys_addr[SLI4_WQ_CREATE_MAX_PAGES];
925
+
};
926
+
927
+
struct sli4_rsp_wq_create {
928
+
struct sli4_rsp_cmn_create_queue rsp;
929
+
};
930
+
931
+
enum sli4_link_attention_flags {
932
+
SLI4_LNK_ATTN_TYPE_LINK_UP = 0x01,
933
+
SLI4_LNK_ATTN_TYPE_LINK_DOWN = 0x02,
934
+
SLI4_LNK_ATTN_TYPE_NO_HARD_ALPA = 0x03,
935
+
936
+
SLI4_LNK_ATTN_P2P = 0x01,
937
+
SLI4_LNK_ATTN_FC_AL = 0x02,
938
+
SLI4_LNK_ATTN_INTERNAL_LOOPBACK = 0x03,
939
+
SLI4_LNK_ATTN_SERDES_LOOPBACK = 0x04,
940
+
};
941
+
942
+
struct sli4_link_attention {
943
+
u8 link_number;
944
+
u8 attn_type;
945
+
u8 topology;
946
+
u8 port_speed;
947
+
u8 port_fault;
948
+
u8 shared_link_status;
949
+
__le16 logical_link_speed;
950
+
__le32 event_tag;
951
+
u8 rsvd12;
952
+
u8 event_code;
953
+
u8 event_type;
954
+
u8 flags;
955
+
};
956
+
957
+
enum sli4_link_event_type {
958
+
SLI4_EVENT_LINK_ATTENTION = 0x01,
959
+
SLI4_EVENT_SHARED_LINK_ATTENTION = 0x02,
960
+
};
961
+
962
+
enum sli4_wcqe_flags {
963
+
SLI4_WCQE_XB = 0x10,
964
+
SLI4_WCQE_QX = 0x80,
965
+
};
966
+
967
+
struct sli4_fc_wcqe {
968
+
u8 hw_status;
969
+
u8 status;
970
+
__le16 request_tag;
971
+
__le32 wqe_specific_1;
972
+
__le32 wqe_specific_2;
973
+
u8 rsvd12;
974
+
u8 qx_byte;
975
+
u8 code;
976
+
u8 flags;
977
+
};
978
+
979
+
/* FC WQ consumed CQ queue entry */
980
+
struct sli4_fc_wqec {
981
+
__le32 rsvd0;
982
+
__le32 rsvd1;
983
+
__le16 wqe_index;
984
+
__le16 wq_id;
985
+
__le16 rsvd12;
986
+
u8 code;
987
+
u8 vld_byte;
988
+
};
989
+
990
+
/* FC Completion Status Codes. */
991
+
enum sli4_wcqe_status {
992
+
SLI4_FC_WCQE_STATUS_SUCCESS,
993
+
SLI4_FC_WCQE_STATUS_FCP_RSP_FAILURE,
994
+
SLI4_FC_WCQE_STATUS_REMOTE_STOP,
995
+
SLI4_FC_WCQE_STATUS_LOCAL_REJECT,
996
+
SLI4_FC_WCQE_STATUS_NPORT_RJT,
997
+
SLI4_FC_WCQE_STATUS_FABRIC_RJT,
998
+
SLI4_FC_WCQE_STATUS_NPORT_BSY,
999
+
SLI4_FC_WCQE_STATUS_FABRIC_BSY,
1000
+
SLI4_FC_WCQE_STATUS_RSVD,
1001
+
SLI4_FC_WCQE_STATUS_LS_RJT,
1002
+
SLI4_FC_WCQE_STATUS_RX_BUF_OVERRUN,
1003
+
SLI4_FC_WCQE_STATUS_CMD_REJECT,
1004
+
SLI4_FC_WCQE_STATUS_FCP_TGT_LENCHECK,
1005
+
SLI4_FC_WCQE_STATUS_RSVD1,
1006
+
SLI4_FC_WCQE_STATUS_ELS_CMPLT_NO_AUTOREG,
1007
+
SLI4_FC_WCQE_STATUS_RSVD2,
1008
+
SLI4_FC_WCQE_STATUS_RQ_SUCCESS,
1009
+
SLI4_FC_WCQE_STATUS_RQ_BUF_LEN_EXCEEDED,
1010
+
SLI4_FC_WCQE_STATUS_RQ_INSUFF_BUF_NEEDED,
1011
+
SLI4_FC_WCQE_STATUS_RQ_INSUFF_FRM_DISC,
1012
+
SLI4_FC_WCQE_STATUS_RQ_DMA_FAILURE,
1013
+
SLI4_FC_WCQE_STATUS_FCP_RSP_TRUNCATE,
1014
+
SLI4_FC_WCQE_STATUS_DI_ERROR,
1015
+
SLI4_FC_WCQE_STATUS_BA_RJT,
1016
+
SLI4_FC_WCQE_STATUS_RQ_INSUFF_XRI_NEEDED,
1017
+
SLI4_FC_WCQE_STATUS_RQ_INSUFF_XRI_DISC,
1018
+
SLI4_FC_WCQE_STATUS_RX_ERROR_DETECT,
1019
+
SLI4_FC_WCQE_STATUS_RX_ABORT_REQUEST,
1020
+
1021
+
/* driver generated status codes */
1022
+
SLI4_FC_WCQE_STATUS_DISPATCH_ERROR = 0xfd,
1023
+
SLI4_FC_WCQE_STATUS_SHUTDOWN = 0xfe,
1024
+
SLI4_FC_WCQE_STATUS_TARGET_WQE_TIMEOUT = 0xff,
1025
+
};
1026
+
1027
+
/* DI_ERROR Extended Status */
1028
+
enum sli4_fc_di_error_status {
1029
+
SLI4_FC_DI_ERROR_GE = 1 << 0,
1030
+
SLI4_FC_DI_ERROR_AE = 1 << 1,
1031
+
SLI4_FC_DI_ERROR_RE = 1 << 2,
1032
+
SLI4_FC_DI_ERROR_TDPV = 1 << 3,
1033
+
SLI4_FC_DI_ERROR_UDB = 1 << 4,
1034
+
SLI4_FC_DI_ERROR_EDIR = 1 << 5,
1035
+
};
1036
+
1037
+
/* WQE DIF field contents */
1038
+
enum sli4_dif_fields {
1039
+
SLI4_DIF_DISABLED,
1040
+
SLI4_DIF_PASS_THROUGH,
1041
+
SLI4_DIF_STRIP,
1042
+
SLI4_DIF_INSERT,
1043
+
};
1044
+
1045
+
/* Work Queue Entry (WQE) types */
1046
+
enum sli4_wqe_types {
1047
+
SLI4_WQE_ABORT = 0x0f,
1048
+
SLI4_WQE_ELS_REQUEST64 = 0x8a,
1049
+
SLI4_WQE_FCP_IBIDIR64 = 0xac,
1050
+
SLI4_WQE_FCP_IREAD64 = 0x9a,
1051
+
SLI4_WQE_FCP_IWRITE64 = 0x98,
1052
+
SLI4_WQE_FCP_ICMND64 = 0x9c,
1053
+
SLI4_WQE_FCP_TRECEIVE64 = 0xa1,
1054
+
SLI4_WQE_FCP_CONT_TRECEIVE64 = 0xe5,
1055
+
SLI4_WQE_FCP_TRSP64 = 0xa3,
1056
+
SLI4_WQE_FCP_TSEND64 = 0x9f,
1057
+
SLI4_WQE_GEN_REQUEST64 = 0xc2,
1058
+
SLI4_WQE_SEND_FRAME = 0xe1,
1059
+
SLI4_WQE_XMIT_BCAST64 = 0x84,
1060
+
SLI4_WQE_XMIT_BLS_RSP = 0x97,
1061
+
SLI4_WQE_ELS_RSP64 = 0x95,
1062
+
SLI4_WQE_XMIT_SEQUENCE64 = 0x82,
1063
+
SLI4_WQE_REQUEUE_XRI = 0x93,
1064
+
};
1065
+
1066
+
/* WQE command types */
1067
+
enum sli4_wqe_cmds {
1068
+
SLI4_CMD_FCP_IREAD64_WQE = 0x00,
1069
+
SLI4_CMD_FCP_ICMND64_WQE = 0x00,
1070
+
SLI4_CMD_FCP_IWRITE64_WQE = 0x01,
1071
+
SLI4_CMD_FCP_TRECEIVE64_WQE = 0x02,
1072
+
SLI4_CMD_FCP_TRSP64_WQE = 0x03,
1073
+
SLI4_CMD_FCP_TSEND64_WQE = 0x07,
1074
+
SLI4_CMD_GEN_REQUEST64_WQE = 0x08,
1075
+
SLI4_CMD_XMIT_BCAST64_WQE = 0x08,
1076
+
SLI4_CMD_XMIT_BLS_RSP64_WQE = 0x08,
1077
+
SLI4_CMD_ABORT_WQE = 0x08,
1078
+
SLI4_CMD_XMIT_SEQUENCE64_WQE = 0x08,
1079
+
SLI4_CMD_REQUEUE_XRI_WQE = 0x0a,
1080
+
SLI4_CMD_SEND_FRAME_WQE = 0x0a,
1081
+
};
1082
+
1083
+
#define SLI4_WQE_SIZE 0x05
1084
+
#define SLI4_WQE_EXT_SIZE 0x06
1085
+
1086
+
#define SLI4_WQE_BYTES (16 * sizeof(u32))
1087
+
#define SLI4_WQE_EXT_BYTES (32 * sizeof(u32))
1088
+
1089
+
/* Mask for ccp (CS_CTL) */
1090
+
#define SLI4_MASK_CCP 0xfe
1091
+
1092
+
/* Generic WQE */
1093
+
enum sli4_gen_wqe_flags {
1094
+
SLI4_GEN_WQE_EBDECNT = 0xf,
1095
+
SLI4_GEN_WQE_LEN_LOC = 0x3 << 7,
1096
+
SLI4_GEN_WQE_QOSD = 1 << 9,
1097
+
SLI4_GEN_WQE_XBL = 1 << 11,
1098
+
SLI4_GEN_WQE_HLM = 1 << 12,
1099
+
SLI4_GEN_WQE_IOD = 1 << 13,
1100
+
SLI4_GEN_WQE_DBDE = 1 << 14,
1101
+
SLI4_GEN_WQE_WQES = 1 << 15,
1102
+
1103
+
SLI4_GEN_WQE_PRI = 0x7,
1104
+
SLI4_GEN_WQE_PV = 1 << 3,
1105
+
SLI4_GEN_WQE_EAT = 1 << 4,
1106
+
SLI4_GEN_WQE_XC = 1 << 5,
1107
+
SLI4_GEN_WQE_CCPE = 1 << 7,
1108
+
1109
+
SLI4_GEN_WQE_CMDTYPE = 0xf,
1110
+
SLI4_GEN_WQE_WQEC = 1 << 7,
1111
+
};
1112
+
1113
+
struct sli4_generic_wqe {
1114
+
__le32 cmd_spec0_5[6];
1115
+
__le16 xri_tag;
1116
+
__le16 context_tag;
1117
+
u8 ct_byte;
1118
+
u8 command;
1119
+
u8 class_byte;
1120
+
u8 timer;
1121
+
__le32 abort_tag;
1122
+
__le16 request_tag;
1123
+
__le16 rsvd34;
1124
+
__le16 dw10w0_flags;
1125
+
u8 eat_xc_ccpe;
1126
+
u8 ccp;
1127
+
u8 cmdtype_wqec_byte;
1128
+
u8 rsvd41;
1129
+
__le16 cq_id;
1130
+
};
1131
+
1132
+
/* WQE used to abort exchanges. */
1133
+
enum sli4_abort_wqe_flags {
1134
+
SLI4_ABRT_WQE_IR = 0x02,
1135
+
1136
+
SLI4_ABRT_WQE_EBDECNT = 0xf,
1137
+
SLI4_ABRT_WQE_LEN_LOC = 0x3 << 7,
1138
+
SLI4_ABRT_WQE_QOSD = 1 << 9,
1139
+
SLI4_ABRT_WQE_XBL = 1 << 11,
1140
+
SLI4_ABRT_WQE_IOD = 1 << 13,
1141
+
SLI4_ABRT_WQE_DBDE = 1 << 14,
1142
+
SLI4_ABRT_WQE_WQES = 1 << 15,
1143
+
1144
+
SLI4_ABRT_WQE_PRI = 0x7,
1145
+
SLI4_ABRT_WQE_PV = 1 << 3,
1146
+
SLI4_ABRT_WQE_EAT = 1 << 4,
1147
+
SLI4_ABRT_WQE_XC = 1 << 5,
1148
+
SLI4_ABRT_WQE_CCPE = 1 << 7,
1149
+
1150
+
SLI4_ABRT_WQE_CMDTYPE = 0xf,
1151
+
SLI4_ABRT_WQE_WQEC = 1 << 7,
1152
+
};
1153
+
1154
+
struct sli4_abort_wqe {
1155
+
__le32 rsvd0;
1156
+
__le32 rsvd4;
1157
+
__le32 ext_t_tag;
1158
+
u8 ia_ir_byte;
1159
+
u8 criteria;
1160
+
__le16 rsvd10;
1161
+
__le32 ext_t_mask;
1162
+
__le32 t_mask;
1163
+
__le16 xri_tag;
1164
+
__le16 context_tag;
1165
+
u8 ct_byte;
1166
+
u8 command;
1167
+
u8 class_byte;
1168
+
u8 timer;
1169
+
__le32 t_tag;
1170
+
__le16 request_tag;
1171
+
__le16 rsvd34;
1172
+
__le16 dw10w0_flags;
1173
+
u8 eat_xc_ccpe;
1174
+
u8 ccp;
1175
+
u8 cmdtype_wqec_byte;
1176
+
u8 rsvd41;
1177
+
__le16 cq_id;
1178
+
};
1179
+
1180
+
enum sli4_abort_criteria {
1181
+
SLI4_ABORT_CRITERIA_XRI_TAG = 0x01,
1182
+
SLI4_ABORT_CRITERIA_ABORT_TAG,
1183
+
SLI4_ABORT_CRITERIA_REQUEST_TAG,
1184
+
SLI4_ABORT_CRITERIA_EXT_ABORT_TAG,
1185
+
};
1186
+
1187
+
enum sli4_abort_type {
1188
+
SLI4_ABORT_XRI,
1189
+
SLI4_ABORT_ABORT_ID,
1190
+
SLI4_ABORT_REQUEST_ID,
1191
+
SLI4_ABORT_MAX, /* must be last */
1192
+
};
1193
+
1194
+
/* WQE used to create an ELS request. */
1195
+
enum sli4_els_req_wqe_flags {
1196
+
SLI4_REQ_WQE_QOSD = 0x2,
1197
+
SLI4_REQ_WQE_DBDE = 0x40,
1198
+
SLI4_REQ_WQE_XBL = 0x8,
1199
+
SLI4_REQ_WQE_XC = 0x20,
1200
+
SLI4_REQ_WQE_IOD = 0x20,
1201
+
SLI4_REQ_WQE_HLM = 0x10,
1202
+
SLI4_REQ_WQE_CCPE = 0x80,
1203
+
SLI4_REQ_WQE_EAT = 0x10,
1204
+
SLI4_REQ_WQE_WQES = 0x80,
1205
+
SLI4_REQ_WQE_PU_SHFT = 4,
1206
+
SLI4_REQ_WQE_CT_SHFT = 2,
1207
+
SLI4_REQ_WQE_CT = 0xc,
1208
+
SLI4_REQ_WQE_ELSID_SHFT = 4,
1209
+
SLI4_REQ_WQE_SP_SHFT = 24,
1210
+
SLI4_REQ_WQE_LEN_LOC_BIT1 = 0x80,
1211
+
SLI4_REQ_WQE_LEN_LOC_BIT2 = 0x1,
1212
+
};
1213
+
1214
+
struct sli4_els_request64_wqe {
1215
+
struct sli4_bde els_request_payload;
1216
+
__le32 els_request_payload_length;
1217
+
__le32 sid_sp_dword;
1218
+
__le32 remote_id_dword;
1219
+
__le16 xri_tag;
1220
+
__le16 context_tag;
1221
+
u8 ct_byte;
1222
+
u8 command;
1223
+
u8 class_byte;
1224
+
u8 timer;
1225
+
__le32 abort_tag;
1226
+
__le16 request_tag;
1227
+
__le16 temporary_rpi;
1228
+
u8 len_loc1_byte;
1229
+
u8 qosd_xbl_hlm_iod_dbde_wqes;
1230
+
u8 eat_xc_ccpe;
1231
+
u8 ccp;
1232
+
u8 cmdtype_elsid_byte;
1233
+
u8 rsvd41;
1234
+
__le16 cq_id;
1235
+
struct sli4_bde els_response_payload_bde;
1236
+
__le32 max_response_payload_length;
1237
+
};
1238
+
1239
+
/* WQE used to create an FCP initiator no data command. */
1240
+
enum sli4_icmd_wqe_flags {
1241
+
SLI4_ICMD_WQE_DBDE = 0x40,
1242
+
SLI4_ICMD_WQE_XBL = 0x8,
1243
+
SLI4_ICMD_WQE_XC = 0x20,
1244
+
SLI4_ICMD_WQE_IOD = 0x20,
1245
+
SLI4_ICMD_WQE_HLM = 0x10,
1246
+
SLI4_ICMD_WQE_CCPE = 0x80,
1247
+
SLI4_ICMD_WQE_EAT = 0x10,
1248
+
SLI4_ICMD_WQE_APPID = 0x10,
1249
+
SLI4_ICMD_WQE_WQES = 0x80,
1250
+
SLI4_ICMD_WQE_PU_SHFT = 4,
1251
+
SLI4_ICMD_WQE_CT_SHFT = 2,
1252
+
SLI4_ICMD_WQE_BS_SHFT = 4,
1253
+
SLI4_ICMD_WQE_LEN_LOC_BIT1 = 0x80,
1254
+
SLI4_ICMD_WQE_LEN_LOC_BIT2 = 0x1,
1255
+
};
1256
+
1257
+
struct sli4_fcp_icmnd64_wqe {
1258
+
struct sli4_bde bde;
1259
+
__le16 payload_offset_length;
1260
+
__le16 fcp_cmd_buffer_length;
1261
+
__le32 rsvd12;
1262
+
__le32 remote_n_port_id_dword;
1263
+
__le16 xri_tag;
1264
+
__le16 context_tag;
1265
+
u8 dif_ct_bs_byte;
1266
+
u8 command;
1267
+
u8 class_pu_byte;
1268
+
u8 timer;
1269
+
__le32 abort_tag;
1270
+
__le16 request_tag;
1271
+
__le16 rsvd34;
1272
+
u8 len_loc1_byte;
1273
+
u8 qosd_xbl_hlm_iod_dbde_wqes;
1274
+
u8 eat_xc_ccpe;
1275
+
u8 ccp;
1276
+
u8 cmd_type_byte;
1277
+
u8 rsvd41;
1278
+
__le16 cq_id;
1279
+
__le32 rsvd44;
1280
+
__le32 rsvd48;
1281
+
__le32 rsvd52;
1282
+
__le32 rsvd56;
1283
+
};
1284
+
1285
+
/* WQE used to create an FCP initiator read. */
1286
+
enum sli4_ir_wqe_flags {
1287
+
SLI4_IR_WQE_DBDE = 0x40,
1288
+
SLI4_IR_WQE_XBL = 0x8,
1289
+
SLI4_IR_WQE_XC = 0x20,
1290
+
SLI4_IR_WQE_IOD = 0x20,
1291
+
SLI4_IR_WQE_HLM = 0x10,
1292
+
SLI4_IR_WQE_CCPE = 0x80,
1293
+
SLI4_IR_WQE_EAT = 0x10,
1294
+
SLI4_IR_WQE_APPID = 0x10,
1295
+
SLI4_IR_WQE_WQES = 0x80,
1296
+
SLI4_IR_WQE_PU_SHFT = 4,
1297
+
SLI4_IR_WQE_CT_SHFT = 2,
1298
+
SLI4_IR_WQE_BS_SHFT = 4,
1299
+
SLI4_IR_WQE_LEN_LOC_BIT1 = 0x80,
1300
+
SLI4_IR_WQE_LEN_LOC_BIT2 = 0x1,
1301
+
};
1302
+
1303
+
struct sli4_fcp_iread64_wqe {
1304
+
struct sli4_bde bde;
1305
+
__le16 payload_offset_length;
1306
+
__le16 fcp_cmd_buffer_length;
1307
+
1308
+
__le32 total_transfer_length;
1309
+
1310
+
__le32 remote_n_port_id_dword;
1311
+
1312
+
__le16 xri_tag;
1313
+
__le16 context_tag;
1314
+
1315
+
u8 dif_ct_bs_byte;
1316
+
u8 command;
1317
+
u8 class_pu_byte;
1318
+
u8 timer;
1319
+
1320
+
__le32 abort_tag;
1321
+
1322
+
__le16 request_tag;
1323
+
__le16 rsvd34;
1324
+
1325
+
u8 len_loc1_byte;
1326
+
u8 qosd_xbl_hlm_iod_dbde_wqes;
1327
+
u8 eat_xc_ccpe;
1328
+
u8 ccp;
1329
+
1330
+
u8 cmd_type_byte;
1331
+
u8 rsvd41;
1332
+
__le16 cq_id;
1333
+
1334
+
__le32 rsvd44;
1335
+
struct sli4_bde first_data_bde;
1336
+
};
1337
+
1338
+
/* WQE used to create an FCP initiator write. */
1339
+
enum sli4_iwr_wqe_flags {
1340
+
SLI4_IWR_WQE_DBDE = 0x40,
1341
+
SLI4_IWR_WQE_XBL = 0x8,
1342
+
SLI4_IWR_WQE_XC = 0x20,
1343
+
SLI4_IWR_WQE_IOD = 0x20,
1344
+
SLI4_IWR_WQE_HLM = 0x10,
1345
+
SLI4_IWR_WQE_DNRX = 0x10,
1346
+
SLI4_IWR_WQE_CCPE = 0x80,
1347
+
SLI4_IWR_WQE_EAT = 0x10,
1348
+
SLI4_IWR_WQE_APPID = 0x10,
1349
+
SLI4_IWR_WQE_WQES = 0x80,
1350
+
SLI4_IWR_WQE_PU_SHFT = 4,
1351
+
SLI4_IWR_WQE_CT_SHFT = 2,
1352
+
SLI4_IWR_WQE_BS_SHFT = 4,
1353
+
SLI4_IWR_WQE_LEN_LOC_BIT1 = 0x80,
1354
+
SLI4_IWR_WQE_LEN_LOC_BIT2 = 0x1,
1355
+
};
1356
+
1357
+
struct sli4_fcp_iwrite64_wqe {
1358
+
struct sli4_bde bde;
1359
+
__le16 payload_offset_length;
1360
+
__le16 fcp_cmd_buffer_length;
1361
+
__le16 total_transfer_length;
1362
+
__le16 initial_transfer_length;
1363
+
__le16 xri_tag;
1364
+
__le16 context_tag;
1365
+
u8 dif_ct_bs_byte;
1366
+
u8 command;
1367
+
u8 class_pu_byte;
1368
+
u8 timer;
1369
+
__le32 abort_tag;
1370
+
__le16 request_tag;
1371
+
__le16 rsvd34;
1372
+
u8 len_loc1_byte;
1373
+
u8 qosd_xbl_hlm_iod_dbde_wqes;
1374
+
u8 eat_xc_ccpe;
1375
+
u8 ccp;
1376
+
u8 cmd_type_byte;
1377
+
u8 rsvd41;
1378
+
__le16 cq_id;
1379
+
__le32 remote_n_port_id_dword;
1380
+
struct sli4_bde first_data_bde;
1381
+
};
1382
+
1383
+
struct sli4_fcp_128byte_wqe {
1384
+
u32 dw[32];
1385
+
};
1386
+
1387
+
/* WQE used to create an FCP target receive */
1388
+
enum sli4_trcv_wqe_flags {
1389
+
SLI4_TRCV_WQE_DBDE = 0x40,
1390
+
SLI4_TRCV_WQE_XBL = 0x8,
1391
+
SLI4_TRCV_WQE_AR = 0x8,
1392
+
SLI4_TRCV_WQE_XC = 0x20,
1393
+
SLI4_TRCV_WQE_IOD = 0x20,
1394
+
SLI4_TRCV_WQE_HLM = 0x10,
1395
+
SLI4_TRCV_WQE_DNRX = 0x10,
1396
+
SLI4_TRCV_WQE_CCPE = 0x80,
1397
+
SLI4_TRCV_WQE_EAT = 0x10,
1398
+
SLI4_TRCV_WQE_APPID = 0x10,
1399
+
SLI4_TRCV_WQE_WQES = 0x80,
1400
+
SLI4_TRCV_WQE_PU_SHFT = 4,
1401
+
SLI4_TRCV_WQE_CT_SHFT = 2,
1402
+
SLI4_TRCV_WQE_BS_SHFT = 4,
1403
+
SLI4_TRCV_WQE_LEN_LOC_BIT2 = 0x1,
1404
+
};
1405
+
1406
+
struct sli4_fcp_treceive64_wqe {
1407
+
struct sli4_bde bde;
1408
+
__le32 payload_offset_length;
1409
+
__le32 relative_offset;
1410
+
union {
1411
+
__le16 sec_xri_tag;
1412
+
__le16 rsvd;
1413
+
__le32 dword;
1414
+
} dword5;
1415
+
__le16 xri_tag;
1416
+
__le16 context_tag;
1417
+
u8 dif_ct_bs_byte;
1418
+
u8 command;
1419
+
u8 class_ar_pu_byte;
1420
+
u8 timer;
1421
+
__le32 abort_tag;
1422
+
__le16 request_tag;
1423
+
__le16 remote_xid;
1424
+
u8 lloc1_appid;
1425
+
u8 qosd_xbl_hlm_iod_dbde_wqes;
1426
+
u8 eat_xc_ccpe;
1427
+
u8 ccp;
1428
+
u8 cmd_type_byte;
1429
+
u8 rsvd41;
1430
+
__le16 cq_id;
1431
+
__le32 fcp_data_receive_length;
1432
+
struct sli4_bde first_data_bde;
1433
+
};
1434
+
1435
+
/* WQE used to create an FCP target response */
1436
+
enum sli4_trsp_wqe_flags {
1437
+
SLI4_TRSP_WQE_AG = 0x8,
1438
+
SLI4_TRSP_WQE_DBDE = 0x40,
1439
+
SLI4_TRSP_WQE_XBL = 0x8,
1440
+
SLI4_TRSP_WQE_XC = 0x20,
1441
+
SLI4_TRSP_WQE_HLM = 0x10,
1442
+
SLI4_TRSP_WQE_DNRX = 0x10,
1443
+
SLI4_TRSP_WQE_CCPE = 0x80,
1444
+
SLI4_TRSP_WQE_EAT = 0x10,
1445
+
SLI4_TRSP_WQE_APPID = 0x10,
1446
+
SLI4_TRSP_WQE_WQES = 0x80,
1447
+
};
1448
+
1449
+
struct sli4_fcp_trsp64_wqe {
1450
+
struct sli4_bde bde;
1451
+
__le32 fcp_response_length;
1452
+
__le32 rsvd12;
1453
+
__le32 dword5;
1454
+
__le16 xri_tag;
1455
+
__le16 rpi;
1456
+
u8 ct_dnrx_byte;
1457
+
u8 command;
1458
+
u8 class_ag_byte;
1459
+
u8 timer;
1460
+
__le32 abort_tag;
1461
+
__le16 request_tag;
1462
+
__le16 remote_xid;
1463
+
u8 lloc1_appid;
1464
+
u8 qosd_xbl_hlm_dbde_wqes;
1465
+
u8 eat_xc_ccpe;
1466
+
u8 ccp;
1467
+
u8 cmd_type_byte;
1468
+
u8 rsvd41;
1469
+
__le16 cq_id;
1470
+
__le32 rsvd44;
1471
+
__le32 rsvd48;
1472
+
__le32 rsvd52;
1473
+
__le32 rsvd56;
1474
+
};
1475
+
1476
+
/* WQE used to create an FCP target send (DATA IN). */
1477
+
enum sli4_tsend_wqe_flags {
1478
+
SLI4_TSEND_WQE_XBL = 0x8,
1479
+
SLI4_TSEND_WQE_DBDE = 0x40,
1480
+
SLI4_TSEND_WQE_IOD = 0x20,
1481
+
SLI4_TSEND_WQE_QOSD = 0x2,
1482
+
SLI4_TSEND_WQE_HLM = 0x10,
1483
+
SLI4_TSEND_WQE_PU_SHFT = 4,
1484
+
SLI4_TSEND_WQE_AR = 0x8,
1485
+
SLI4_TSEND_CT_SHFT = 2,
1486
+
SLI4_TSEND_BS_SHFT = 4,
1487
+
SLI4_TSEND_LEN_LOC_BIT2 = 0x1,
1488
+
SLI4_TSEND_CCPE = 0x80,
1489
+
SLI4_TSEND_APPID_VALID = 0x20,
1490
+
SLI4_TSEND_WQES = 0x80,
1491
+
SLI4_TSEND_XC = 0x20,
1492
+
SLI4_TSEND_EAT = 0x10,
1493
+
};
1494
+
1495
+
struct sli4_fcp_tsend64_wqe {
1496
+
struct sli4_bde bde;
1497
+
__le32 payload_offset_length;
1498
+
__le32 relative_offset;
1499
+
__le32 dword5;
1500
+
__le16 xri_tag;
1501
+
__le16 rpi;
1502
+
u8 ct_byte;
1503
+
u8 command;
1504
+
u8 class_pu_ar_byte;
1505
+
u8 timer;
1506
+
__le32 abort_tag;
1507
+
__le16 request_tag;
1508
+
__le16 remote_xid;
1509
+
u8 dw10byte0;
1510
+
u8 ll_qd_xbl_hlm_iod_dbde;
1511
+
u8 dw10byte2;
1512
+
u8 ccp;
1513
+
u8 cmd_type_byte;
1514
+
u8 rsvd45;
1515
+
__le16 cq_id;
1516
+
__le32 fcp_data_transmit_length;
1517
+
struct sli4_bde first_data_bde;
1518
+
};
1519
+
1520
+
/* WQE used to create a general request. */
1521
+
enum sli4_gen_req_wqe_flags {
1522
+
SLI4_GEN_REQ64_WQE_XBL = 0x8,
1523
+
SLI4_GEN_REQ64_WQE_DBDE = 0x40,
1524
+
SLI4_GEN_REQ64_WQE_IOD = 0x20,
1525
+
SLI4_GEN_REQ64_WQE_QOSD = 0x2,
1526
+
SLI4_GEN_REQ64_WQE_HLM = 0x10,
1527
+
SLI4_GEN_REQ64_CT_SHFT = 2,
1528
+
};
1529
+
1530
+
struct sli4_gen_request64_wqe {
1531
+
struct sli4_bde bde;
1532
+
__le32 request_payload_length;
1533
+
__le32 relative_offset;
1534
+
u8 rsvd17;
1535
+
u8 df_ctl;
1536
+
u8 type;
1537
+
u8 r_ctl;
1538
+
__le16 xri_tag;
1539
+
__le16 context_tag;
1540
+
u8 ct_byte;
1541
+
u8 command;
1542
+
u8 class_byte;
1543
+
u8 timer;
1544
+
__le32 abort_tag;
1545
+
__le16 request_tag;
1546
+
__le16 rsvd34;
1547
+
u8 dw10flags0;
1548
+
u8 dw10flags1;
1549
+
u8 dw10flags2;
1550
+
u8 ccp;
1551
+
u8 cmd_type_byte;
1552
+
u8 rsvd41;
1553
+
__le16 cq_id;
1554
+
__le32 remote_n_port_id_dword;
1555
+
__le32 rsvd48;
1556
+
__le32 rsvd52;
1557
+
__le32 max_response_payload_length;
1558
+
};
1559
+
1560
+
/* WQE used to create a send frame request */
1561
+
enum sli4_sf_wqe_flags {
1562
+
SLI4_SF_WQE_DBDE = 0x40,
1563
+
SLI4_SF_PU = 0x30,
1564
+
SLI4_SF_CT = 0xc,
1565
+
SLI4_SF_QOSD = 0x2,
1566
+
SLI4_SF_LEN_LOC_BIT1 = 0x80,
1567
+
SLI4_SF_LEN_LOC_BIT2 = 0x1,
1568
+
SLI4_SF_XC = 0x20,
1569
+
SLI4_SF_XBL = 0x8,
1570
+
};
1571
+
1572
+
struct sli4_send_frame_wqe {
1573
+
struct sli4_bde bde;
1574
+
__le32 frame_length;
1575
+
__le32 fc_header_0_1[2];
1576
+
__le16 xri_tag;
1577
+
__le16 context_tag;
1578
+
u8 ct_byte;
1579
+
u8 command;
1580
+
u8 dw7flags0;
1581
+
u8 timer;
1582
+
__le32 abort_tag;
1583
+
__le16 request_tag;
1584
+
u8 eof;
1585
+
u8 sof;
1586
+
u8 dw10flags0;
1587
+
u8 dw10flags1;
1588
+
u8 dw10flags2;
1589
+
u8 ccp;
1590
+
u8 cmd_type_byte;
1591
+
u8 rsvd41;
1592
+
__le16 cq_id;
1593
+
__le32 fc_header_2_5[4];
1594
+
};
1595
+
1596
+
/* WQE used to create a transmit sequence */
1597
+
enum sli4_seq_wqe_flags {
1598
+
SLI4_SEQ_WQE_DBDE = 0x4000,
1599
+
SLI4_SEQ_WQE_XBL = 0x800,
1600
+
SLI4_SEQ_WQE_SI = 0x4,
1601
+
SLI4_SEQ_WQE_FT = 0x8,
1602
+
SLI4_SEQ_WQE_XO = 0x40,
1603
+
SLI4_SEQ_WQE_LS = 0x80,
1604
+
SLI4_SEQ_WQE_DIF = 0x3,
1605
+
SLI4_SEQ_WQE_BS = 0x70,
1606
+
SLI4_SEQ_WQE_PU = 0x30,
1607
+
SLI4_SEQ_WQE_HLM = 0x1000,
1608
+
SLI4_SEQ_WQE_IOD_SHIFT = 13,
1609
+
SLI4_SEQ_WQE_CT_SHIFT = 2,
1610
+
SLI4_SEQ_WQE_LEN_LOC_SHIFT = 7,
1611
+
};
1612
+
1613
+
struct sli4_xmit_sequence64_wqe {
1614
+
struct sli4_bde bde;
1615
+
__le32 remote_n_port_id_dword;
1616
+
__le32 relative_offset;
1617
+
u8 dw5flags0;
1618
+
u8 df_ctl;
1619
+
u8 type;
1620
+
u8 r_ctl;
1621
+
__le16 xri_tag;
1622
+
__le16 context_tag;
1623
+
u8 dw7flags0;
1624
+
u8 command;
1625
+
u8 dw7flags1;
1626
+
u8 timer;
1627
+
__le32 abort_tag;
1628
+
__le16 request_tag;
1629
+
__le16 remote_xid;
1630
+
__le16 dw10w0;
1631
+
u8 dw10flags0;
1632
+
u8 ccp;
1633
+
u8 cmd_type_wqec_byte;
1634
+
u8 rsvd45;
1635
+
__le16 cq_id;
1636
+
__le32 sequence_payload_len;
1637
+
__le32 rsvd48;
1638
+
__le32 rsvd52;
1639
+
__le32 rsvd56;
1640
+
};
1641
+
1642
+
/*
1643
+
* WQE used unblock the specified XRI and to release
1644
+
* it to the SLI Port's free pool.
1645
+
*/
1646
+
enum sli4_requeue_wqe_flags {
1647
+
SLI4_REQU_XRI_WQE_XC = 0x20,
1648
+
SLI4_REQU_XRI_WQE_QOSD = 0x2,
1649
+
};
1650
+
1651
+
struct sli4_requeue_xri_wqe {
1652
+
__le32 rsvd0;
1653
+
__le32 rsvd4;
1654
+
__le32 rsvd8;
1655
+
__le32 rsvd12;
1656
+
__le32 rsvd16;
1657
+
__le32 rsvd20;
1658
+
__le16 xri_tag;
1659
+
__le16 context_tag;
1660
+
u8 ct_byte;
1661
+
u8 command;
1662
+
u8 class_byte;
1663
+
u8 timer;
1664
+
__le32 rsvd32;
1665
+
__le16 request_tag;
1666
+
__le16 rsvd34;
1667
+
__le16 flags0;
1668
+
__le16 flags1;
1669
+
__le16 flags2;
1670
+
u8 ccp;
1671
+
u8 cmd_type_wqec_byte;
1672
+
u8 rsvd42;
1673
+
__le16 cq_id;
1674
+
__le32 rsvd44;
1675
+
__le32 rsvd48;
1676
+
__le32 rsvd52;
1677
+
__le32 rsvd56;
1678
+
};
1679
+
1680
+
/* WQE used to create a BLS response */
1681
+
enum sli4_bls_rsp_wqe_flags {
1682
+
SLI4_BLS_RSP_RID = 0xffffff,
1683
+
SLI4_BLS_RSP_WQE_AR = 0x40000000,
1684
+
SLI4_BLS_RSP_WQE_CT_SHFT = 2,
1685
+
SLI4_BLS_RSP_WQE_QOSD = 0x2,
1686
+
SLI4_BLS_RSP_WQE_HLM = 0x10,
1687
+
};
1688
+
1689
+
struct sli4_xmit_bls_rsp_wqe {
1690
+
__le32 payload_word0;
1691
+
__le16 rx_id;
1692
+
__le16 ox_id;
1693
+
__le16 high_seq_cnt;
1694
+
__le16 low_seq_cnt;
1695
+
__le32 rsvd12;
1696
+
__le32 local_n_port_id_dword;
1697
+
__le32 remote_id_dword;
1698
+
__le16 xri_tag;
1699
+
__le16 context_tag;
1700
+
u8 dw8flags0;
1701
+
u8 command;
1702
+
u8 dw8flags1;
1703
+
u8 timer;
1704
+
__le32 abort_tag;
1705
+
__le16 request_tag;
1706
+
__le16 rsvd38;
1707
+
u8 dw11flags0;
1708
+
u8 dw11flags1;
1709
+
u8 dw11flags2;
1710
+
u8 ccp;
1711
+
u8 dw12flags0;
1712
+
u8 rsvd45;
1713
+
__le16 cq_id;
1714
+
__le16 temporary_rpi;
1715
+
u8 rsvd50;
1716
+
u8 rsvd51;
1717
+
__le32 rsvd52;
1718
+
__le32 rsvd56;
1719
+
__le32 rsvd60;
1720
+
};
1721
+
1722
+
enum sli_bls_type {
1723
+
SLI4_SLI_BLS_ACC,
1724
+
SLI4_SLI_BLS_RJT,
1725
+
SLI4_SLI_BLS_MAX
1726
+
};
1727
+
1728
+
struct sli_bls_payload {
1729
+
enum sli_bls_type type;
1730
+
__le16 ox_id;
1731
+
__le16 rx_id;
1732
+
union {
1733
+
struct {
1734
+
u8 seq_id_validity;
1735
+
u8 seq_id_last;
1736
+
u8 rsvd2;
1737
+
u8 rsvd3;
1738
+
u16 ox_id;
1739
+
u16 rx_id;
1740
+
__le16 low_seq_cnt;
1741
+
__le16 high_seq_cnt;
1742
+
} acc;
1743
+
struct {
1744
+
u8 vendor_unique;
1745
+
u8 reason_explanation;
1746
+
u8 reason_code;
1747
+
u8 rsvd3;
1748
+
} rjt;
1749
+
} u;
1750
+
};
1751
+
1752
+
/* WQE used to create an ELS response */
1753
+
1754
+
enum sli4_els_rsp_flags {
1755
+
SLI4_ELS_SID = 0xffffff,
1756
+
SLI4_ELS_RID = 0xffffff,
1757
+
SLI4_ELS_DBDE = 0x40,
1758
+
SLI4_ELS_XBL = 0x8,
1759
+
SLI4_ELS_IOD = 0x20,
1760
+
SLI4_ELS_QOSD = 0x2,
1761
+
SLI4_ELS_XC = 0x20,
1762
+
SLI4_ELS_CT_OFFSET = 0X2,
1763
+
SLI4_ELS_SP = 0X1000000,
1764
+
SLI4_ELS_HLM = 0X10,
1765
+
};
1766
+
1767
+
struct sli4_xmit_els_rsp64_wqe {
1768
+
struct sli4_bde els_response_payload;
1769
+
__le32 els_response_payload_length;
1770
+
__le32 sid_dw;
1771
+
__le32 rid_dw;
1772
+
__le16 xri_tag;
1773
+
__le16 context_tag;
1774
+
u8 ct_byte;
1775
+
u8 command;
1776
+
u8 class_byte;
1777
+
u8 timer;
1778
+
__le32 abort_tag;
1779
+
__le16 request_tag;
1780
+
__le16 ox_id;
1781
+
u8 flags1;
1782
+
u8 flags2;
1783
+
u8 flags3;
1784
+
u8 flags4;
1785
+
u8 cmd_type_wqec;
1786
+
u8 rsvd34;
1787
+
__le16 cq_id;
1788
+
__le16 temporary_rpi;
1789
+
__le16 rsvd38;
1790
+
u32 rsvd40;
1791
+
u32 rsvd44;
1792
+
u32 rsvd48;
1793
+
};
1794
+
1795
+
/* Local Reject Reason Codes */
1796
+
enum sli4_fc_local_rej_codes {
1797
+
SLI4_FC_LOCAL_REJECT_UNKNOWN,
1798
+
SLI4_FC_LOCAL_REJECT_MISSING_CONTINUE,
1799
+
SLI4_FC_LOCAL_REJECT_SEQUENCE_TIMEOUT,
1800
+
SLI4_FC_LOCAL_REJECT_INTERNAL_ERROR,
1801
+
SLI4_FC_LOCAL_REJECT_INVALID_RPI,
1802
+
SLI4_FC_LOCAL_REJECT_NO_XRI,
1803
+
SLI4_FC_LOCAL_REJECT_ILLEGAL_COMMAND,
1804
+
SLI4_FC_LOCAL_REJECT_XCHG_DROPPED,
1805
+
SLI4_FC_LOCAL_REJECT_ILLEGAL_FIELD,
1806
+
SLI4_FC_LOCAL_REJECT_RPI_SUSPENDED,
1807
+
SLI4_FC_LOCAL_REJECT_RSVD,
1808
+
SLI4_FC_LOCAL_REJECT_RSVD1,
1809
+
SLI4_FC_LOCAL_REJECT_NO_ABORT_MATCH,
1810
+
SLI4_FC_LOCAL_REJECT_TX_DMA_FAILED,
1811
+
SLI4_FC_LOCAL_REJECT_RX_DMA_FAILED,
1812
+
SLI4_FC_LOCAL_REJECT_ILLEGAL_FRAME,
1813
+
SLI4_FC_LOCAL_REJECT_RSVD2,
1814
+
SLI4_FC_LOCAL_REJECT_NO_RESOURCES, //0x11
1815
+
SLI4_FC_LOCAL_REJECT_FCP_CONF_FAILURE,
1816
+
SLI4_FC_LOCAL_REJECT_ILLEGAL_LENGTH,
1817
+
SLI4_FC_LOCAL_REJECT_UNSUPPORTED_FEATURE,
1818
+
SLI4_FC_LOCAL_REJECT_ABORT_IN_PROGRESS,
1819
+
SLI4_FC_LOCAL_REJECT_ABORT_REQUESTED,
1820
+
SLI4_FC_LOCAL_REJECT_RCV_BUFFER_TIMEOUT,
1821
+
SLI4_FC_LOCAL_REJECT_LOOP_OPEN_FAILURE,
1822
+
SLI4_FC_LOCAL_REJECT_RSVD3,
1823
+
SLI4_FC_LOCAL_REJECT_LINK_DOWN,
1824
+
SLI4_FC_LOCAL_REJECT_CORRUPTED_DATA,
1825
+
SLI4_FC_LOCAL_REJECT_CORRUPTED_RPI,
1826
+
SLI4_FC_LOCAL_REJECT_OUTOFORDER_DATA,
1827
+
SLI4_FC_LOCAL_REJECT_OUTOFORDER_ACK,
1828
+
SLI4_FC_LOCAL_REJECT_DUP_FRAME,
1829
+
SLI4_FC_LOCAL_REJECT_LINK_CONTROL_FRAME, //0x20
1830
+
SLI4_FC_LOCAL_REJECT_BAD_HOST_ADDRESS,
1831
+
SLI4_FC_LOCAL_REJECT_RSVD4,
1832
+
SLI4_FC_LOCAL_REJECT_MISSING_HDR_BUFFER,
1833
+
SLI4_FC_LOCAL_REJECT_MSEQ_CHAIN_CORRUPTED,
1834
+
SLI4_FC_LOCAL_REJECT_ABORTMULT_REQUESTED,
1835
+
SLI4_FC_LOCAL_REJECT_BUFFER_SHORTAGE = 0x28,
1836
+
SLI4_FC_LOCAL_REJECT_RCV_XRIBUF_WAITING,
1837
+
SLI4_FC_LOCAL_REJECT_INVALID_VPI = 0x2e,
1838
+
SLI4_FC_LOCAL_REJECT_NO_FPORT_DETECTED,
1839
+
SLI4_FC_LOCAL_REJECT_MISSING_XRIBUF,
1840
+
SLI4_FC_LOCAL_REJECT_RSVD5,
1841
+
SLI4_FC_LOCAL_REJECT_INVALID_XRI,
1842
+
SLI4_FC_LOCAL_REJECT_INVALID_RELOFFSET = 0x40,
1843
+
SLI4_FC_LOCAL_REJECT_MISSING_RELOFFSET,
1844
+
SLI4_FC_LOCAL_REJECT_INSUFF_BUFFERSPACE,
1845
+
SLI4_FC_LOCAL_REJECT_MISSING_SI,
1846
+
SLI4_FC_LOCAL_REJECT_MISSING_ES,
1847
+
SLI4_FC_LOCAL_REJECT_INCOMPLETE_XFER,
1848
+
SLI4_FC_LOCAL_REJECT_SLER_FAILURE,
1849
+
SLI4_FC_LOCAL_REJECT_SLER_CMD_RCV_FAILURE,
1850
+
SLI4_FC_LOCAL_REJECT_SLER_REC_RJT_ERR,
1851
+
SLI4_FC_LOCAL_REJECT_SLER_REC_SRR_RETRY_ERR,
1852
+
SLI4_FC_LOCAL_REJECT_SLER_SRR_RJT_ERR,
1853
+
SLI4_FC_LOCAL_REJECT_RSVD6,
1854
+
SLI4_FC_LOCAL_REJECT_SLER_RRQ_RJT_ERR,
1855
+
SLI4_FC_LOCAL_REJECT_SLER_RRQ_RETRY_ERR,
1856
+
SLI4_FC_LOCAL_REJECT_SLER_ABTS_ERR,
1857
+
};
1858
+
1859
+
enum sli4_async_rcqe_flags {
1860
+
SLI4_RACQE_RQ_EL_INDX = 0xfff,
1861
+
SLI4_RACQE_FCFI = 0x3f,
1862
+
SLI4_RACQE_HDPL = 0x3f,
1863
+
SLI4_RACQE_RQ_ID = 0xffc0,
1864
+
};
1865
+
1866
+
struct sli4_fc_async_rcqe {
1867
+
u8 rsvd0;
1868
+
u8 status;
1869
+
__le16 rq_elmt_indx_word;
1870
+
__le32 rsvd4;
1871
+
__le16 fcfi_rq_id_word;
1872
+
__le16 data_placement_length;
1873
+
u8 sof_byte;
1874
+
u8 eof_byte;
1875
+
u8 code;
1876
+
u8 hdpl_byte;
1877
+
};
1878
+
1879
+
struct sli4_fc_async_rcqe_v1 {
1880
+
u8 rsvd0;
1881
+
u8 status;
1882
+
__le16 rq_elmt_indx_word;
1883
+
u8 fcfi_byte;
1884
+
u8 rsvd5;
1885
+
__le16 rsvd6;
1886
+
__le16 rq_id;
1887
+
__le16 data_placement_length;
1888
+
u8 sof_byte;
1889
+
u8 eof_byte;
1890
+
u8 code;
1891
+
u8 hdpl_byte;
1892
+
};
1893
+
1894
+
enum sli4_fc_async_rq_status {
1895
+
SLI4_FC_ASYNC_RQ_SUCCESS = 0x10,
1896
+
SLI4_FC_ASYNC_RQ_BUF_LEN_EXCEEDED,
1897
+
SLI4_FC_ASYNC_RQ_INSUFF_BUF_NEEDED,
1898
+
SLI4_FC_ASYNC_RQ_INSUFF_BUF_FRM_DISC,
1899
+
SLI4_FC_ASYNC_RQ_DMA_FAILURE,
1900
+
};
1901
+
1902
+
#define SLI4_RCQE_RQ_EL_INDX 0xfff
1903
+
1904
+
struct sli4_fc_coalescing_rcqe {
1905
+
u8 rsvd0;
1906
+
u8 status;
1907
+
__le16 rq_elmt_indx_word;
1908
+
__le32 rsvd4;
1909
+
__le16 rq_id;
1910
+
__le16 seq_placement_length;
1911
+
__le16 rsvd14;
1912
+
u8 code;
1913
+
u8 vld_byte;
1914
+
};
1915
+
1916
+
#define SLI4_FC_COALESCE_RQ_SUCCESS 0x10
1917
+
#define SLI4_FC_COALESCE_RQ_INSUFF_XRI_NEEDED 0x18
1918
+
1919
+
enum sli4_optimized_write_cmd_cqe_flags {
1920
+
SLI4_OCQE_RQ_EL_INDX = 0x7f, /* DW0 bits 16:30 */
1921
+
SLI4_OCQE_FCFI = 0x3f, /* DW1 bits 0:6 */
1922
+
SLI4_OCQE_OOX = 1 << 6, /* DW1 bit 15 */
1923
+
SLI4_OCQE_AGXR = 1 << 7, /* DW1 bit 16 */
1924
+
SLI4_OCQE_HDPL = 0x3f, /* DW3 bits 24:29*/
1925
+
};
1926
+
1927
+
struct sli4_fc_optimized_write_cmd_cqe {
1928
+
u8 rsvd0;
1929
+
u8 status;
1930
+
__le16 w1;
1931
+
u8 flags0;
1932
+
u8 flags1;
1933
+
__le16 xri;
1934
+
__le16 rq_id;
1935
+
__le16 data_placement_length;
1936
+
__le16 rpi;
1937
+
u8 code;
1938
+
u8 hdpl_vld;
1939
+
};
1940
+
1941
+
#define SLI4_OCQE_XB 0x10
1942
+
1943
+
struct sli4_fc_optimized_write_data_cqe {
1944
+
u8 hw_status;
1945
+
u8 status;
1946
+
__le16 xri;
1947
+
__le32 total_data_placed;
1948
+
__le32 extended_status;
1949
+
__le16 rsvd12;
1950
+
u8 code;
1951
+
u8 flags;
1952
+
};
1953
+
1954
+
struct sli4_fc_xri_aborted_cqe {
1955
+
u8 rsvd0;
1956
+
u8 status;
1957
+
__le16 rsvd2;
1958
+
__le32 extended_status;
1959
+
__le16 xri;
1960
+
__le16 remote_xid;
1961
+
__le16 rsvd12;
1962
+
u8 code;
1963
+
u8 flags;
1964
+
};
1965
+
1966
+
enum sli4_generic_ctx {
1967
+
SLI4_GENERIC_CONTEXT_RPI,
1968
+
SLI4_GENERIC_CONTEXT_VPI,
1969
+
SLI4_GENERIC_CONTEXT_VFI,
1970
+
SLI4_GENERIC_CONTEXT_FCFI,
1971
+
};
1972
+
1973
+
#define SLI4_GENERIC_CLASS_CLASS_2 0x1
1974
+
#define SLI4_GENERIC_CLASS_CLASS_3 0x2
1975
+
1976
+
#define SLI4_ELS_REQUEST64_DIR_WRITE 0x0
1977
+
#define SLI4_ELS_REQUEST64_DIR_READ 0x1
1978
+
1979
+
enum sli4_els_request {
1980
+
SLI4_ELS_REQUEST64_OTHER,
1981
+
SLI4_ELS_REQUEST64_LOGO,
1982
+
SLI4_ELS_REQUEST64_FDISC,
1983
+
SLI4_ELS_REQUEST64_FLOGIN,
1984
+
SLI4_ELS_REQUEST64_PLOGI,
1985
+
};
1986
+
1987
+
enum sli4_els_cmd_type {
1988
+
SLI4_ELS_REQUEST64_CMD_GEN = 0x08,
1989
+
SLI4_ELS_REQUEST64_CMD_NON_FABRIC = 0x0c,
1990
+
SLI4_ELS_REQUEST64_CMD_FABRIC = 0x0d,
1991
+
};
1992
+
1993
+
/******Driver specific structures******/
1994
+
1995
+
struct sli4_queue {
1996
+
/* Common to all queue types */
1997
+
struct efc_dma dma;
1998
+
spinlock_t lock; /* Lock to protect the doorbell register
1999
+
* writes and queue reads
2000
+
*/
2001
+
u32 index; /* current host entry index */
2002
+
u16 size; /* entry size */
2003
+
u16 length; /* number of entries */
2004
+
u16 n_posted; /* number entries posted for CQ, EQ */
2005
+
u16 id; /* Port assigned xQ_ID */
2006
+
u8 type; /* queue type ie EQ, CQ, ... */
2007
+
void __iomem *db_regaddr; /* register address for the doorbell */
2008
+
u16 phase; /* For if_type = 6, this value toggle
2009
+
* for each iteration of the queue,
2010
+
* a queue entry is valid when a cqe
2011
+
* valid bit matches this value
2012
+
*/
2013
+
u32 proc_limit; /* limit CQE processed per iteration */
2014
+
u32 posted_limit; /* CQE/EQE process before ring db */
2015
+
u32 max_num_processed;
2016
+
u64 max_process_time;
2017
+
union {
2018
+
u32 r_idx; /* "read" index (MQ only) */
2019
+
u32 flag;
2020
+
} u;
2021
+
};
2022
+
2023
+
/* Parameters used to populate WQE*/
2024
+
struct sli_bls_params {
2025
+
u32 s_id;
2026
+
u32 d_id;
2027
+
u16 ox_id;
2028
+
u16 rx_id;
2029
+
u32 rpi;
2030
+
u32 vpi;
2031
+
bool rpi_registered;
2032
+
u8 payload[12];
2033
+
u16 xri;
2034
+
u16 tag;
2035
+
};
2036
+
2037
+
struct sli_els_params {
2038
+
u32 s_id;
2039
+
u32 d_id;
2040
+
u16 ox_id;
2041
+
u32 rpi;
2042
+
u32 vpi;
2043
+
bool rpi_registered;
2044
+
u32 xmit_len;
2045
+
u32 rsp_len;
2046
+
u8 timeout;
2047
+
u8 cmd;
2048
+
u16 xri;
2049
+
u16 tag;
2050
+
};
2051
+
2052
+
struct sli_ct_params {
2053
+
u8 r_ctl;
2054
+
u8 type;
2055
+
u8 df_ctl;
2056
+
u8 timeout;
2057
+
u16 ox_id;
2058
+
u32 d_id;
2059
+
u32 rpi;
2060
+
u32 vpi;
2061
+
bool rpi_registered;
2062
+
u32 xmit_len;
2063
+
u32 rsp_len;
2064
+
u16 xri;
2065
+
u16 tag;
2066
+
};
2067
+
2068
+
struct sli_fcp_tgt_params {
2069
+
u32 s_id;
2070
+
u32 d_id;
2071
+
u32 rpi;
2072
+
u32 vpi;
2073
+
u32 offset;
2074
+
u16 ox_id;
2075
+
u16 flags;
2076
+
u8 cs_ctl;
2077
+
u8 timeout;
2078
+
u32 app_id;
2079
+
u32 xmit_len;
2080
+
u16 xri;
2081
+
u16 tag;
2082
+
};
2083
+
308
2084
#endif /* !_SLI4_H */