Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'dmaengine-5.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
Pull dmaengine updates from Vinod Koul:
"This time around we have a smaller pull request than usual and this
includes code removal, so should be good!
New drivers/devices
- Support for QCOM SM8250 GPI DMA
- removal of shdma-of driver and binding
Updates:
- arm-pl08x yaml binding move
- altera-msgdma gained DT support
- removal of imx-sdma platform data support
- idxd and xilinx driver updates"
* tag 'dmaengine-5.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (22 commits)
dmaengine: imx-sdma: Remove platform data header
dmaengine: xilinx: dpdma: Fix spacing around addr[i-1]
dmaengine: xilinx: dpdma: Use kernel type u32 over uint32_t
dmaengine: altera-msgdma: add OF support
MAINTAINERS: add entry for Altera mSGDMA
dt-bindings: dma: add schema for altera-msgdma
dmaengine: xilinx: dpdma: fix kernel-doc
dmaengine: sf-pdma: apply proper spinlock flags in sf_pdma_prep_dma_memcpy()
dmaengine: sh: Remove unused shdma-of driver
dt-bindings: dmaengine: Remove SHDMA Device Tree bindings
dmaengine: qcom: gpi: Add SM8250 compatible
dt-bindings: dmaengine: qcom: gpi: add compatible for sm8250
dmaengine: sun4i: Use list_move_tail instead of list_del/list_add_tail
dmaengine: ti: omap-dma: Skip pointless cpu_pm context restore on errors
dmaengine: hsu: Account transferred bytes
dmaengine: Move kdoc description of struct dma_chan_percpu closer to it
dmaengine: xilinx: dpdma: Print debug message when losing vsync race
dmaengine: xilinx: dpdma: Print channel number in kernel log messages
dt-bindings: dma: convert arm-pl08x to yaml
dmaengine: idxd: remove devm allocation for idxd->int_handles
...
+333
-313
+61
Documentation/devicetree/bindings/dma/altr,msgdma.yaml
+61
Documentation/devicetree/bindings/dma/altr,msgdma.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/dma/altr,msgdma.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Altera mSGDMA IP core
8
+
9
+
maintainers:
10
+
- Olivier Dautricourt <olivier.dautricourt@orolia.com>
11
+
12
+
description: |
13
+
Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA)
14
+
intellectual property (IP)
15
+
16
+
allOf:
17
+
- $ref: "dma-controller.yaml#"
18
+
19
+
properties:
20
+
compatible:
21
+
const: altr,socfpga-msgdma
22
+
23
+
reg:
24
+
items:
25
+
- description: Control and Status Register Slave Port
26
+
- description: Descriptor Slave Port
27
+
- description: Response Slave Port
28
+
29
+
reg-names:
30
+
items:
31
+
- const: csr
32
+
- const: desc
33
+
- const: resp
34
+
35
+
interrupts:
36
+
maxItems: 1
37
+
38
+
"#dma-cells":
39
+
const: 1
40
+
description:
41
+
The cell identifies the channel id (must be 0)
42
+
43
+
required:
44
+
- compatible
45
+
- reg
46
+
- reg-names
47
+
- interrupts
48
+
49
+
unevaluatedProperties: false
50
+
51
+
examples:
52
+
- |
53
+
#include <dt-bindings/interrupt-controller/irq.h>
54
+
55
+
msgdma_controller: dma-controller@ff200b00 {
56
+
compatible = "altr,socfpga-msgdma";
57
+
reg = <0xff200b00 0x100>, <0xff200c00 0x100>, <0xff200d00 0x100>;
58
+
reg-names = "csr", "desc", "resp";
59
+
interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
60
+
#dma-cells = <1>;
61
+
};
-59
Documentation/devicetree/bindings/dma/arm-pl08x.txt
-59
Documentation/devicetree/bindings/dma/arm-pl08x.txt
···
1
-
* ARM PrimeCells PL080 and PL081 and derivatives DMA controller
2
-
3
-
Required properties:
4
-
- compatible: "arm,pl080", "arm,primecell";
5
-
"arm,pl081", "arm,primecell";
6
-
"faraday,ftdmac020", "arm,primecell"
7
-
- arm,primecell-periphid: on the FTDMAC020 the primecell ID is not hard-coded
8
-
in the hardware and must be specified here as <0x0003b080>. This number
9
-
follows the PrimeCell standard numbering using the JEP106 vendor code 0x38
10
-
for Faraday Technology.
11
-
- reg: Address range of the PL08x registers
12
-
- interrupt: The PL08x interrupt number
13
-
- clocks: The clock running the IP core clock
14
-
- clock-names: Must contain "apb_pclk"
15
-
- lli-bus-interface-ahb1: if AHB master 1 is eligible for fetching LLIs
16
-
- lli-bus-interface-ahb2: if AHB master 2 is eligible for fetching LLIs
17
-
- mem-bus-interface-ahb1: if AHB master 1 is eligible for fetching memory contents
18
-
- mem-bus-interface-ahb2: if AHB master 2 is eligible for fetching memory contents
19
-
- #dma-cells: must be <2>. First cell should contain the DMA request,
20
-
second cell should contain either 1 or 2 depending on
21
-
which AHB master that is used.
22
-
23
-
Optional properties:
24
-
- dma-channels: contains the total number of DMA channels supported by the DMAC
25
-
- dma-requests: contains the total number of DMA requests supported by the DMAC
26
-
- memcpy-burst-size: the size of the bursts for memcpy: 1, 4, 8, 16, 32
27
-
64, 128 or 256 bytes are legal values
28
-
- memcpy-bus-width: the bus width used for memcpy in bits: 8, 16 or 32 are legal
29
-
values, the Faraday FTDMAC020 can also accept 64 bits
30
-
31
-
Clients
32
-
Required properties:
33
-
- dmas: List of DMA controller phandle, request channel and AHB master id
34
-
- dma-names: Names of the aforementioned requested channels
35
-
36
-
Example:
37
-
38
-
dmac0: dma-controller@10130000 {
39
-
compatible = "arm,pl080", "arm,primecell";
40
-
reg = <0x10130000 0x1000>;
41
-
interrupt-parent = <&vica>;
42
-
interrupts = <15>;
43
-
clocks = <&hclkdma0>;
44
-
clock-names = "apb_pclk";
45
-
lli-bus-interface-ahb1;
46
-
lli-bus-interface-ahb2;
47
-
mem-bus-interface-ahb2;
48
-
memcpy-burst-size = <256>;
49
-
memcpy-bus-width = <32>;
50
-
#dma-cells = <2>;
51
-
};
52
-
53
-
device@40008000 {
54
-
...
55
-
dmas = <&dmac0 0 2
56
-
&dmac0 1 2>;
57
-
dma-names = "tx", "rx";
58
-
...
59
-
};
+136
Documentation/devicetree/bindings/dma/arm-pl08x.yaml
+136
Documentation/devicetree/bindings/dma/arm-pl08x.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/dma/arm-pl08x.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: ARM PrimeCells PL080 and PL081 and derivatives DMA controller
8
+
9
+
maintainers:
10
+
- Vinod Koul <vkoul@kernel.org>
11
+
12
+
allOf:
13
+
- $ref: "dma-controller.yaml#"
14
+
15
+
# We need a select here so we don't match all nodes with 'arm,primecell'
16
+
select:
17
+
properties:
18
+
compatible:
19
+
contains:
20
+
enum:
21
+
- arm,pl080
22
+
- arm,pl081
23
+
required:
24
+
- compatible
25
+
26
+
properties:
27
+
compatible:
28
+
oneOf:
29
+
- items:
30
+
- enum:
31
+
- arm,pl080
32
+
- arm,pl081
33
+
- const: arm,primecell
34
+
- items:
35
+
- const: faraday,ftdma020
36
+
- const: arm,pl080
37
+
- const: arm,primecell
38
+
39
+
reg:
40
+
maxItems: 1
41
+
description: Address range of the PL08x registers
42
+
43
+
interrupts:
44
+
minItems: 1
45
+
description: The PL08x interrupt number
46
+
47
+
clocks:
48
+
minItems: 1
49
+
description: The clock running the IP core clock
50
+
51
+
clock-names:
52
+
maxItems: 1
53
+
54
+
lli-bus-interface-ahb1:
55
+
type: boolean
56
+
description: if AHB master 1 is eligible for fetching LLIs
57
+
58
+
lli-bus-interface-ahb2:
59
+
type: boolean
60
+
description: if AHB master 2 is eligible for fetching LLIs
61
+
62
+
mem-bus-interface-ahb1:
63
+
type: boolean
64
+
description: if AHB master 1 is eligible for fetching memory contents
65
+
66
+
mem-bus-interface-ahb2:
67
+
type: boolean
68
+
description: if AHB master 2 is eligible for fetching memory contents
69
+
70
+
memcpy-burst-size:
71
+
$ref: /schemas/types.yaml#/definitions/uint32
72
+
enum:
73
+
- 1
74
+
- 4
75
+
- 8
76
+
- 16
77
+
- 32
78
+
- 64
79
+
- 128
80
+
- 256
81
+
description: the size of the bursts for memcpy
82
+
83
+
memcpy-bus-width:
84
+
$ref: /schemas/types.yaml#/definitions/uint32
85
+
enum:
86
+
- 8
87
+
- 16
88
+
- 32
89
+
- 64
90
+
description: bus width used for memcpy in bits. FTDMAC020 also accept 64 bits
91
+
92
+
required:
93
+
- reg
94
+
- interrupts
95
+
- clocks
96
+
- clock-names
97
+
- "#dma-cells"
98
+
99
+
unevaluatedProperties: false
100
+
101
+
examples:
102
+
- |
103
+
dmac0: dma-controller@10130000 {
104
+
compatible = "arm,pl080", "arm,primecell";
105
+
reg = <0x10130000 0x1000>;
106
+
interrupt-parent = <&vica>;
107
+
interrupts = <15>;
108
+
clocks = <&hclkdma0>;
109
+
clock-names = "apb_pclk";
110
+
lli-bus-interface-ahb1;
111
+
lli-bus-interface-ahb2;
112
+
mem-bus-interface-ahb2;
113
+
memcpy-burst-size = <256>;
114
+
memcpy-bus-width = <32>;
115
+
#dma-cells = <2>;
116
+
};
117
+
- |
118
+
#include <dt-bindings/interrupt-controller/irq.h>
119
+
#include <dt-bindings/reset/cortina,gemini-reset.h>
120
+
#include <dt-bindings/clock/cortina,gemini-clock.h>
121
+
dma-controller@67000000 {
122
+
compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell";
123
+
/* Faraday Technology FTDMAC020 variant */
124
+
arm,primecell-periphid = <0x0003b080>;
125
+
reg = <0x67000000 0x1000>;
126
+
interrupts = <9 IRQ_TYPE_EDGE_RISING>;
127
+
resets = <&syscon GEMINI_RESET_DMAC>;
128
+
clocks = <&syscon GEMINI_CLK_AHB>;
129
+
clock-names = "apb_pclk";
130
+
/* Bus interface AHB1 (AHB0) is totally tilted */
131
+
lli-bus-interface-ahb2;
132
+
mem-bus-interface-ahb2;
133
+
memcpy-burst-size = <256>;
134
+
memcpy-bus-width = <32>;
135
+
#dma-cells = <2>;
136
+
};
+1
Documentation/devicetree/bindings/dma/qcom,gpi.yaml
+1
Documentation/devicetree/bindings/dma/qcom,gpi.yaml
-84
Documentation/devicetree/bindings/dma/renesas,shdma.txt
-84
Documentation/devicetree/bindings/dma/renesas,shdma.txt
···
1
-
* SHDMA Device Tree bindings
2
-
3
-
Sh-/r-mobile and R-Car systems often have multiple identical DMA controller
4
-
instances, capable of serving any of a common set of DMA slave devices, using
5
-
the same configuration. To describe this topology we require all compatible
6
-
SHDMA DT nodes to be placed under a DMA multiplexer node. All such compatible
7
-
DMAC instances have the same number of channels and use the same DMA
8
-
descriptors. Therefore respective DMA DT bindings can also all be placed in the
9
-
multiplexer node. Even if there is only one such DMAC instance on a system, it
10
-
still has to be placed under such a multiplexer node.
11
-
12
-
* DMA multiplexer
13
-
14
-
Required properties:
15
-
- compatible: should be "renesas,shdma-mux"
16
-
- #dma-cells: should be <1>, see "dmas" property below
17
-
18
-
Optional properties (currently unused):
19
-
- dma-channels: number of DMA channels
20
-
- dma-requests: number of DMA request signals
21
-
22
-
* DMA controller
23
-
24
-
Required properties:
25
-
- compatible: should be of the form "renesas,shdma-<soc>", where <soc> should
26
-
be replaced with the desired SoC model, e.g.
27
-
"renesas,shdma-r8a73a4" for the system DMAC on r8a73a4 SoC
28
-
29
-
Example:
30
-
dmac: dma-multiplexer@0 {
31
-
compatible = "renesas,shdma-mux";
32
-
#dma-cells = <1>;
33
-
dma-channels = <20>;
34
-
dma-requests = <256>;
35
-
#address-cells = <2>;
36
-
#size-cells = <2>;
37
-
ranges;
38
-
39
-
dma0: dma-controller@e6700020 {
40
-
compatible = "renesas,shdma-r8a73a4";
41
-
reg = <0 0xe6700020 0 0x89e0>;
42
-
interrupt-parent = <&gic>;
43
-
interrupts = <0 220 4
44
-
0 200 4
45
-
0 201 4
46
-
0 202 4
47
-
0 203 4
48
-
0 204 4
49
-
0 205 4
50
-
0 206 4
51
-
0 207 4
52
-
0 208 4
53
-
0 209 4
54
-
0 210 4
55
-
0 211 4
56
-
0 212 4
57
-
0 213 4
58
-
0 214 4
59
-
0 215 4
60
-
0 216 4
61
-
0 217 4
62
-
0 218 4
63
-
0 219 4>;
64
-
interrupt-names = "error",
65
-
"ch0", "ch1", "ch2", "ch3",
66
-
"ch4", "ch5", "ch6", "ch7",
67
-
"ch8", "ch9", "ch10", "ch11",
68
-
"ch12", "ch13", "ch14", "ch15",
69
-
"ch16", "ch17", "ch18", "ch19";
70
-
};
71
-
};
72
-
73
-
* DMA client
74
-
75
-
Required properties:
76
-
- dmas: a list of <[DMA multiplexer phandle] [MID/RID value]> pairs,
77
-
where MID/RID values are fixed handles, specified in the SoC
78
-
manual
79
-
- dma-names: a list of DMA channel names, one per "dmas" entry
80
-
81
-
Example:
82
-
dmas = <&dmac 0xd1
83
-
&dmac 0xd2>;
84
-
dma-names = "tx", "rx";
+8
MAINTAINERS
+8
MAINTAINERS
···
791
791
S: Maintained
792
792
F: drivers/mailbox/mailbox-altera.c
793
793
794
+
ALTERA MSGDMA IP CORE DRIVER
795
+
M: Olivier Dautricourt <olivier.dautricourt@orolia.com>
796
+
R: Stefan Roese <sr@denx.de>
797
+
L: dmaengine@vger.kernel.org
798
+
S: Odd Fixes
799
+
F: Documentation/devicetree/bindings/dma/altr,msgdma.yaml
800
+
F: drivers/dma/altera-msgdma.c
801
+
794
802
ALTERA PIO DRIVER
795
803
M: Joyce Ooi <joyce.ooi@intel.com>
796
804
L: linux-gpio@vger.kernel.org
+20
drivers/dma/altera-msgdma.c
+20
drivers/dma/altera-msgdma.c
···
19
19
#include <linux/module.h>
20
20
#include <linux/platform_device.h>
21
21
#include <linux/slab.h>
22
+
#include <linux/of_dma.h>
22
23
23
24
#include "dmaengine.h"
24
25
···
889
888
if (ret)
890
889
goto fail;
891
890
891
+
ret = of_dma_controller_register(pdev->dev.of_node,
892
+
of_dma_xlate_by_chan_id, dma_dev);
893
+
if (ret == -EINVAL)
894
+
dev_warn(&pdev->dev, "device was not probed from DT");
895
+
else if (ret && ret != -ENODEV)
896
+
goto fail;
897
+
892
898
dev_notice(&pdev->dev, "Altera mSGDMA driver probe success\n");
893
899
894
900
return 0;
···
916
908
{
917
909
struct msgdma_device *mdev = platform_get_drvdata(pdev);
918
910
911
+
if (pdev->dev.of_node)
912
+
of_dma_controller_free(pdev->dev.of_node);
919
913
dma_async_device_unregister(&mdev->dmadev);
920
914
msgdma_dev_remove(mdev);
921
915
···
926
916
return 0;
927
917
}
928
918
919
+
#ifdef CONFIG_OF
920
+
static const struct of_device_id msgdma_match[] = {
921
+
{ .compatible = "altr,socfpga-msgdma", },
922
+
{ }
923
+
};
924
+
925
+
MODULE_DEVICE_TABLE(of, msgdma_match);
926
+
#endif
927
+
929
928
static struct platform_driver msgdma_driver = {
930
929
.driver = {
931
930
.name = "altera-msgdma",
931
+
.of_match_table = of_match_ptr(msgdma_match),
932
932
},
933
933
.probe = msgdma_probe,
934
934
.remove = msgdma_remove,
+5
-1
drivers/dma/fsl-qdma.c
+5
-1
drivers/dma/fsl-qdma.c
···
1235
1235
fsl_qdma->dma_dev.device_synchronize = fsl_qdma_synchronize;
1236
1236
fsl_qdma->dma_dev.device_terminate_all = fsl_qdma_terminate_all;
1237
1237
1238
-
dma_set_mask(&pdev->dev, DMA_BIT_MASK(40));
1238
+
ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(40));
1239
+
if (ret) {
1240
+
dev_err(&pdev->dev, "dma_set_mask failure.\n");
1241
+
return ret;
1242
+
}
1239
1243
1240
1244
platform_set_drvdata(pdev, fsl_qdma);
1241
1245
+3
drivers/dma/hsu/hsu.c
+3
drivers/dma/hsu/hsu.c
···
201
201
*/
202
202
int hsu_dma_do_irq(struct hsu_dma_chip *chip, unsigned short nr, u32 status)
203
203
{
204
+
struct dma_chan_percpu *stat;
204
205
struct hsu_dma_chan *hsuc;
205
206
struct hsu_dma_desc *desc;
206
207
unsigned long flags;
···
211
210
return 0;
212
211
213
212
hsuc = &chip->hsu->chan[nr];
213
+
stat = this_cpu_ptr(hsuc->vchan.chan.local);
214
214
215
215
spin_lock_irqsave(&hsuc->vchan.lock, flags);
216
216
desc = hsuc->desc;
···
223
221
} else {
224
222
vchan_cookie_complete(&desc->vdesc);
225
223
desc->status = DMA_COMPLETE;
224
+
stat->bytes_transferred += desc->length;
226
225
hsu_dma_start_transfer(hsuc);
227
226
}
228
227
}
-2
drivers/dma/idxd/cdev.c
-2
drivers/dma/idxd/cdev.c
···
296
296
void idxd_wq_del_cdev(struct idxd_wq *wq)
297
297
{
298
298
struct idxd_cdev *idxd_cdev;
299
-
struct idxd_cdev_context *cdev_ctx;
300
299
301
-
cdev_ctx = &ictx[wq->idxd->data->type];
302
300
idxd_cdev = wq->idxd_cdev;
303
301
wq->idxd_cdev = NULL;
304
302
cdev_device_del(&idxd_cdev->cdev, &idxd_cdev->dev);
+2
-1
drivers/dma/idxd/init.c
+2
-1
drivers/dma/idxd/init.c
···
351
351
init_waitqueue_head(&idxd->cmd_waitq);
352
352
353
353
if (idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE)) {
354
-
idxd->int_handles = devm_kcalloc(dev, idxd->max_wqs, sizeof(int), GFP_KERNEL);
354
+
idxd->int_handles = kcalloc_node(idxd->max_wqs, sizeof(int), GFP_KERNEL,
355
+
dev_to_node(dev));
355
356
if (!idxd->int_handles)
356
357
return -ENOMEM;
357
358
}
+55
-1
drivers/dma/imx-sdma.c
+55
-1
drivers/dma/imx-sdma.c
···
35
35
#include <linux/workqueue.h>
36
36
37
37
#include <asm/irq.h>
38
-
#include <linux/platform_data/dma-imx-sdma.h>
39
38
#include <linux/platform_data/dma-imx.h>
40
39
#include <linux/regmap.h>
41
40
#include <linux/mfd/syscon.h>
···
179
180
#define SDMA_DMA_DIRECTIONS (BIT(DMA_DEV_TO_MEM) | \
180
181
BIT(DMA_MEM_TO_DEV) | \
181
182
BIT(DMA_DEV_TO_DEV))
183
+
184
+
/**
185
+
* struct sdma_script_start_addrs - SDMA script start pointers
186
+
*
187
+
* start addresses of the different functions in the physical
188
+
* address space of the SDMA engine.
189
+
*/
190
+
struct sdma_script_start_addrs {
191
+
s32 ap_2_ap_addr;
192
+
s32 ap_2_bp_addr;
193
+
s32 ap_2_ap_fixed_addr;
194
+
s32 bp_2_ap_addr;
195
+
s32 loopback_on_dsp_side_addr;
196
+
s32 mcu_interrupt_only_addr;
197
+
s32 firi_2_per_addr;
198
+
s32 firi_2_mcu_addr;
199
+
s32 per_2_firi_addr;
200
+
s32 mcu_2_firi_addr;
201
+
s32 uart_2_per_addr;
202
+
s32 uart_2_mcu_addr;
203
+
s32 per_2_app_addr;
204
+
s32 mcu_2_app_addr;
205
+
s32 per_2_per_addr;
206
+
s32 uartsh_2_per_addr;
207
+
s32 uartsh_2_mcu_addr;
208
+
s32 per_2_shp_addr;
209
+
s32 mcu_2_shp_addr;
210
+
s32 ata_2_mcu_addr;
211
+
s32 mcu_2_ata_addr;
212
+
s32 app_2_per_addr;
213
+
s32 app_2_mcu_addr;
214
+
s32 shp_2_per_addr;
215
+
s32 shp_2_mcu_addr;
216
+
s32 mshc_2_mcu_addr;
217
+
s32 mcu_2_mshc_addr;
218
+
s32 spdif_2_mcu_addr;
219
+
s32 mcu_2_spdif_addr;
220
+
s32 asrc_2_mcu_addr;
221
+
s32 ext_mem_2_ipu_addr;
222
+
s32 descrambler_addr;
223
+
s32 dptc_dvfs_addr;
224
+
s32 utra_addr;
225
+
s32 ram_code_start_addr;
226
+
/* End of v1 array */
227
+
s32 mcu_2_ssish_addr;
228
+
s32 ssish_2_mcu_addr;
229
+
s32 hdmi_dma_addr;
230
+
/* End of v2 array */
231
+
s32 zcanfd_2_mcu_addr;
232
+
s32 zqspi_2_mcu_addr;
233
+
s32 mcu_2_ecspi_addr;
234
+
/* End of v3 array */
235
+
s32 mcu_2_zqspi_addr;
236
+
/* End of v4 array */
237
+
};
182
238
183
239
/*
184
240
* Mode/Count of data node descriptors - IPCv2
+1
drivers/dma/qcom/gpi.c
+1
drivers/dma/qcom/gpi.c
+3
-2
drivers/dma/sf-pdma/sf-pdma.c
+3
-2
drivers/dma/sf-pdma/sf-pdma.c
···
94
94
{
95
95
struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan);
96
96
struct sf_pdma_desc *desc;
97
+
unsigned long iflags;
97
98
98
99
if (chan && (!len || !dest || !src)) {
99
100
dev_err(chan->pdma->dma_dev.dev,
···
110
109
desc->dirn = DMA_MEM_TO_MEM;
111
110
desc->async_tx = vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
112
111
113
-
spin_lock_irqsave(&chan->vchan.lock, flags);
112
+
spin_lock_irqsave(&chan->vchan.lock, iflags);
114
113
chan->desc = desc;
115
114
sf_pdma_fill_desc(desc, dest, src, len);
116
-
spin_unlock_irqrestore(&chan->vchan.lock, flags);
115
+
spin_unlock_irqrestore(&chan->vchan.lock, iflags);
117
116
118
117
return desc->async_tx;
119
118
}
+1
-1
drivers/dma/sh/Makefile
+1
-1
drivers/dma/sh/Makefile
-76
drivers/dma/sh/shdma-of.c
-76
drivers/dma/sh/shdma-of.c
···
1
-
// SPDX-License-Identifier: GPL-2.0
2
-
/*
3
-
* SHDMA Device Tree glue
4
-
*
5
-
* Copyright (C) 2013 Renesas Electronics Inc.
6
-
* Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
7
-
*/
8
-
9
-
#include <linux/dmaengine.h>
10
-
#include <linux/module.h>
11
-
#include <linux/of.h>
12
-
#include <linux/of_dma.h>
13
-
#include <linux/of_platform.h>
14
-
#include <linux/platform_device.h>
15
-
#include <linux/shdma-base.h>
16
-
17
-
#define to_shdma_chan(c) container_of(c, struct shdma_chan, dma_chan)
18
-
19
-
static struct dma_chan *shdma_of_xlate(struct of_phandle_args *dma_spec,
20
-
struct of_dma *ofdma)
21
-
{
22
-
u32 id = dma_spec->args[0];
23
-
dma_cap_mask_t mask;
24
-
struct dma_chan *chan;
25
-
26
-
if (dma_spec->args_count != 1)
27
-
return NULL;
28
-
29
-
dma_cap_zero(mask);
30
-
/* Only slave DMA channels can be allocated via DT */
31
-
dma_cap_set(DMA_SLAVE, mask);
32
-
33
-
chan = dma_request_channel(mask, shdma_chan_filter,
34
-
(void *)(uintptr_t)id);
35
-
if (chan)
36
-
to_shdma_chan(chan)->hw_req = id;
37
-
38
-
return chan;
39
-
}
40
-
41
-
static int shdma_of_probe(struct platform_device *pdev)
42
-
{
43
-
const struct of_dev_auxdata *lookup = dev_get_platdata(&pdev->dev);
44
-
int ret;
45
-
46
-
ret = of_dma_controller_register(pdev->dev.of_node,
47
-
shdma_of_xlate, pdev);
48
-
if (ret < 0)
49
-
return ret;
50
-
51
-
ret = of_platform_populate(pdev->dev.of_node, NULL, lookup, &pdev->dev);
52
-
if (ret < 0)
53
-
of_dma_controller_free(pdev->dev.of_node);
54
-
55
-
return ret;
56
-
}
57
-
58
-
static const struct of_device_id shdma_of_match[] = {
59
-
{ .compatible = "renesas,shdma-mux", },
60
-
{ }
61
-
};
62
-
MODULE_DEVICE_TABLE(of, sh_dmae_of_match);
63
-
64
-
static struct platform_driver shdma_of = {
65
-
.driver = {
66
-
.name = "shdma-of",
67
-
.of_match_table = shdma_of_match,
68
-
},
69
-
.probe = shdma_of_probe,
70
-
};
71
-
72
-
module_platform_driver(shdma_of);
73
-
74
-
MODULE_LICENSE("GPL v2");
75
-
MODULE_DESCRIPTION("SH-DMA driver DT glue");
76
-
MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
+2
-3
drivers/dma/sun4i-dma.c
+2
-3
drivers/dma/sun4i-dma.c
···
1042
1042
* Move the promise into the completed list now that
1043
1043
* we're done with it
1044
1044
*/
1045
-
list_del(&vchan->processing->list);
1046
-
list_add_tail(&vchan->processing->list,
1047
-
&contract->completed_demands);
1045
+
list_move_tail(&vchan->processing->list,
1046
+
&contract->completed_demands);
1048
1047
1049
1048
/*
1050
1049
* Cyclic DMA transfers are special:
+2
-1
drivers/dma/ti/omap-dma.c
+2
-1
drivers/dma/ti/omap-dma.c
···
1608
1608
return NOTIFY_BAD;
1609
1609
omap_dma_context_save(od);
1610
1610
break;
1611
-
case CPU_CLUSTER_PM_ENTER_FAILED:
1611
+
case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */
1612
+
break;
1612
1613
case CPU_CLUSTER_PM_EXIT:
1613
1614
omap_dma_context_restore(od);
1614
1615
break;
+28
-16
drivers/dma/xilinx/xilinx_dpdma.c
+28
-16
drivers/dma/xilinx/xilinx_dpdma.c
···
531
531
for (i = 1; i < num_src_addr; i++) {
532
532
u32 *addr = &hw_desc->src_addr2;
533
533
534
-
addr[i-1] = lower_32_bits(dma_addr[i]);
534
+
addr[i - 1] = lower_32_bits(dma_addr[i]);
535
535
536
536
if (xdev->ext_addr) {
537
537
u32 *addr_ext = &hw_desc->addr_ext_23;
···
703
703
size_t stride = hsize + xt->sgl[0].icg;
704
704
705
705
if (!IS_ALIGNED(xt->src_start, XILINX_DPDMA_ALIGN_BYTES)) {
706
-
dev_err(chan->xdev->dev, "buffer should be aligned at %d B\n",
707
-
XILINX_DPDMA_ALIGN_BYTES);
706
+
dev_err(chan->xdev->dev,
707
+
"chan%u: buffer should be aligned at %d B\n",
708
+
chan->id, XILINX_DPDMA_ALIGN_BYTES);
708
709
return NULL;
709
710
}
710
711
···
918
917
}
919
918
920
919
/**
921
-
* xilinx_dpdma_chan_no_ostand - Notify no outstanding transaction event
920
+
* xilinx_dpdma_chan_notify_no_ostand - Notify no outstanding transaction event
922
921
* @chan: DPDMA channel
923
922
*
924
923
* Notify waiters for no outstanding event, so waiters can stop the channel
···
937
936
938
937
cnt = xilinx_dpdma_chan_ostand(chan);
939
938
if (cnt) {
940
-
dev_dbg(chan->xdev->dev, "%d outstanding transactions\n", cnt);
939
+
dev_dbg(chan->xdev->dev,
940
+
"chan%u: %d outstanding transactions\n",
941
+
chan->id, cnt);
941
942
return -EWOULDBLOCK;
942
943
}
943
944
···
975
972
return 0;
976
973
}
977
974
978
-
dev_err(chan->xdev->dev, "not ready to stop: %d trans\n",
979
-
xilinx_dpdma_chan_ostand(chan));
975
+
dev_err(chan->xdev->dev, "chan%u: not ready to stop: %d trans\n",
976
+
chan->id, xilinx_dpdma_chan_ostand(chan));
980
977
981
978
if (ret == 0)
982
979
return -ETIMEDOUT;
···
1010
1007
return 0;
1011
1008
}
1012
1009
1013
-
dev_err(chan->xdev->dev, "not ready to stop: %d trans\n",
1014
-
xilinx_dpdma_chan_ostand(chan));
1010
+
dev_err(chan->xdev->dev, "chan%u: not ready to stop: %d trans\n",
1011
+
chan->id, xilinx_dpdma_chan_ostand(chan));
1015
1012
1016
1013
return -ETIMEDOUT;
1017
1014
}
···
1065
1062
vchan_cyclic_callback(&active->vdesc);
1066
1063
else
1067
1064
dev_warn(chan->xdev->dev,
1068
-
"DONE IRQ with no active descriptor!\n");
1065
+
"chan%u: DONE IRQ with no active descriptor!\n",
1066
+
chan->id);
1069
1067
1070
1068
spin_unlock_irqrestore(&chan->lock, flags);
1071
1069
}
···
1098
1094
/* If the retrigger raced with vsync, retry at the next frame. */
1099
1095
sw_desc = list_first_entry(&pending->descriptors,
1100
1096
struct xilinx_dpdma_sw_desc, node);
1101
-
if (sw_desc->hw.desc_id != desc_id)
1097
+
if (sw_desc->hw.desc_id != desc_id) {
1098
+
dev_dbg(chan->xdev->dev,
1099
+
"chan%u: vsync race lost (%u != %u), retrying\n",
1100
+
chan->id, sw_desc->hw.desc_id, desc_id);
1102
1101
goto out;
1102
+
}
1103
1103
1104
1104
/*
1105
1105
* Complete the active descriptor, if any, promote the pending
···
1159
1151
1160
1152
spin_lock_irqsave(&chan->lock, flags);
1161
1153
1162
-
dev_dbg(xdev->dev, "cur desc addr = 0x%04x%08x\n",
1154
+
dev_dbg(xdev->dev, "chan%u: cur desc addr = 0x%04x%08x\n",
1155
+
chan->id,
1163
1156
dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDRE),
1164
1157
dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDR));
1165
-
dev_dbg(xdev->dev, "cur payload addr = 0x%04x%08x\n",
1158
+
dev_dbg(xdev->dev, "chan%u: cur payload addr = 0x%04x%08x\n",
1159
+
chan->id,
1166
1160
dpdma_read(chan->reg, XILINX_DPDMA_CH_PYLD_CUR_ADDRE),
1167
1161
dpdma_read(chan->reg, XILINX_DPDMA_CH_PYLD_CUR_ADDR));
1168
1162
···
1180
1170
xilinx_dpdma_chan_dump_tx_desc(chan, active);
1181
1171
1182
1172
if (active->error)
1183
-
dev_dbg(xdev->dev, "repeated error on desc\n");
1173
+
dev_dbg(xdev->dev, "chan%u: repeated error on desc\n",
1174
+
chan->id);
1184
1175
1185
1176
/* Reschedule if there's no new descriptor */
1186
1177
if (!chan->desc.pending &&
···
1246
1235
align, 0);
1247
1236
if (!chan->desc_pool) {
1248
1237
dev_err(chan->xdev->dev,
1249
-
"failed to allocate a descriptor pool\n");
1238
+
"chan%u: failed to allocate a descriptor pool\n",
1239
+
chan->id);
1250
1240
return -ENOMEM;
1251
1241
}
1252
1242
···
1600
1588
struct of_dma *ofdma)
1601
1589
{
1602
1590
struct xilinx_dpdma_device *xdev = ofdma->of_dma_data;
1603
-
uint32_t chan_id = dma_spec->args[0];
1591
+
u32 chan_id = dma_spec->args[0];
1604
1592
1605
1593
if (chan_id >= ARRAY_SIZE(xdev->chan))
1606
1594
return NULL;
+5
-6
include/linux/dmaengine.h
+5
-6
include/linux/dmaengine.h
···
230
230
typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
231
231
232
232
/**
233
-
* struct dma_chan_percpu - the per-CPU part of struct dma_chan
234
-
* @memcpy_count: transaction counter
235
-
* @bytes_transferred: byte counter
236
-
*/
237
-
238
-
/**
239
233
* enum dma_desc_metadata_mode - per descriptor metadata mode types supported
240
234
* @DESC_METADATA_CLIENT - the metadata buffer is allocated/provided by the
241
235
* client driver and it is attached (via the dmaengine_desc_attach_metadata()
···
285
291
DESC_METADATA_ENGINE = BIT(1),
286
292
};
287
293
294
+
/**
295
+
* struct dma_chan_percpu - the per-CPU part of struct dma_chan
296
+
* @memcpy_count: transaction counter
297
+
* @bytes_transferred: byte counter
298
+
*/
288
299
struct dma_chan_percpu {
289
300
/* stats */
290
301
unsigned long memcpy_count;
-60
include/linux/platform_data/dma-imx-sdma.h
-60
include/linux/platform_data/dma-imx-sdma.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 */
2
-
#ifndef __MACH_MXC_SDMA_H__
3
-
#define __MACH_MXC_SDMA_H__
4
-
5
-
/**
6
-
* struct sdma_script_start_addrs - SDMA script start pointers
7
-
*
8
-
* start addresses of the different functions in the physical
9
-
* address space of the SDMA engine.
10
-
*/
11
-
struct sdma_script_start_addrs {
12
-
s32 ap_2_ap_addr;
13
-
s32 ap_2_bp_addr;
14
-
s32 ap_2_ap_fixed_addr;
15
-
s32 bp_2_ap_addr;
16
-
s32 loopback_on_dsp_side_addr;
17
-
s32 mcu_interrupt_only_addr;
18
-
s32 firi_2_per_addr;
19
-
s32 firi_2_mcu_addr;
20
-
s32 per_2_firi_addr;
21
-
s32 mcu_2_firi_addr;
22
-
s32 uart_2_per_addr;
23
-
s32 uart_2_mcu_addr;
24
-
s32 per_2_app_addr;
25
-
s32 mcu_2_app_addr;
26
-
s32 per_2_per_addr;
27
-
s32 uartsh_2_per_addr;
28
-
s32 uartsh_2_mcu_addr;
29
-
s32 per_2_shp_addr;
30
-
s32 mcu_2_shp_addr;
31
-
s32 ata_2_mcu_addr;
32
-
s32 mcu_2_ata_addr;
33
-
s32 app_2_per_addr;
34
-
s32 app_2_mcu_addr;
35
-
s32 shp_2_per_addr;
36
-
s32 shp_2_mcu_addr;
37
-
s32 mshc_2_mcu_addr;
38
-
s32 mcu_2_mshc_addr;
39
-
s32 spdif_2_mcu_addr;
40
-
s32 mcu_2_spdif_addr;
41
-
s32 asrc_2_mcu_addr;
42
-
s32 ext_mem_2_ipu_addr;
43
-
s32 descrambler_addr;
44
-
s32 dptc_dvfs_addr;
45
-
s32 utra_addr;
46
-
s32 ram_code_start_addr;
47
-
/* End of v1 array */
48
-
s32 mcu_2_ssish_addr;
49
-
s32 ssish_2_mcu_addr;
50
-
s32 hdmi_dma_addr;
51
-
/* End of v2 array */
52
-
s32 zcanfd_2_mcu_addr;
53
-
s32 zqspi_2_mcu_addr;
54
-
s32 mcu_2_ecspi_addr;
55
-
/* End of v3 array */
56
-
s32 mcu_2_zqspi_addr;
57
-
/* End of v4 array */
58
-
};
59
-
60
-
#endif /* __MACH_MXC_SDMA_H__ */