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RISC-V: KVM: Add support for Raw event v2

SBI v3.0 introduced a new raw event type v2 for wider mhpmeventX
programming. Add the support in kvm for that.

Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Acked-by: Paul Walmsley <pjw@kernel.org>
Link: https://lore.kernel.org/r/20250909-pmu_event_info-v6-3-d8f80cacb884@rivosinc.com
Signed-off-by: Anup Patel <anup@brainfault.org>

authored by

Atish Patra and committed by
Anup Patel 190b7415 656ef2ea

+4
+4
arch/riscv/kvm/vcpu_pmu.c
··· 60 60 type = PERF_TYPE_HW_CACHE; 61 61 break; 62 62 case SBI_PMU_EVENT_TYPE_RAW: 63 + case SBI_PMU_EVENT_TYPE_RAW_V2: 63 64 case SBI_PMU_EVENT_TYPE_FW: 64 65 type = PERF_TYPE_RAW; 65 66 break; ··· 128 127 break; 129 128 case SBI_PMU_EVENT_TYPE_RAW: 130 129 config = evt_data & RISCV_PMU_RAW_EVENT_MASK; 130 + break; 131 + case SBI_PMU_EVENT_TYPE_RAW_V2: 132 + config = evt_data & RISCV_PMU_RAW_EVENT_V2_MASK; 131 133 break; 132 134 case SBI_PMU_EVENT_TYPE_FW: 133 135 if (ecode < SBI_PMU_FW_MAX)