Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
soc: qcom: Add UBWC config provider
Add a file that will serve as a single source of truth for UBWC
configuration data for various multimedia blocks.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/660959/
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
authored by
Konrad Dybcio
and committed by
Rob Clark
1924272b
6733d827
+325
+8
drivers/soc/qcom/Kconfig
+8
drivers/soc/qcom/Kconfig
···
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PBS trigger event to the PBS RAM.
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endmenu
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config QCOM_UBWC_CONFIG
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tristate
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help
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Most Qualcomm SoCs feature a number of Universal Bandwidth Compression
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(UBWC) engines across various IP blocks, which need to be initialized
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with coherent configuration data. This module functions as a single
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source of truth for that information.
+1
drivers/soc/qcom/Makefile
+1
drivers/soc/qcom/Makefile
+251
drivers/soc/qcom/ubwc_config.c
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drivers/soc/qcom/ubwc_config.c
···
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#include <linux/debugfs.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/soc/qcom/ubwc.h>
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static const struct qcom_ubwc_cfg_data msm8937_data = {
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.ubwc_enc_version = UBWC_1_0,
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.ubwc_dec_version = UBWC_1_0,
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.highest_bank_bit = 14,
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};
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static const struct qcom_ubwc_cfg_data msm8998_data = {
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.ubwc_enc_version = UBWC_1_0,
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.ubwc_dec_version = UBWC_1_0,
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.highest_bank_bit = 15,
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};
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static const struct qcom_ubwc_cfg_data qcm2290_data = {
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/* no UBWC */
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.highest_bank_bit = 15,
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};
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static const struct qcom_ubwc_cfg_data sa8775p_data = {
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.ubwc_enc_version = UBWC_4_0,
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.ubwc_dec_version = UBWC_4_0,
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.ubwc_swizzle = 4,
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.ubwc_bank_spread = true,
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.highest_bank_bit = 13,
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.macrotile_mode = true,
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};
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static const struct qcom_ubwc_cfg_data sar2130p_data = {
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.ubwc_enc_version = UBWC_3_0, /* 4.0.2 in hw */
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.ubwc_dec_version = UBWC_4_3,
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.ubwc_swizzle = 6,
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.ubwc_bank_spread = true,
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.highest_bank_bit = 13,
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.macrotile_mode = true,
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};
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static const struct qcom_ubwc_cfg_data sc7180_data = {
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.ubwc_enc_version = UBWC_2_0,
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.ubwc_dec_version = UBWC_2_0,
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.ubwc_swizzle = 6,
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.ubwc_bank_spread = true,
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.highest_bank_bit = 14,
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};
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static const struct qcom_ubwc_cfg_data sc7280_data = {
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.ubwc_enc_version = UBWC_3_0,
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.ubwc_dec_version = UBWC_4_0,
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.ubwc_swizzle = 6,
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.ubwc_bank_spread = true,
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.highest_bank_bit = 14,
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.macrotile_mode = true,
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};
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static const struct qcom_ubwc_cfg_data sc8180x_data = {
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.ubwc_enc_version = UBWC_3_0,
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.ubwc_dec_version = UBWC_3_0,
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.highest_bank_bit = 16,
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.macrotile_mode = true,
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};
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static const struct qcom_ubwc_cfg_data sc8280xp_data = {
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.ubwc_enc_version = UBWC_4_0,
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.ubwc_dec_version = UBWC_4_0,
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.ubwc_swizzle = 6,
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.ubwc_bank_spread = true,
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.highest_bank_bit = 16,
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.macrotile_mode = true,
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};
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static const struct qcom_ubwc_cfg_data sdm670_data = {
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.ubwc_enc_version = UBWC_2_0,
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.ubwc_dec_version = UBWC_2_0,
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.highest_bank_bit = 14,
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};
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static const struct qcom_ubwc_cfg_data sdm845_data = {
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.ubwc_enc_version = UBWC_2_0,
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.ubwc_dec_version = UBWC_2_0,
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.highest_bank_bit = 15,
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};
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static const struct qcom_ubwc_cfg_data sm6115_data = {
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.ubwc_enc_version = UBWC_1_0,
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.ubwc_dec_version = UBWC_2_0,
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.ubwc_swizzle = 7,
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.ubwc_bank_spread = true,
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.highest_bank_bit = 14,
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};
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static const struct qcom_ubwc_cfg_data sm6125_data = {
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.ubwc_enc_version = UBWC_1_0,
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.ubwc_dec_version = UBWC_3_0,
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.ubwc_swizzle = 1,
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.highest_bank_bit = 14,
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};
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static const struct qcom_ubwc_cfg_data sm6150_data = {
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.ubwc_enc_version = UBWC_2_0,
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.ubwc_dec_version = UBWC_2_0,
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.highest_bank_bit = 14,
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};
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static const struct qcom_ubwc_cfg_data sm6350_data = {
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.ubwc_enc_version = UBWC_2_0,
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.ubwc_dec_version = UBWC_2_0,
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.ubwc_swizzle = 6,
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.ubwc_bank_spread = true,
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.highest_bank_bit = 14,
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};
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static const struct qcom_ubwc_cfg_data sm7150_data = {
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.ubwc_enc_version = UBWC_2_0,
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.ubwc_dec_version = UBWC_2_0,
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.highest_bank_bit = 14,
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};
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static const struct qcom_ubwc_cfg_data sm8150_data = {
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.ubwc_enc_version = UBWC_3_0,
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.ubwc_dec_version = UBWC_3_0,
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.highest_bank_bit = 15,
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};
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static const struct qcom_ubwc_cfg_data sm8250_data = {
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.ubwc_enc_version = UBWC_4_0,
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.ubwc_dec_version = UBWC_4_0,
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.ubwc_swizzle = 6,
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.ubwc_bank_spread = true,
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/* TODO: highest_bank_bit = 15 for LP_DDR4 */
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.highest_bank_bit = 16,
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.macrotile_mode = true,
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};
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static const struct qcom_ubwc_cfg_data sm8350_data = {
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.ubwc_enc_version = UBWC_4_0,
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.ubwc_dec_version = UBWC_4_0,
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.ubwc_swizzle = 6,
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.ubwc_bank_spread = true,
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/* TODO: highest_bank_bit = 15 for LP_DDR4 */
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.highest_bank_bit = 16,
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.macrotile_mode = true,
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};
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static const struct qcom_ubwc_cfg_data sm8550_data = {
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.ubwc_enc_version = UBWC_4_0,
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.ubwc_dec_version = UBWC_4_3,
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.ubwc_swizzle = 6,
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.ubwc_bank_spread = true,
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/* TODO: highest_bank_bit = 15 for LP_DDR4 */
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.highest_bank_bit = 16,
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.macrotile_mode = true,
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};
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static const struct qcom_ubwc_cfg_data sm8750_data = {
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.ubwc_enc_version = UBWC_5_0,
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.ubwc_dec_version = UBWC_5_0,
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.ubwc_swizzle = 6,
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.ubwc_bank_spread = true,
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/* TODO: highest_bank_bit = 15 for LP_DDR4 */
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.highest_bank_bit = 16,
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.macrotile_mode = true,
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};
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static const struct qcom_ubwc_cfg_data x1e80100_data = {
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.ubwc_enc_version = UBWC_4_0,
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.ubwc_dec_version = UBWC_4_3,
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.ubwc_swizzle = 6,
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.ubwc_bank_spread = true,
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/* TODO: highest_bank_bit = 15 for LP_DDR4 */
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.highest_bank_bit = 16,
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.macrotile_mode = true,
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};
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static const struct of_device_id qcom_ubwc_configs[] __maybe_unused = {
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{ .compatible = "qcom,apq8096", .data = &msm8998_data },
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{ .compatible = "qcom,msm8917", .data = &msm8937_data },
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{ .compatible = "qcom,msm8937", .data = &msm8937_data },
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{ .compatible = "qcom,msm8953", .data = &msm8937_data },
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{ .compatible = "qcom,msm8956", .data = &msm8937_data },
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{ .compatible = "qcom,msm8976", .data = &msm8937_data },
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{ .compatible = "qcom,msm8996", .data = &msm8998_data },
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{ .compatible = "qcom,msm8998", .data = &msm8998_data },
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{ .compatible = "qcom,qcm2290", .data = &qcm2290_data, },
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{ .compatible = "qcom,qcm6490", .data = &sc7280_data, },
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{ .compatible = "qcom,sa8155p", .data = &sm8150_data, },
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{ .compatible = "qcom,sa8540p", .data = &sc8280xp_data, },
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{ .compatible = "qcom,sa8775p", .data = &sa8775p_data, },
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{ .compatible = "qcom,sar2130p", .data = &sar2130p_data },
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{ .compatible = "qcom,sc7180", .data = &sc7180_data },
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{ .compatible = "qcom,sc7280", .data = &sc7280_data, },
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{ .compatible = "qcom,sc8180x", .data = &sc8180x_data, },
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{ .compatible = "qcom,sc8280xp", .data = &sc8280xp_data, },
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{ .compatible = "qcom,sdm630", .data = &msm8937_data },
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{ .compatible = "qcom,sdm636", .data = &msm8937_data },
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{ .compatible = "qcom,sdm660", .data = &msm8937_data },
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{ .compatible = "qcom,sdm670", .data = &sdm670_data, },
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{ .compatible = "qcom,sdm845", .data = &sdm845_data, },
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{ .compatible = "qcom,sm4250", .data = &sm6115_data, },
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{ .compatible = "qcom,sm6115", .data = &sm6115_data, },
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{ .compatible = "qcom,sm6125", .data = &sm6125_data, },
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{ .compatible = "qcom,sm6150", .data = &sm6150_data, },
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{ .compatible = "qcom,sm6350", .data = &sm6350_data, },
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{ .compatible = "qcom,sm6375", .data = &sm6350_data, },
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{ .compatible = "qcom,sm7125", .data = &sc7180_data },
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{ .compatible = "qcom,sm7150", .data = &sm7150_data, },
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{ .compatible = "qcom,sm8150", .data = &sm8150_data, },
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{ .compatible = "qcom,sm8250", .data = &sm8250_data, },
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{ .compatible = "qcom,sm8350", .data = &sm8350_data, },
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{ .compatible = "qcom,sm8450", .data = &sm8350_data, },
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{ .compatible = "qcom,sm8550", .data = &sm8550_data, },
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{ .compatible = "qcom,sm8650", .data = &sm8550_data, },
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{ .compatible = "qcom,sm8750", .data = &sm8750_data, },
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{ .compatible = "qcom,x1e80100", .data = &x1e80100_data, },
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{ .compatible = "qcom,x1p42100", .data = &x1e80100_data, },
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{ }
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};
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const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void)
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{
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const struct of_device_id *match;
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struct device_node *root;
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root = of_find_node_by_path("/");
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if (!root)
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return ERR_PTR(-ENODEV);
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match = of_match_node(qcom_ubwc_configs, root);
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of_node_put(root);
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if (!match) {
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pr_err("Couldn't find UBWC config data for this platform!\n");
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return ERR_PTR(-EINVAL);
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}
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return match->data;
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}
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EXPORT_SYMBOL_GPL(qcom_ubwc_config_get_data);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("UBWC config database for QTI SoCs");
+65
include/linux/soc/qcom/ubwc.h
+65
include/linux/soc/qcom/ubwc.h
···
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2018, The Linux Foundation
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#ifndef __QCOM_UBWC_H__
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#define __QCOM_UBWC_H__
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#include <linux/bits.h>
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#include <linux/types.h>
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struct qcom_ubwc_cfg_data {
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u32 ubwc_enc_version;
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/* Can be read from MDSS_BASE + 0x58 */
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u32 ubwc_dec_version;
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/**
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* @ubwc_swizzle: Whether to enable level 1, 2 & 3 bank swizzling.
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*
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* UBWC 1.0 always enables all three levels.
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* UBWC 2.0 removes level 1 bank swizzling, leaving levels 2 & 3.
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* UBWC 4.0 adds the optional ability to disable levels 2 & 3.
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*
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* This is a bitmask where BIT(0) enables level 1, BIT(1)
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* controls level 2, and BIT(2) enables level 3.
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*/
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u32 ubwc_swizzle;
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/**
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* @highest_bank_bit: Highest Bank Bit
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*
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* The Highest Bank Bit value represents the bit of the highest
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* DDR bank. This should ideally use DRAM type detection.
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*/
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int highest_bank_bit;
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bool ubwc_bank_spread;
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/**
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* @macrotile_mode: Macrotile Mode
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*
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* Whether to use 4-channel macrotiling mode or the newer
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* 8-channel macrotiling mode introduced in UBWC 3.1. 0 is
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* 4-channel and 1 is 8-channel.
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*/
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bool macrotile_mode;
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};
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#define UBWC_1_0 0x10000000
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#define UBWC_2_0 0x20000000
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#define UBWC_3_0 0x30000000
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#define UBWC_4_0 0x40000000
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#define UBWC_4_3 0x40030000
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#define UBWC_5_0 0x50000000
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#ifdef CONFIG_QCOM_UBWC_CONFIG
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const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void);
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#else
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static inline const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void)
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{
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return ERR_PTR(-EOPNOTSUPP);
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}
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#endif
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#endif /* __QCOM_UBWC_H__ */