Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: freescale: fsl-samsung-hdmi: Support dynamic integer
There is currently a look-up table for a variety of resolutions.
Since the phy has the ability to dynamically calculate the values
necessary to use the intger divider which should allow more
resolutions without having to update the look-up-table.
If the lookup table cannot find an exact match, fall back to the
dynamic calculator of the integer divider.
Previously, the value of P was hard-coded to 1, this required an
update to the phy_pll_cfg table to add in the extra value into the
table, so if the value of P is calculated to be something else
by the PMS calculator, the calculated_phy_pll_cfg structure
can be used instead without having to keep track of which method
was used.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Dominique Martinet <dominique.martinet@atmark-techno.com>
Tested-by: Dominique Martinet <dominique.martinet@atmark-techno.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Link: https://lore.kernel.org/r/20240914112816.520224-4-aford173@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Adam Ford
and committed by
Vinod Koul
1951dbb4
375ee44a
+270
-107
+270
-107
drivers/phy/freescale/phy-fsl-samsung-hdmi.c
+270
-107
drivers/phy/freescale/phy-fsl-samsung-hdmi.c
···
16
16
17
17
#define PHY_REG(reg) (reg * 4)
18
18
19
+
#define REG01_PMS_P_MASK GENMASK(3, 0)
20
+
#define REG03_PMS_S_MASK GENMASK(7, 4)
19
21
#define REG12_CK_DIV_MASK GENMASK(5, 4)
20
22
21
23
#define REG13_TG_CODE_LOW_MASK GENMASK(7, 0)
···
40
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#define REG34_PLL_LOCK BIT(6)
41
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#define REG34_PHY_CLK_READY BIT(5)
42
40
43
-
#define PHY_PLL_DIV_REGS_NUM 6
41
+
#ifndef MHZ
42
+
#define MHZ (1000UL * 1000UL)
43
+
#endif
44
+
45
+
#define PHY_PLL_DIV_REGS_NUM 7
44
46
45
47
struct phy_config {
46
48
u32 pixclk;
47
49
u8 pll_div_regs[PHY_PLL_DIV_REGS_NUM];
48
50
};
49
51
52
+
/*
53
+
* The calculated_phy_pll_cfg only handles integer divider for PMS,
54
+
* meaning the last four entries will be fixed, but the first three will
55
+
* be calculated by the PMS calculator.
56
+
*/
57
+
static struct phy_config calculated_phy_pll_cfg = {
58
+
.pixclk = 0,
59
+
.pll_div_regs = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00 },
60
+
};
61
+
62
+
/* The lookup table contains values for which the fractional divder is used */
50
63
static const struct phy_config phy_pll_cfg[] = {
51
64
{
52
65
.pixclk = 22250000,
53
-
.pll_div_regs = { 0x4b, 0xf1, 0x89, 0x88, 0x80, 0x40 },
66
+
.pll_div_regs = { 0xd1, 0x4b, 0xf1, 0x89, 0x88, 0x80, 0x40 },
54
67
}, {
55
68
.pixclk = 23750000,
56
-
.pll_div_regs = { 0x50, 0xf1, 0x86, 0x85, 0x80, 0x40 },
69
+
.pll_div_regs = { 0xd1, 0x50, 0xf1, 0x86, 0x85, 0x80, 0x40 },
57
70
}, {
58
71
.pixclk = 24000000,
59
-
.pll_div_regs = { 0x50, 0xf0, 0x00, 0x00, 0x80, 0x00 },
72
+
.pll_div_regs = { 0xd1, 0x50, 0xf0, 0x00, 0x00, 0x80, 0x00 },
60
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}, {
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.pixclk = 24024000,
62
-
.pll_div_regs = { 0x50, 0xf1, 0x99, 0x02, 0x80, 0x40 },
75
+
.pll_div_regs = { 0xd1, 0x50, 0xf1, 0x99, 0x02, 0x80, 0x40 },
63
76
}, {
64
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.pixclk = 25175000,
65
-
.pll_div_regs = { 0x54, 0xfc, 0xcc, 0x91, 0x80, 0x40 },
78
+
.pll_div_regs = { 0xd1, 0x54, 0xfc, 0xcc, 0x91, 0x80, 0x40 },
66
79
}, {
67
80
.pixclk = 25200000,
68
-
.pll_div_regs = { 0x54, 0xf0, 0x00, 0x00, 0x80, 0x00 },
81
+
.pll_div_regs = { 0xd1, 0x54, 0xf0, 0x00, 0x00, 0x80, 0x00 },
69
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}, {
70
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.pixclk = 26750000,
71
-
.pll_div_regs = { 0x5a, 0xf2, 0x89, 0x88, 0x80, 0x40 },
84
+
.pll_div_regs = { 0xd1, 0x5a, 0xf2, 0x89, 0x88, 0x80, 0x40 },
72
85
}, {
73
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.pixclk = 27000000,
74
-
.pll_div_regs = { 0x5a, 0xf0, 0x00, 0x00, 0x80, 0x00 },
87
+
.pll_div_regs = { 0xd1, 0x5a, 0xf0, 0x00, 0x00, 0x80, 0x00 },
75
88
}, {
76
89
.pixclk = 27027000,
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-
.pll_div_regs = { 0x5a, 0xf2, 0xfd, 0x0c, 0x80, 0x40 },
90
+
.pll_div_regs = { 0xd1, 0x5a, 0xf2, 0xfd, 0x0c, 0x80, 0x40 },
78
91
}, {
79
92
.pixclk = 29500000,
80
-
.pll_div_regs = { 0x62, 0xf4, 0x95, 0x08, 0x80, 0x40 },
93
+
.pll_div_regs = { 0xd1, 0x62, 0xf4, 0x95, 0x08, 0x80, 0x40 },
81
94
}, {
82
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.pixclk = 30750000,
83
-
.pll_div_regs = { 0x66, 0xf4, 0x82, 0x01, 0x88, 0x45 },
96
+
.pll_div_regs = { 0xd1, 0x66, 0xf4, 0x82, 0x01, 0x88, 0x45 },
84
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}, {
85
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.pixclk = 30888000,
86
-
.pll_div_regs = { 0x66, 0xf4, 0x99, 0x18, 0x88, 0x45 },
99
+
.pll_div_regs = { 0xd1, 0x66, 0xf4, 0x99, 0x18, 0x88, 0x45 },
87
100
}, {
88
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.pixclk = 33750000,
89
-
.pll_div_regs = { 0x70, 0xf4, 0x82, 0x01, 0x80, 0x40 },
102
+
.pll_div_regs = { 0xd1, 0x70, 0xf4, 0x82, 0x01, 0x80, 0x40 },
90
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}, {
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.pixclk = 35000000,
92
-
.pll_div_regs = { 0x58, 0xb8, 0x8b, 0x88, 0x80, 0x40 },
105
+
.pll_div_regs = { 0xd1, 0x58, 0xb8, 0x8b, 0x88, 0x80, 0x40 },
93
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}, {
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.pixclk = 36000000,
95
-
.pll_div_regs = { 0x5a, 0xb0, 0x00, 0x00, 0x80, 0x00 },
108
+
.pll_div_regs = { 0xd1, 0x5a, 0xb0, 0x00, 0x00, 0x80, 0x00 },
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}, {
97
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.pixclk = 36036000,
98
-
.pll_div_regs = { 0x5a, 0xb2, 0xfd, 0x0c, 0x80, 0x40 },
111
+
.pll_div_regs = { 0xd1, 0x5a, 0xb2, 0xfd, 0x0c, 0x80, 0x40 },
99
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}, {
100
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.pixclk = 40000000,
101
-
.pll_div_regs = { 0x64, 0xb0, 0x00, 0x00, 0x80, 0x00 },
114
+
.pll_div_regs = { 0xd1, 0x64, 0xb0, 0x00, 0x00, 0x80, 0x00 },
102
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}, {
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.pixclk = 43200000,
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-
.pll_div_regs = { 0x5a, 0x90, 0x00, 0x00, 0x80, 0x00 },
117
+
.pll_div_regs = { 0xd1, 0x5a, 0x90, 0x00, 0x00, 0x80, 0x00 },
105
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}, {
106
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.pixclk = 43243200,
107
-
.pll_div_regs = { 0x5a, 0x92, 0xfd, 0x0c, 0x80, 0x40 },
120
+
.pll_div_regs = { 0xd1, 0x5a, 0x92, 0xfd, 0x0c, 0x80, 0x40 },
108
121
}, {
109
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.pixclk = 44500000,
110
-
.pll_div_regs = { 0x5c, 0x92, 0x98, 0x11, 0x84, 0x41 },
123
+
.pll_div_regs = { 0xd1, 0x5c, 0x92, 0x98, 0x11, 0x84, 0x41 },
111
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}, {
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.pixclk = 47000000,
113
-
.pll_div_regs = { 0x62, 0x94, 0x95, 0x82, 0x80, 0x40 },
126
+
.pll_div_regs = { 0xd1, 0x62, 0x94, 0x95, 0x82, 0x80, 0x40 },
114
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}, {
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.pixclk = 47500000,
116
-
.pll_div_regs = { 0x63, 0x96, 0xa1, 0x82, 0x80, 0x40 },
129
+
.pll_div_regs = { 0xd1, 0x63, 0x96, 0xa1, 0x82, 0x80, 0x40 },
117
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}, {
118
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.pixclk = 50349650,
119
-
.pll_div_regs = { 0x54, 0x7c, 0xc3, 0x8f, 0x80, 0x40 },
132
+
.pll_div_regs = { 0xd1, 0x54, 0x7c, 0xc3, 0x8f, 0x80, 0x40 },
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}, {
121
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.pixclk = 50400000,
122
-
.pll_div_regs = { 0x54, 0x70, 0x00, 0x00, 0x80, 0x00 },
135
+
.pll_div_regs = { 0xd1, 0x54, 0x70, 0x00, 0x00, 0x80, 0x00 },
123
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}, {
124
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.pixclk = 53250000,
125
-
.pll_div_regs = { 0x58, 0x72, 0x84, 0x03, 0x82, 0x41 },
138
+
.pll_div_regs = { 0xd1, 0x58, 0x72, 0x84, 0x03, 0x82, 0x41 },
126
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}, {
127
140
.pixclk = 53500000,
128
-
.pll_div_regs = { 0x5a, 0x72, 0x89, 0x88, 0x80, 0x40 },
141
+
.pll_div_regs = { 0xd1, 0x5a, 0x72, 0x89, 0x88, 0x80, 0x40 },
129
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}, {
130
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.pixclk = 54000000,
131
-
.pll_div_regs = { 0x5a, 0x70, 0x00, 0x00, 0x80, 0x00 },
144
+
.pll_div_regs = { 0xd1, 0x5a, 0x70, 0x00, 0x00, 0x80, 0x00 },
132
145
}, {
133
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.pixclk = 54054000,
134
-
.pll_div_regs = { 0x5a, 0x72, 0xfd, 0x0c, 0x80, 0x40 },
147
+
.pll_div_regs = { 0xd1, 0x5a, 0x72, 0xfd, 0x0c, 0x80, 0x40 },
135
148
}, {
136
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.pixclk = 59000000,
137
-
.pll_div_regs = { 0x62, 0x74, 0x95, 0x08, 0x80, 0x40 },
150
+
.pll_div_regs = { 0xd1, 0x62, 0x74, 0x95, 0x08, 0x80, 0x40 },
138
151
}, {
139
152
.pixclk = 59340659,
140
-
.pll_div_regs = { 0x62, 0x74, 0xdb, 0x52, 0x88, 0x47 },
153
+
.pll_div_regs = { 0xd1, 0x62, 0x74, 0xdb, 0x52, 0x88, 0x47 },
141
154
}, {
142
155
.pixclk = 59400000,
143
-
.pll_div_regs = { 0x63, 0x70, 0x00, 0x00, 0x80, 0x00 },
156
+
.pll_div_regs = { 0xd1, 0x63, 0x70, 0x00, 0x00, 0x80, 0x00 },
144
157
}, {
145
158
.pixclk = 61500000,
146
-
.pll_div_regs = { 0x66, 0x74, 0x82, 0x01, 0x88, 0x45 },
159
+
.pll_div_regs = { 0xd1, 0x66, 0x74, 0x82, 0x01, 0x88, 0x45 },
147
160
}, {
148
161
.pixclk = 63500000,
149
-
.pll_div_regs = { 0x69, 0x74, 0x89, 0x08, 0x80, 0x40 },
162
+
.pll_div_regs = { 0xd1, 0x69, 0x74, 0x89, 0x08, 0x80, 0x40 },
150
163
}, {
151
164
.pixclk = 67500000,
152
-
.pll_div_regs = { 0x54, 0x52, 0x87, 0x03, 0x80, 0x40 },
165
+
.pll_div_regs = { 0xd1, 0x54, 0x52, 0x87, 0x03, 0x80, 0x40 },
153
166
}, {
154
167
.pixclk = 70000000,
155
-
.pll_div_regs = { 0x58, 0x58, 0x8b, 0x88, 0x80, 0x40 },
168
+
.pll_div_regs = { 0xd1, 0x58, 0x58, 0x8b, 0x88, 0x80, 0x40 },
156
169
}, {
157
170
.pixclk = 72000000,
158
-
.pll_div_regs = { 0x5a, 0x50, 0x00, 0x00, 0x80, 0x00 },
171
+
.pll_div_regs = { 0xd1, 0x5a, 0x50, 0x00, 0x00, 0x80, 0x00 },
159
172
}, {
160
173
.pixclk = 72072000,
161
-
.pll_div_regs = { 0x5a, 0x52, 0xfd, 0x0c, 0x80, 0x40 },
174
+
.pll_div_regs = { 0xd1, 0x5a, 0x52, 0xfd, 0x0c, 0x80, 0x40 },
162
175
}, {
163
176
.pixclk = 74176000,
164
-
.pll_div_regs = { 0x5d, 0x58, 0xdb, 0xA2, 0x88, 0x41 },
177
+
.pll_div_regs = { 0xd1, 0x5d, 0x58, 0xdb, 0xA2, 0x88, 0x41 },
165
178
}, {
166
179
.pixclk = 74250000,
167
-
.pll_div_regs = { 0x5c, 0x52, 0x90, 0x0d, 0x84, 0x41 },
180
+
.pll_div_regs = { 0xd1, 0x5c, 0x52, 0x90, 0x0d, 0x84, 0x41 },
168
181
}, {
169
182
.pixclk = 78500000,
170
-
.pll_div_regs = { 0x62, 0x54, 0x87, 0x01, 0x80, 0x40 },
183
+
.pll_div_regs = { 0xd1, 0x62, 0x54, 0x87, 0x01, 0x80, 0x40 },
171
184
}, {
172
185
.pixclk = 80000000,
173
-
.pll_div_regs = { 0x64, 0x50, 0x00, 0x00, 0x80, 0x00 },
186
+
.pll_div_regs = { 0xd1, 0x64, 0x50, 0x00, 0x00, 0x80, 0x00 },
174
187
}, {
175
188
.pixclk = 82000000,
176
-
.pll_div_regs = { 0x66, 0x54, 0x82, 0x01, 0x88, 0x45 },
189
+
.pll_div_regs = { 0xd1, 0x66, 0x54, 0x82, 0x01, 0x88, 0x45 },
177
190
}, {
178
191
.pixclk = 82500000,
179
-
.pll_div_regs = { 0x67, 0x54, 0x88, 0x01, 0x90, 0x49 },
192
+
.pll_div_regs = { 0xd1, 0x67, 0x54, 0x88, 0x01, 0x90, 0x49 },
180
193
}, {
181
194
.pixclk = 89000000,
182
-
.pll_div_regs = { 0x70, 0x54, 0x84, 0x83, 0x80, 0x40 },
195
+
.pll_div_regs = { 0xd1, 0x70, 0x54, 0x84, 0x83, 0x80, 0x40 },
183
196
}, {
184
197
.pixclk = 90000000,
185
-
.pll_div_regs = { 0x70, 0x54, 0x82, 0x01, 0x80, 0x40 },
198
+
.pll_div_regs = { 0xd1, 0x70, 0x54, 0x82, 0x01, 0x80, 0x40 },
186
199
}, {
187
200
.pixclk = 94000000,
188
-
.pll_div_regs = { 0x4e, 0x32, 0xa7, 0x10, 0x80, 0x40 },
201
+
.pll_div_regs = { 0xd1, 0x4e, 0x32, 0xa7, 0x10, 0x80, 0x40 },
189
202
}, {
190
203
.pixclk = 95000000,
191
-
.pll_div_regs = { 0x50, 0x31, 0x86, 0x85, 0x80, 0x40 },
204
+
.pll_div_regs = { 0xd1, 0x50, 0x31, 0x86, 0x85, 0x80, 0x40 },
192
205
}, {
193
206
.pixclk = 98901099,
194
-
.pll_div_regs = { 0x52, 0x3a, 0xdb, 0x4c, 0x88, 0x47 },
207
+
.pll_div_regs = { 0xd1, 0x52, 0x3a, 0xdb, 0x4c, 0x88, 0x47 },
195
208
}, {
196
209
.pixclk = 99000000,
197
-
.pll_div_regs = { 0x52, 0x32, 0x82, 0x01, 0x88, 0x47 },
210
+
.pll_div_regs = { 0xd1, 0x52, 0x32, 0x82, 0x01, 0x88, 0x47 },
198
211
}, {
199
212
.pixclk = 100699300,
200
-
.pll_div_regs = { 0x54, 0x3c, 0xc3, 0x8f, 0x80, 0x40 },
213
+
.pll_div_regs = { 0xd1, 0x54, 0x3c, 0xc3, 0x8f, 0x80, 0x40 },
201
214
}, {
202
215
.pixclk = 100800000,
203
-
.pll_div_regs = { 0x54, 0x30, 0x00, 0x00, 0x80, 0x00 },
216
+
.pll_div_regs = { 0xd1, 0x54, 0x30, 0x00, 0x00, 0x80, 0x00 },
204
217
}, {
205
218
.pixclk = 102500000,
206
-
.pll_div_regs = { 0x55, 0x32, 0x8c, 0x05, 0x90, 0x4b },
219
+
.pll_div_regs = { 0xd1, 0x55, 0x32, 0x8c, 0x05, 0x90, 0x4b },
207
220
}, {
208
221
.pixclk = 104750000,
209
-
.pll_div_regs = { 0x57, 0x32, 0x98, 0x07, 0x90, 0x49 },
222
+
.pll_div_regs = { 0xd1, 0x57, 0x32, 0x98, 0x07, 0x90, 0x49 },
210
223
}, {
211
224
.pixclk = 106500000,
212
-
.pll_div_regs = { 0x58, 0x32, 0x84, 0x03, 0x82, 0x41 },
225
+
.pll_div_regs = { 0xd1, 0x58, 0x32, 0x84, 0x03, 0x82, 0x41 },
213
226
}, {
214
227
.pixclk = 107000000,
215
-
.pll_div_regs = { 0x5a, 0x32, 0x89, 0x88, 0x80, 0x40 },
228
+
.pll_div_regs = { 0xd1, 0x5a, 0x32, 0x89, 0x88, 0x80, 0x40 },
216
229
}, {
217
230
.pixclk = 108000000,
218
-
.pll_div_regs = { 0x5a, 0x30, 0x00, 0x00, 0x80, 0x00 },
231
+
.pll_div_regs = { 0xd1, 0x5a, 0x30, 0x00, 0x00, 0x80, 0x00 },
219
232
}, {
220
233
.pixclk = 108108000,
221
-
.pll_div_regs = { 0x5a, 0x32, 0xfd, 0x0c, 0x80, 0x40 },
234
+
.pll_div_regs = { 0xd1, 0x5a, 0x32, 0xfd, 0x0c, 0x80, 0x40 },
222
235
}, {
223
236
.pixclk = 118000000,
224
-
.pll_div_regs = { 0x62, 0x34, 0x95, 0x08, 0x80, 0x40 },
237
+
.pll_div_regs = { 0xd1, 0x62, 0x34, 0x95, 0x08, 0x80, 0x40 },
225
238
}, {
226
239
.pixclk = 118800000,
227
-
.pll_div_regs = { 0x63, 0x30, 0x00, 0x00, 0x80, 0x00 },
240
+
.pll_div_regs = { 0xd1, 0x63, 0x30, 0x00, 0x00, 0x80, 0x00 },
228
241
}, {
229
242
.pixclk = 123000000,
230
-
.pll_div_regs = { 0x66, 0x34, 0x82, 0x01, 0x88, 0x45 },
243
+
.pll_div_regs = { 0xd1, 0x66, 0x34, 0x82, 0x01, 0x88, 0x45 },
231
244
}, {
232
245
.pixclk = 127000000,
233
-
.pll_div_regs = { 0x69, 0x34, 0x89, 0x08, 0x80, 0x40 },
246
+
.pll_div_regs = { 0xd1, 0x69, 0x34, 0x89, 0x08, 0x80, 0x40 },
234
247
}, {
235
248
.pixclk = 135000000,
236
-
.pll_div_regs = { 0x70, 0x34, 0x82, 0x01, 0x80, 0x40 },
249
+
.pll_div_regs = { 0xd1, 0x70, 0x34, 0x82, 0x01, 0x80, 0x40 },
237
250
}, {
238
251
.pixclk = 135580000,
239
-
.pll_div_regs = { 0x71, 0x39, 0xe9, 0x82, 0x9c, 0x5b },
252
+
.pll_div_regs = { 0xd1, 0x71, 0x39, 0xe9, 0x82, 0x9c, 0x5b },
240
253
}, {
241
254
.pixclk = 137520000,
242
-
.pll_div_regs = { 0x72, 0x38, 0x99, 0x10, 0x85, 0x41 },
255
+
.pll_div_regs = { 0xd1, 0x72, 0x38, 0x99, 0x10, 0x85, 0x41 },
243
256
}, {
244
257
.pixclk = 138750000,
245
-
.pll_div_regs = { 0x73, 0x35, 0x88, 0x05, 0x90, 0x4d },
258
+
.pll_div_regs = { 0xd1, 0x73, 0x35, 0x88, 0x05, 0x90, 0x4d },
246
259
}, {
247
260
.pixclk = 140000000,
248
-
.pll_div_regs = { 0x75, 0x36, 0xa7, 0x90, 0x80, 0x40 },
261
+
.pll_div_regs = { 0xd1, 0x75, 0x36, 0xa7, 0x90, 0x80, 0x40 },
249
262
}, {
250
263
.pixclk = 144000000,
251
-
.pll_div_regs = { 0x78, 0x30, 0x00, 0x00, 0x80, 0x00 },
264
+
.pll_div_regs = { 0xd1, 0x78, 0x30, 0x00, 0x00, 0x80, 0x00 },
252
265
}, {
253
266
.pixclk = 148352000,
254
-
.pll_div_regs = { 0x7b, 0x35, 0xdb, 0x39, 0x90, 0x45 },
267
+
.pll_div_regs = { 0xd1, 0x7b, 0x35, 0xdb, 0x39, 0x90, 0x45 },
255
268
}, {
256
269
.pixclk = 148500000,
257
-
.pll_div_regs = { 0x7b, 0x35, 0x84, 0x03, 0x90, 0x45 },
270
+
.pll_div_regs = { 0xd1, 0x7b, 0x35, 0x84, 0x03, 0x90, 0x45 },
258
271
}, {
259
272
.pixclk = 154000000,
260
-
.pll_div_regs = { 0x40, 0x18, 0x83, 0x01, 0x00, 0x40 },
273
+
.pll_div_regs = { 0xd1, 0x40, 0x18, 0x83, 0x01, 0x00, 0x40 },
261
274
}, {
262
275
.pixclk = 157000000,
263
-
.pll_div_regs = { 0x41, 0x11, 0xa7, 0x14, 0x80, 0x40 },
276
+
.pll_div_regs = { 0xd1, 0x41, 0x11, 0xa7, 0x14, 0x80, 0x40 },
264
277
}, {
265
278
.pixclk = 160000000,
266
-
.pll_div_regs = { 0x42, 0x12, 0xa1, 0x20, 0x80, 0x40 },
279
+
.pll_div_regs = { 0xd1, 0x42, 0x12, 0xa1, 0x20, 0x80, 0x40 },
267
280
}, {
268
281
.pixclk = 162000000,
269
-
.pll_div_regs = { 0x43, 0x18, 0x8b, 0x08, 0x96, 0x55 },
282
+
.pll_div_regs = { 0xd1, 0x43, 0x18, 0x8b, 0x08, 0x96, 0x55 },
270
283
}, {
271
284
.pixclk = 164000000,
272
-
.pll_div_regs = { 0x45, 0x11, 0x83, 0x82, 0x90, 0x4b },
285
+
.pll_div_regs = { 0xd1, 0x45, 0x11, 0x83, 0x82, 0x90, 0x4b },
273
286
}, {
274
287
.pixclk = 165000000,
275
-
.pll_div_regs = { 0x45, 0x11, 0x84, 0x81, 0x90, 0x4b },
288
+
.pll_div_regs = { 0xd1, 0x45, 0x11, 0x84, 0x81, 0x90, 0x4b },
276
289
}, {
277
290
.pixclk = 180000000,
278
-
.pll_div_regs = { 0x4b, 0x10, 0x00, 0x00, 0x80, 0x00 },
291
+
.pll_div_regs = { 0xd1, 0x4b, 0x10, 0x00, 0x00, 0x80, 0x00 },
279
292
}, {
280
293
.pixclk = 185625000,
281
-
.pll_div_regs = { 0x4e, 0x12, 0x9a, 0x95, 0x80, 0x40 },
294
+
.pll_div_regs = { 0xd1, 0x4e, 0x12, 0x9a, 0x95, 0x80, 0x40 },
282
295
}, {
283
296
.pixclk = 188000000,
284
-
.pll_div_regs = { 0x4e, 0x12, 0xa7, 0x10, 0x80, 0x40 },
297
+
.pll_div_regs = { 0xd1, 0x4e, 0x12, 0xa7, 0x10, 0x80, 0x40 },
285
298
}, {
286
299
.pixclk = 198000000,
287
-
.pll_div_regs = { 0x52, 0x12, 0x82, 0x01, 0x88, 0x47 },
300
+
.pll_div_regs = { 0xd1, 0x52, 0x12, 0x82, 0x01, 0x88, 0x47 },
288
301
}, {
289
302
.pixclk = 205000000,
290
-
.pll_div_regs = { 0x55, 0x12, 0x8c, 0x05, 0x90, 0x4b },
303
+
.pll_div_regs = { 0xd1, 0x55, 0x12, 0x8c, 0x05, 0x90, 0x4b },
291
304
}, {
292
305
.pixclk = 209500000,
293
-
.pll_div_regs = { 0x57, 0x12, 0x98, 0x07, 0x90, 0x49 },
306
+
.pll_div_regs = { 0xd1, 0x57, 0x12, 0x98, 0x07, 0x90, 0x49 },
294
307
}, {
295
308
.pixclk = 213000000,
296
-
.pll_div_regs = { 0x58, 0x12, 0x84, 0x03, 0x82, 0x41 },
309
+
.pll_div_regs = { 0xd1, 0x58, 0x12, 0x84, 0x03, 0x82, 0x41 },
297
310
}, {
298
311
.pixclk = 216000000,
299
-
.pll_div_regs = { 0x5a, 0x10, 0x00, 0x00, 0x80, 0x00 },
312
+
.pll_div_regs = { 0xd1, 0x5a, 0x10, 0x00, 0x00, 0x80, 0x00 },
300
313
}, {
301
314
.pixclk = 216216000,
302
-
.pll_div_regs = { 0x5a, 0x12, 0xfd, 0x0c, 0x80, 0x40 },
315
+
.pll_div_regs = { 0xd1, 0x5a, 0x12, 0xfd, 0x0c, 0x80, 0x40 },
303
316
}, {
304
317
.pixclk = 237600000,
305
-
.pll_div_regs = { 0x63, 0x10, 0x00, 0x00, 0x80, 0x00 },
318
+
.pll_div_regs = { 0xd1, 0x63, 0x10, 0x00, 0x00, 0x80, 0x00 },
306
319
}, {
307
320
.pixclk = 254000000,
308
-
.pll_div_regs = { 0x69, 0x14, 0x89, 0x08, 0x80, 0x40 },
321
+
.pll_div_regs = { 0xd1, 0x69, 0x14, 0x89, 0x08, 0x80, 0x40 },
309
322
}, {
310
323
.pixclk = 277500000,
311
-
.pll_div_regs = { 0x73, 0x15, 0x88, 0x05, 0x90, 0x4d },
324
+
.pll_div_regs = { 0xd1, 0x73, 0x15, 0x88, 0x05, 0x90, 0x4d },
312
325
}, {
313
326
.pixclk = 288000000,
314
-
.pll_div_regs = { 0x78, 0x10, 0x00, 0x00, 0x80, 0x00 },
327
+
.pll_div_regs = { 0xd1, 0x78, 0x10, 0x00, 0x00, 0x80, 0x00 },
315
328
}, {
316
329
.pixclk = 297000000,
317
-
.pll_div_regs = { 0x7b, 0x15, 0x84, 0x03, 0x90, 0x45 },
330
+
.pll_div_regs = { 0xd1, 0x7b, 0x15, 0x84, 0x03, 0x90, 0x45 },
318
331
},
319
332
};
320
333
···
339
322
};
340
323
341
324
static const struct reg_settings common_phy_cfg[] = {
342
-
{ PHY_REG(0), 0x00 }, { PHY_REG(1), 0xd1 },
325
+
{ PHY_REG(0), 0x00 },
326
+
/* PHY_REG(1-7) pix clk specific */
343
327
{ PHY_REG(8), 0x4f }, { PHY_REG(9), 0x30 },
344
328
{ PHY_REG(10), 0x33 }, { PHY_REG(11), 0x65 },
345
329
/* REG12 pixclk specific */
···
433
415
phy->regs + PHY_REG(14));
434
416
}
435
417
418
+
static unsigned long fsl_samsung_hdmi_phy_find_pms(unsigned long fout, u8 *p, u16 *m, u8 *s)
419
+
{
420
+
unsigned long best_freq = 0;
421
+
u32 min_delta = 0xffffffff;
422
+
u8 _p, best_p;
423
+
u16 _m, best_m;
424
+
u8 _s, best_s;
425
+
426
+
/*
427
+
* Figure 13-78 of the reference manual states the PLL should be TMDS x 5
428
+
* while the TMDS_CLKO should be the PLL / 5. So to calculate the PLL,
429
+
* take the pix clock x 5, then return the value of the PLL / 5.
430
+
*/
431
+
fout *= 5;
432
+
433
+
/* The ref manual states the values of 'P' range from 1 to 11 */
434
+
for (_p = 1; _p <= 11; ++_p) {
435
+
for (_s = 1; _s <= 16; ++_s) {
436
+
u64 tmp;
437
+
u32 delta;
438
+
439
+
/* s must be one or even */
440
+
if (_s > 1 && (_s & 0x01) == 1)
441
+
_s++;
442
+
443
+
/* _s cannot be 14 per the TRM */
444
+
if (_s == 14)
445
+
continue;
446
+
447
+
/*
448
+
* TODO: Ref Manual doesn't state the range of _m
449
+
* so this should be further refined if possible.
450
+
* This range was set based on the original values
451
+
* in the lookup table
452
+
*/
453
+
tmp = (u64)fout * (_p * _s);
454
+
do_div(tmp, 24 * MHZ);
455
+
_m = tmp;
456
+
if (_m < 0x30 || _m > 0x7b)
457
+
continue;
458
+
459
+
/*
460
+
* Rev 2 of the Ref Manual states the
461
+
* VCO can range between 750MHz and
462
+
* 3GHz. The VCO is assumed to be
463
+
* Fvco = (M * f_ref) / P,
464
+
* where f_ref is 24MHz.
465
+
*/
466
+
tmp = (u64)_m * 24 * MHZ;
467
+
do_div(tmp, _p);
468
+
if (tmp < 750 * MHZ ||
469
+
tmp > 3000 * MHZ)
470
+
continue;
471
+
472
+
/* Final frequency after post-divider */
473
+
do_div(tmp, _s);
474
+
475
+
delta = abs(fout - tmp);
476
+
if (delta < min_delta) {
477
+
best_p = _p;
478
+
best_s = _s;
479
+
best_m = _m;
480
+
min_delta = delta;
481
+
best_freq = tmp;
482
+
}
483
+
}
484
+
}
485
+
486
+
if (best_freq) {
487
+
*p = best_p;
488
+
*m = best_m;
489
+
*s = best_s;
490
+
}
491
+
492
+
return best_freq / 5;
493
+
}
494
+
436
495
static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy,
437
496
const struct phy_config *cfg)
438
497
{
···
523
428
for (i = 0; i < ARRAY_SIZE(common_phy_cfg); i++)
524
429
writeb(common_phy_cfg[i].val, phy->regs + common_phy_cfg[i].reg);
525
430
526
-
/* set individual PLL registers PHY_REG2 ... PHY_REG7 */
431
+
/* set individual PLL registers PHY_REG1 ... PHY_REG7 */
527
432
for (i = 0; i < PHY_PLL_DIV_REGS_NUM; i++)
528
-
writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG(2) + i * 4);
433
+
writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG(1) + i * 4);
529
434
530
-
/* High nibble of pll_div_regs[1] contains S which also gets written to REG21 */
435
+
/* High nibble of PHY_REG3 and low nibble of PHY_REG21 both contain 'S' */
531
436
writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK,
532
-
cfg->pll_div_regs[1] >> 4), phy->regs + PHY_REG(21));
437
+
cfg->pll_div_regs[2] >> 4), phy->regs + PHY_REG(21));
533
438
534
439
fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg);
535
440
···
554
459
return phy->cur_cfg->pixclk;
555
460
}
556
461
557
-
static long phy_clk_round_rate(struct clk_hw *hw,
558
-
unsigned long rate, unsigned long *parent_rate)
462
+
/* Helper function to lookup the available fractional-divider rate */
463
+
static const struct phy_config *fsl_samsung_hdmi_phy_lookup_rate(unsigned long rate)
559
464
{
560
465
int i;
561
466
467
+
/* Search the lookup table */
562
468
for (i = ARRAY_SIZE(phy_pll_cfg) - 1; i >= 0; i--)
563
469
if (phy_pll_cfg[i].pixclk <= rate)
564
-
return phy_pll_cfg[i].pixclk;
470
+
break;
565
471
566
-
return -EINVAL;
472
+
return &phy_pll_cfg[i];
473
+
}
474
+
475
+
static void fsl_samsung_hdmi_calculate_phy(struct phy_config *cal_phy, unsigned long rate,
476
+
u8 p, u16 m, u8 s)
477
+
{
478
+
cal_phy->pixclk = rate;
479
+
cal_phy->pll_div_regs[0] = FIELD_PREP(REG01_PMS_P_MASK, p);
480
+
cal_phy->pll_div_regs[1] = m;
481
+
cal_phy->pll_div_regs[2] = FIELD_PREP(REG03_PMS_S_MASK, s-1);
482
+
/* pll_div_regs 3-6 are fixed and pre-defined already */
483
+
}
484
+
485
+
static long phy_clk_round_rate(struct clk_hw *hw,
486
+
unsigned long rate, unsigned long *parent_rate)
487
+
{
488
+
const struct phy_config *fract_div_phy;
489
+
u32 int_div_clk;
490
+
u16 m;
491
+
u8 p, s;
492
+
493
+
/* If the clock is out of range return error instead of searching */
494
+
if (rate > 297000000 || rate < 22250000)
495
+
return -EINVAL;
496
+
497
+
/* Search the fractional divider lookup table */
498
+
fract_div_phy = fsl_samsung_hdmi_phy_lookup_rate(rate);
499
+
500
+
/* If the rate is an exact match, return that value */
501
+
if (rate == fract_div_phy->pixclk)
502
+
return fract_div_phy->pixclk;
503
+
504
+
/* If the exact match isn't found, calculate the integer divider */
505
+
int_div_clk = fsl_samsung_hdmi_phy_find_pms(rate, &p, &m, &s);
506
+
507
+
/* If the int_div_clk rate is an exact match, return that value */
508
+
if (int_div_clk == rate)
509
+
return int_div_clk;
510
+
511
+
/* If neither rate is an exact match, use the value from the LUT */
512
+
return fract_div_phy->pixclk;
513
+
}
514
+
515
+
static int phy_use_fract_div(struct fsl_samsung_hdmi_phy *phy, const struct phy_config *fract_div_phy)
516
+
{
517
+
phy->cur_cfg = fract_div_phy;
518
+
dev_dbg(phy->dev, "fsl_samsung_hdmi_phy: using fractional divider rate = %u\n",
519
+
phy->cur_cfg->pixclk);
520
+
return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg);
567
521
}
568
522
569
523
static int phy_clk_set_rate(struct clk_hw *hw,
570
524
unsigned long rate, unsigned long parent_rate)
571
525
{
572
526
struct fsl_samsung_hdmi_phy *phy = to_fsl_samsung_hdmi_phy(hw);
573
-
int i;
527
+
const struct phy_config *fract_div_phy;
528
+
u32 int_div_clk;
529
+
u16 m;
530
+
u8 p, s;
574
531
575
-
for (i = ARRAY_SIZE(phy_pll_cfg) - 1; i >= 0; i--)
576
-
if (phy_pll_cfg[i].pixclk <= rate)
577
-
break;
532
+
/* Search the fractional divider lookup table */
533
+
fract_div_phy = fsl_samsung_hdmi_phy_lookup_rate(rate);
578
534
579
-
if (i < 0)
580
-
return -EINVAL;
535
+
/* If the rate is an exact match, use that value */
536
+
if (fract_div_phy->pixclk == rate)
537
+
return phy_use_fract_div(phy, fract_div_phy);
581
538
582
-
phy->cur_cfg = &phy_pll_cfg[i];
539
+
/*
540
+
* If the rate from the fractional divider is not exact, check the integer divider,
541
+
* and use it if that value is an exact match.
542
+
*/
543
+
int_div_clk = fsl_samsung_hdmi_phy_find_pms(rate, &p, &m, &s);
544
+
if (int_div_clk == rate) {
545
+
dev_dbg(phy->dev, "fsl_samsung_hdmi_phy: integer divider rate = %u\n",
546
+
int_div_clk);
583
547
584
-
return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg);
548
+
fsl_samsung_hdmi_calculate_phy(&calculated_phy_pll_cfg, int_div_clk, p, m, s);
549
+
phy->cur_cfg = &calculated_phy_pll_cfg;
550
+
return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg);
551
+
}
552
+
553
+
/*
554
+
* If neither the fractional divider nor the integer divider can find an exact value
555
+
* fall back to using the fractional divider
556
+
*/
557
+
return phy_use_fract_div(phy, fract_div_phy);
585
558
}
586
559
587
560
static const struct clk_ops phy_clk_ops = {