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phy: freescale: fsl-samsung-hdmi: Simplify REG21_PMS_S_MASK lookup

The value of 'S' is writen to two places, PHY_REG3[7:4] and
PHY_REG21[3:0]. There is a lookup table which contains
the value of PHY_REG3. Rather than using a switch statement
based on the pixel clock to search for the value of 'S' again,
just shift the contents of PHY_REG3[7:4] >> 4 and place the value
in PHY_REG21[3:0]. Doing this can eliminate an entire function.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Dominique Martinet <dominique.martinet@atmark-techno.com>
Tested-by: Dominique Martinet <dominique.martinet@atmark-techno.com>
Link: https://lore.kernel.org/r/20240914112816.520224-3-aford173@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Adam Ford and committed by
Vinod Koul 375ee44a 4a5a9e25

+4 -35
+4 -35
drivers/phy/freescale/phy-fsl-samsung-hdmi.c
··· 365 365 } 366 366 367 367 static void 368 - fsl_samsung_hdmi_phy_configure_pixclk(struct fsl_samsung_hdmi_phy *phy, 369 - const struct phy_config *cfg) 370 - { 371 - u8 div = 0x1; 372 - 373 - switch (cfg->pixclk) { 374 - case 22250000 ... 33750000: 375 - div = 0xf; 376 - break; 377 - case 35000000 ... 40000000: 378 - div = 0xb; 379 - break; 380 - case 43200000 ... 47500000: 381 - div = 0x9; 382 - break; 383 - case 50349650 ... 63500000: 384 - div = 0x7; 385 - break; 386 - case 67500000 ... 90000000: 387 - div = 0x5; 388 - break; 389 - case 94000000 ... 148500000: 390 - div = 0x3; 391 - break; 392 - case 154000000 ... 297000000: 393 - div = 0x1; 394 - break; 395 - } 396 - 397 - writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, div), 398 - phy->regs + PHY_REG(21)); 399 - } 400 - 401 - static void 402 368 fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy, 403 369 const struct phy_config *cfg) 404 370 { ··· 432 466 for (i = 0; i < PHY_PLL_DIV_REGS_NUM; i++) 433 467 writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG(2) + i * 4); 434 468 435 - fsl_samsung_hdmi_phy_configure_pixclk(phy, cfg); 469 + /* High nibble of pll_div_regs[1] contains S which also gets written to REG21 */ 470 + writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, 471 + cfg->pll_div_regs[1] >> 4), phy->regs + PHY_REG(21)); 472 + 436 473 fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg); 437 474 438 475 writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG(33));