-29

Documentation/devicetree/bindings/dma/brcm,iproc-sba.txt

reviewed

··· 1 1 - * Broadcom SBA RAID engine 2 2 - 3 3 - Required properties: 4 4 - - compatible: Should be one of the following 5 5 - "brcm,iproc-sba" 6 6 - "brcm,iproc-sba-v2" 7 7 - The "brcm,iproc-sba" has support for only 6 PQ coefficients 8 8 - The "brcm,iproc-sba-v2" has support for only 30 PQ coefficients 9 9 - - mboxes: List of phandle and mailbox channel specifiers 10 10 - 11 11 - Example: 12 12 - 13 13 - raid_mbox: mbox@67400000 { 14 14 - ... 15 15 - #mbox-cells = <3>; 16 16 - ... 17 17 - }; 18 18 - 19 19 - raid0 { 20 20 - compatible = "brcm,iproc-sba-v2"; 21 21 - mboxes = <&raid_mbox 0 0x1 0xffff>, 22 22 - <&raid_mbox 1 0x1 0xffff>, 23 23 - <&raid_mbox 2 0x1 0xffff>, 24 24 - <&raid_mbox 3 0x1 0xffff>, 25 25 - <&raid_mbox 4 0x1 0xffff>, 26 26 - <&raid_mbox 5 0x1 0xffff>, 27 27 - <&raid_mbox 6 0x1 0xffff>, 28 28 - <&raid_mbox 7 0x1 0xffff>; 29 29 - };

+41

Documentation/devicetree/bindings/dma/brcm,iproc-sba.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/dma/brcm,iproc-sba.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Broadcom SBA RAID engine 8 8 + 9 9 + maintainers: 10 10 + - Ray Jui <rjui@broadcom.com> 11 11 + - Scott Branden <sbranden@broadcom.com> 12 12 + 13 13 + properties: 14 14 + compatible: 15 15 + enum: 16 16 + - brcm,iproc-sba 17 17 + - brcm,iproc-sba-v2 18 18 + 19 19 + mboxes: 20 20 + minItems: 1 21 21 + maxItems: 8 22 22 + 23 23 + required: 24 24 + - compatible 25 25 + - mboxes 26 26 + 27 27 + additionalProperties: false 28 28 + 29 29 + examples: 30 30 + - | 31 31 + raid0 { 32 32 + compatible = "brcm,iproc-sba-v2"; 33 33 + mboxes = <&raid_mbox 0 0x1 0xffff>, 34 34 + <&raid_mbox 1 0x1 0xffff>, 35 35 + <&raid_mbox 2 0x1 0xffff>, 36 36 + <&raid_mbox 3 0x1 0xffff>, 37 37 + <&raid_mbox 4 0x1 0xffff>, 38 38 + <&raid_mbox 5 0x1 0xffff>, 39 39 + <&raid_mbox 6 0x1 0xffff>, 40 40 + <&raid_mbox 7 0x1 0xffff>; 41 41 + };

+33

Documentation/devicetree/bindings/dma/fsl,mxs-dma.yaml

reviewed

··· 23 23 properties: 24 24 power-domains: false 25 25 26 26 + - if: 27 27 + properties: 28 28 + compatible: 29 29 + contains: 30 30 + const: fsl,imx23-dma-apbx 31 31 + then: 32 32 + properties: 33 33 + interrupt-names: 34 34 + items: 35 35 + - const: audio-adc 36 36 + - const: audio-dac 37 37 + - const: spdif-tx 38 38 + - const: i2c 39 39 + - const: saif0 40 40 + - const: empty0 41 41 + - const: auart0-rx 42 42 + - const: auart0-tx 43 43 + - const: auart1-rx 44 44 + - const: auart1-tx 45 45 + - const: saif1 46 46 + - const: empty1 47 47 + - const: empty2 48 48 + - const: empty3 49 49 + - const: empty4 50 50 + - const: empty5 51 51 + else: 52 52 + properties: 53 53 + interrupt-names: false 54 54 + 26 55 properties: 27 56 compatible: 28 57 oneOf: ··· 80 51 maxItems: 1 81 52 82 53 interrupts: 54 54 + minItems: 4 55 55 + maxItems: 16 56 56 + 57 57 + interrupt-names: 83 58 minItems: 4 84 59 maxItems: 16 85 60

+84

Documentation/devicetree/bindings/dma/marvell,orion-xor.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/dma/marvell,orion-xor.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Marvell XOR engine 8 8 + 9 9 + maintainers: 10 10 + - Andrew Lunn <andrew@lunn.ch> 11 11 + - Gregory Clement <gregory.clement@bootlin.com> 12 12 + 13 13 + properties: 14 14 + compatible: 15 15 + oneOf: 16 16 + - items: 17 17 + - const: marvell,armada-380-xor 18 18 + - const: marvell,orion-xor 19 19 + - enum: 20 20 + - marvell,armada-3700-xor 21 21 + - marvell,orion-xor 22 22 + 23 23 + reg: 24 24 + items: 25 25 + - description: Low registers for the XOR engine 26 26 + - description: High registers for the XOR engine 27 27 + 28 28 + clocks: 29 29 + maxItems: 1 30 30 + 31 31 + patternProperties: 32 32 + "^(channel|xor)[0-9]+$": 33 33 + description: XOR channel sub-node 34 34 + type: object 35 35 + additionalProperties: false 36 36 + 37 37 + properties: 38 38 + interrupts: 39 39 + description: Interrupt specifier for the XOR channel 40 40 + items: 41 41 + - description: Interrupt for this channel 42 42 + 43 43 + dmacap,memcpy: 44 44 + type: boolean 45 45 + deprecated: true 46 46 + description: 47 47 + Indicates that the XOR channel is capable of memcpy operations 48 48 + 49 49 + dmacap,memset: 50 50 + type: boolean 51 51 + deprecated: true 52 52 + description: 53 53 + Indicates that the XOR channel is capable of memset operations 54 54 + 55 55 + dmacap,xor: 56 56 + type: boolean 57 57 + deprecated: true 58 58 + description: 59 59 + Indicates that the XOR channel is capable of xor operations 60 60 + 61 61 + required: 62 62 + - interrupts 63 63 + 64 64 + required: 65 65 + - compatible 66 66 + - reg 67 67 + 68 68 + additionalProperties: false 69 69 + 70 70 + examples: 71 71 + - | 72 72 + xor@d0060900 { 73 73 + compatible = "marvell,orion-xor"; 74 74 + reg = <0xd0060900 0x100>, 75 75 + <0xd0060b00 0x100>; 76 76 + clocks = <&coreclk 0>; 77 77 + 78 78 + xor00 { 79 79 + interrupts = <51>; 80 80 + }; 81 81 + xor01 { 82 82 + interrupts = <52>; 83 83 + }; 84 84 + };

-40

Documentation/devicetree/bindings/dma/mv-xor.txt

reviewed

··· 1 1 - * Marvell XOR engines 2 2 - 3 3 - Required properties: 4 4 - - compatible: Should be one of the following: 5 5 - - "marvell,orion-xor" 6 6 - - "marvell,armada-380-xor" 7 7 - - "marvell,armada-3700-xor". 8 8 - - reg: Should contain registers location and length (two sets) 9 9 - the first set is the low registers, the second set the high 10 10 - registers for the XOR engine. 11 11 - - clocks: pointer to the reference clock 12 12 - 13 13 - The DT node must also contains sub-nodes for each XOR channel that the 14 14 - XOR engine has. Those sub-nodes have the following required 15 15 - properties: 16 16 - - interrupts: interrupt of the XOR channel 17 17 - 18 18 - The sub-nodes used to contain one or several of the following 19 19 - properties, but they are now deprecated: 20 20 - - dmacap,memcpy to indicate that the XOR channel is capable of memcpy operations 21 21 - - dmacap,memset to indicate that the XOR channel is capable of memset operations 22 22 - - dmacap,xor to indicate that the XOR channel is capable of xor operations 23 23 - - dmacap,interrupt to indicate that the XOR channel is capable of 24 24 - generating interrupts 25 25 - 26 26 - Example: 27 27 - 28 28 - xor@d0060900 { 29 29 - compatible = "marvell,orion-xor"; 30 30 - reg = <0xd0060900 0x100 31 31 - 0xd0060b00 0x100>; 32 32 - clocks = <&coreclk 0>; 33 33 - 34 34 - xor00 { 35 35 - interrupts = <51>; 36 36 - }; 37 37 - xor01 { 38 38 - interrupts = <52>; 39 39 - }; 40 40 - };

+2

Documentation/devicetree/bindings/dma/qcom,gpi.yaml

reviewed

··· 24 24 - qcom,sm6350-gpi-dma 25 25 - items: 26 26 - enum: 27 27 + - qcom,milos-gpi-dma 27 28 - qcom,qcm2290-gpi-dma 28 29 - qcom,qcs8300-gpi-dma 29 30 - qcom,qdu1000-gpi-dma 30 31 - qcom,sa8775p-gpi-dma 31 32 - qcom,sar2130p-gpi-dma 32 33 - qcom,sc7280-gpi-dma 34 34 + - qcom,sc8280xp-gpi-dma 33 35 - qcom,sdx75-gpi-dma 34 36 - qcom,sm6115-gpi-dma 35 37 - qcom,sm6375-gpi-dma

+51

Documentation/devicetree/bindings/dma/sophgo,cv1800b-dmamux.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/dma/sophgo,cv1800b-dmamux.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Sophgo CV1800/SG200 Series DMA multiplexer 8 8 + 9 9 + maintainers: 10 10 + - Inochi Amaoto <inochiama@gmail.com> 11 11 + 12 12 + description: 13 13 + The DMA multiplexer of CV1800 is a subdevice of the system 14 14 + controller. It support mapping 8 channels, but each channel 15 15 + can be mapped only once. 16 16 + 17 17 + allOf: 18 18 + - $ref: dma-router.yaml# 19 19 + 20 20 + properties: 21 21 + compatible: 22 22 + const: sophgo,cv1800b-dmamux 23 23 + 24 24 + reg: 25 25 + items: 26 26 + - description: DMA channal remapping register 27 27 + - description: DMA channel interrupt mapping register 28 28 + 29 29 + '#dma-cells': 30 30 + const: 2 31 31 + description: 32 32 + The first cells is device id. The second one is the cpu id. 33 33 + 34 34 + dma-masters: 35 35 + maxItems: 1 36 36 + 37 37 + required: 38 38 + - reg 39 39 + - '#dma-cells' 40 40 + - dma-masters 41 41 + 42 42 + additionalProperties: false 43 43 + 44 44 + examples: 45 45 + - | 46 46 + dma-router@154 { 47 47 + compatible = "sophgo,cv1800b-dmamux"; 48 48 + reg = <0x154 0x8>, <0x298 0x4>; 49 49 + #dma-cells = <2>; 50 50 + dma-masters = <&dmac>; 51 51 + };

+10 -2

drivers/dma/Kconfig

reviewed

··· 89 89 tristate "Apple ADMAC support" 90 90 depends on ARCH_APPLE || COMPILE_TEST 91 91 select DMA_ENGINE 92 92 - default ARCH_APPLE 93 92 help 94 93 Enable support for Audio DMA Controller found on Apple Silicon SoCs. 95 94 ··· 110 111 111 112 config AT_XDMAC 112 113 tristate "Atmel XDMA support" 113 113 - depends on ARCH_AT91 114 114 + depends on ARCH_MICROCHIP 114 115 select DMA_ENGINE 115 116 help 116 117 Support the Atmel XDMA controller. ··· 570 571 Some PLX ExpressLane PCI Switches support additional DMA engines. 571 572 These are exposed via extra functions on the switch's 572 573 upstream port. Each function exposes one DMA channel. 574 574 + 575 575 + config SOPHGO_CV1800B_DMAMUX 576 576 + tristate "Sophgo CV1800/SG2000 series SoC DMA multiplexer support" 577 577 + depends on MFD_SYSCON 578 578 + depends on ARCH_SOPHGO || COMPILE_TEST 579 579 + help 580 580 + Support for the DMA multiplexer on Sophgo CV1800/SG2000 581 581 + series SoCs. 582 582 + Say Y here if your board have this soc. 573 583 574 584 config STE_DMA40 575 585 bool "ST-Ericsson DMA40 support"

+1

drivers/dma/Makefile

reviewed

··· 71 71 obj-$(CONFIG_PXA_DMA) += pxa_dma.o 72 72 obj-$(CONFIG_RENESAS_DMA) += sh/ 73 73 obj-$(CONFIG_SF_PDMA) += sf-pdma/ 74 74 + obj-$(CONFIG_SOPHGO_CV1800B_DMAMUX) += cv1800b-dmamux.o 74 75 obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o 75 76 obj-$(CONFIG_SPRD_DMA) += sprd-dma.o 76 77 obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o

+259

drivers/dma/cv1800b-dmamux.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com> 4 4 + */ 5 5 + 6 6 + #include <linux/bitops.h> 7 7 + #include <linux/cleanup.h> 8 8 + #include <linux/module.h> 9 9 + #include <linux/of_dma.h> 10 10 + #include <linux/of_address.h> 11 11 + #include <linux/of_platform.h> 12 12 + #include <linux/platform_device.h> 13 13 + #include <linux/llist.h> 14 14 + #include <linux/regmap.h> 15 15 + #include <linux/spinlock.h> 16 16 + #include <linux/mfd/syscon.h> 17 17 + 18 18 + #define REG_DMA_CHANNEL_REMAP0 0x154 19 19 + #define REG_DMA_CHANNEL_REMAP1 0x158 20 20 + #define REG_DMA_INT_MUX 0x298 21 21 + 22 22 + #define DMAMUX_NCELLS 2 23 23 + #define MAX_DMA_MAPPING_ID 42 24 24 + #define MAX_DMA_CPU_ID 2 25 25 + #define MAX_DMA_CH_ID 7 26 26 + 27 27 + #define DMAMUX_INTMUX_REGISTER_LEN 4 28 28 + #define DMAMUX_NR_CH_PER_REGISTER 4 29 29 + #define DMAMUX_BIT_PER_CH 8 30 30 + #define DMAMUX_CH_MASk GENMASK(5, 0) 31 31 + #define DMAMUX_INT_BIT_PER_CPU 10 32 32 + #define DMAMUX_CH_UPDATE_BIT BIT(31) 33 33 + 34 34 + #define DMAMUX_CH_REGPOS(chid) \ 35 35 + ((chid) / DMAMUX_NR_CH_PER_REGISTER) 36 36 + #define DMAMUX_CH_REGOFF(chid) \ 37 37 + ((chid) % DMAMUX_NR_CH_PER_REGISTER) 38 38 + #define DMAMUX_CH_REG(chid) \ 39 39 + ((DMAMUX_CH_REGPOS(chid) * sizeof(u32)) + \ 40 40 + REG_DMA_CHANNEL_REMAP0) 41 41 + #define DMAMUX_CH_SET(chid, val) \ 42 42 + (((val) << (DMAMUX_CH_REGOFF(chid) * DMAMUX_BIT_PER_CH)) | \ 43 43 + DMAMUX_CH_UPDATE_BIT) 44 44 + #define DMAMUX_CH_MASK(chid) \ 45 45 + DMAMUX_CH_SET(chid, DMAMUX_CH_MASk) 46 46 + 47 47 + #define DMAMUX_INT_BIT(chid, cpuid) \ 48 48 + BIT((cpuid) * DMAMUX_INT_BIT_PER_CPU + (chid)) 49 49 + #define DMAMUX_INTEN_BIT(cpuid) \ 50 50 + DMAMUX_INT_BIT(8, cpuid) 51 51 + #define DMAMUX_INT_CH_BIT(chid, cpuid) \ 52 52 + (DMAMUX_INT_BIT(chid, cpuid) | DMAMUX_INTEN_BIT(cpuid)) 53 53 + #define DMAMUX_INT_MASK(chid) \ 54 54 + (DMAMUX_INT_BIT(chid, 0) | \ 55 55 + DMAMUX_INT_BIT(chid, 1) | \ 56 56 + DMAMUX_INT_BIT(chid, 2)) 57 57 + #define DMAMUX_INT_CH_MASK(chid, cpuid) \ 58 58 + (DMAMUX_INT_MASK(chid) | DMAMUX_INTEN_BIT(cpuid)) 59 59 + 60 60 + struct cv1800_dmamux_data { 61 61 + struct dma_router dmarouter; 62 62 + struct regmap *regmap; 63 63 + spinlock_t lock; 64 64 + struct llist_head free_maps; 65 65 + struct llist_head reserve_maps; 66 66 + DECLARE_BITMAP(mapped_peripherals, MAX_DMA_MAPPING_ID); 67 67 + }; 68 68 + 69 69 + struct cv1800_dmamux_map { 70 70 + struct llist_node node; 71 71 + unsigned int channel; 72 72 + unsigned int peripheral; 73 73 + unsigned int cpu; 74 74 + }; 75 75 + 76 76 + static void cv1800_dmamux_free(struct device *dev, void *route_data) 77 77 + { 78 78 + struct cv1800_dmamux_data *dmamux = dev_get_drvdata(dev); 79 79 + struct cv1800_dmamux_map *map = route_data; 80 80 + 81 81 + guard(spinlock_irqsave)(&dmamux->lock); 82 82 + 83 83 + regmap_update_bits(dmamux->regmap, 84 84 + DMAMUX_CH_REG(map->channel), 85 85 + DMAMUX_CH_MASK(map->channel), 86 86 + DMAMUX_CH_UPDATE_BIT); 87 87 + 88 88 + regmap_update_bits(dmamux->regmap, REG_DMA_INT_MUX, 89 89 + DMAMUX_INT_CH_MASK(map->channel, map->cpu), 90 90 + DMAMUX_INTEN_BIT(map->cpu)); 91 91 + 92 92 + dev_dbg(dev, "free channel %u for req %u (cpu %u)\n", 93 93 + map->channel, map->peripheral, map->cpu); 94 94 + } 95 95 + 96 96 + static void *cv1800_dmamux_route_allocate(struct of_phandle_args *dma_spec, 97 97 + struct of_dma *ofdma) 98 98 + { 99 99 + struct platform_device *pdev = of_find_device_by_node(ofdma->of_node); 100 100 + struct cv1800_dmamux_data *dmamux = platform_get_drvdata(pdev); 101 101 + struct cv1800_dmamux_map *map; 102 102 + struct llist_node *node; 103 103 + unsigned long flags; 104 104 + unsigned int chid, devid, cpuid; 105 105 + int ret; 106 106 + 107 107 + if (dma_spec->args_count != DMAMUX_NCELLS) { 108 108 + dev_err(&pdev->dev, "invalid number of dma mux args\n"); 109 109 + return ERR_PTR(-EINVAL); 110 110 + } 111 111 + 112 112 + devid = dma_spec->args[0]; 113 113 + cpuid = dma_spec->args[1]; 114 114 + dma_spec->args_count = 1; 115 115 + 116 116 + if (devid > MAX_DMA_MAPPING_ID) { 117 117 + dev_err(&pdev->dev, "invalid device id: %u\n", devid); 118 118 + return ERR_PTR(-EINVAL); 119 119 + } 120 120 + 121 121 + if (cpuid > MAX_DMA_CPU_ID) { 122 122 + dev_err(&pdev->dev, "invalid cpu id: %u\n", cpuid); 123 123 + return ERR_PTR(-EINVAL); 124 124 + } 125 125 + 126 126 + dma_spec->np = of_parse_phandle(ofdma->of_node, "dma-masters", 0); 127 127 + if (!dma_spec->np) { 128 128 + dev_err(&pdev->dev, "can't get dma master\n"); 129 129 + return ERR_PTR(-EINVAL); 130 130 + } 131 131 + 132 132 + spin_lock_irqsave(&dmamux->lock, flags); 133 133 + 134 134 + if (test_bit(devid, dmamux->mapped_peripherals)) { 135 135 + llist_for_each_entry(map, dmamux->reserve_maps.first, node) { 136 136 + if (map->peripheral == devid && map->cpu == cpuid) 137 137 + goto found; 138 138 + } 139 139 + 140 140 + ret = -EINVAL; 141 141 + goto failed; 142 142 + } else { 143 143 + node = llist_del_first(&dmamux->free_maps); 144 144 + if (!node) { 145 145 + ret = -ENODEV; 146 146 + goto failed; 147 147 + } 148 148 + 149 149 + map = llist_entry(node, struct cv1800_dmamux_map, node); 150 150 + llist_add(&map->node, &dmamux->reserve_maps); 151 151 + set_bit(devid, dmamux->mapped_peripherals); 152 152 + } 153 153 + 154 154 + found: 155 155 + chid = map->channel; 156 156 + map->peripheral = devid; 157 157 + map->cpu = cpuid; 158 158 + 159 159 + regmap_set_bits(dmamux->regmap, 160 160 + DMAMUX_CH_REG(chid), 161 161 + DMAMUX_CH_SET(chid, devid)); 162 162 + 163 163 + regmap_update_bits(dmamux->regmap, REG_DMA_INT_MUX, 164 164 + DMAMUX_INT_CH_MASK(chid, cpuid), 165 165 + DMAMUX_INT_CH_BIT(chid, cpuid)); 166 166 + 167 167 + spin_unlock_irqrestore(&dmamux->lock, flags); 168 168 + 169 169 + dma_spec->args[0] = chid; 170 170 + 171 171 + dev_dbg(&pdev->dev, "register channel %u for req %u (cpu %u)\n", 172 172 + chid, devid, cpuid); 173 173 + 174 174 + return map; 175 175 + 176 176 + failed: 177 177 + spin_unlock_irqrestore(&dmamux->lock, flags); 178 178 + of_node_put(dma_spec->np); 179 179 + dev_err(&pdev->dev, "errno %d\n", ret); 180 180 + return ERR_PTR(ret); 181 181 + } 182 182 + 183 183 + static int cv1800_dmamux_probe(struct platform_device *pdev) 184 184 + { 185 185 + struct device *dev = &pdev->dev; 186 186 + struct device_node *mux_node = dev->of_node; 187 187 + struct cv1800_dmamux_data *data; 188 188 + struct cv1800_dmamux_map *tmp; 189 189 + struct device *parent = dev->parent; 190 190 + struct regmap *regmap = NULL; 191 191 + unsigned int i; 192 192 + 193 193 + if (!parent) 194 194 + return -ENODEV; 195 195 + 196 196 + regmap = device_node_to_regmap(parent->of_node); 197 197 + if (IS_ERR(regmap)) 198 198 + return PTR_ERR(regmap); 199 199 + 200 200 + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 201 201 + if (!data) 202 202 + return -ENOMEM; 203 203 + 204 204 + spin_lock_init(&data->lock); 205 205 + init_llist_head(&data->free_maps); 206 206 + init_llist_head(&data->reserve_maps); 207 207 + 208 208 + for (i = 0; i <= MAX_DMA_CH_ID; i++) { 209 209 + tmp = devm_kmalloc(dev, sizeof(*tmp), GFP_KERNEL); 210 210 + if (!tmp) { 211 211 + /* It is OK for not allocating all channel */ 212 212 + dev_warn(dev, "can not allocate channel %u\n", i); 213 213 + continue; 214 214 + } 215 215 + 216 216 + init_llist_node(&tmp->node); 217 217 + tmp->channel = i; 218 218 + llist_add(&tmp->node, &data->free_maps); 219 219 + } 220 220 + 221 221 + /* if no channel is allocated, the probe must fail */ 222 222 + if (llist_empty(&data->free_maps)) 223 223 + return -ENOMEM; 224 224 + 225 225 + data->regmap = regmap; 226 226 + data->dmarouter.dev = dev; 227 227 + data->dmarouter.route_free = cv1800_dmamux_free; 228 228 + 229 229 + platform_set_drvdata(pdev, data); 230 230 + 231 231 + return of_dma_router_register(mux_node, 232 232 + cv1800_dmamux_route_allocate, 233 233 + &data->dmarouter); 234 234 + } 235 235 + 236 236 + static void cv1800_dmamux_remove(struct platform_device *pdev) 237 237 + { 238 238 + of_dma_controller_free(pdev->dev.of_node); 239 239 + } 240 240 + 241 241 + static const struct of_device_id cv1800_dmamux_ids[] = { 242 242 + { .compatible = "sophgo,cv1800b-dmamux", }, 243 243 + { } 244 244 + }; 245 245 + MODULE_DEVICE_TABLE(of, cv1800_dmamux_ids); 246 246 + 247 247 + static struct platform_driver cv1800_dmamux_driver = { 248 248 + .probe = cv1800_dmamux_probe, 249 249 + .remove = cv1800_dmamux_remove, 250 250 + .driver = { 251 251 + .name = "cv1800-dmamux", 252 252 + .of_match_table = cv1800_dmamux_ids, 253 253 + }, 254 254 + }; 255 255 + module_platform_driver(cv1800_dmamux_driver); 256 256 + 257 257 + MODULE_AUTHOR("Inochi Amaoto <inochiama@gmail.com>"); 258 258 + MODULE_DESCRIPTION("Sophgo CV1800/SG2000 Series SoC DMAMUX driver"); 259 259 + MODULE_LICENSE("GPL");

-12

drivers/dma/dw-edma/dw-edma-core.c

reviewed

··· 24 24 #include "../virt-dma.h" 25 25 26 26 static inline 27 27 - struct device *dchan2dev(struct dma_chan *dchan) 28 28 - { 29 29 - return &dchan->dev->device; 30 30 - } 31 31 - 32 32 - static inline 33 33 - struct device *chan2dev(struct dw_edma_chan *chan) 34 34 - { 35 35 - return &chan->vc.chan.dev->device; 36 36 - } 37 37 - 38 38 - static inline 39 27 struct dw_edma_desc *vd2dw_edma_desc(struct virt_dma_desc *vd) 40 28 { 41 29 return container_of(vd, struct dw_edma_desc, vd);

-5

drivers/dma/fsl-dpaa2-qdma/dpdmai.c

reviewed

··· 48 48 __le32 dpdmai_id; 49 49 } __packed; 50 50 51 51 - static inline u64 mc_enc(int lsoffset, int width, u64 val) 52 52 - { 53 53 - return (val & MAKE_UMASK64(width)) << lsoffset; 54 54 - } 55 55 - 56 51 /** 57 52 * dpdmai_open() - Open a control session for the specified object 58 53 * @mc_io: Pointer to MC portal's I/O object

+3

drivers/dma/fsl-qdma.c

reviewed

··· 148 148 * @__reserved1: Reserved field. 149 149 * @cfg8b_w1: Compound descriptor command queue origin produced 150 150 * by qDMA and dynamic debug field. 151 151 + * @__reserved2: Reserved field. 152 152 + * @cmd: Command for QDMA (see FSL_QDMA_CMD_RWTTYPE and 153 153 + * others). 151 154 * @data: Pointer to the memory 40-bit address, describes DMA 152 155 * source information and DMA destination information. 153 156 */

-1

drivers/dma/idxd/init.c

reviewed

··· 1036 1036 const char *idxd_name; 1037 1037 int rc; 1038 1038 1039 1039 - dev = &idxd->pdev->dev; 1040 1039 idxd_name = dev_name(idxd_confdev(idxd)); 1041 1040 1042 1041 struct idxd_saved_states *idxd_saved __free(kfree) =

+30 -30

drivers/dma/idxd/registers.h

reviewed

··· 45 45 u64 rsvd3:32; 46 46 }; 47 47 u64 bits; 48 48 - } __packed; 48 48 + }; 49 49 #define IDXD_GENCAP_OFFSET 0x10 50 50 51 51 union wq_cap_reg { ··· 65 65 u64 rsvd4:8; 66 66 }; 67 67 u64 bits; 68 68 - } __packed; 68 68 + }; 69 69 #define IDXD_WQCAP_OFFSET 0x20 70 70 #define IDXD_WQCFG_MIN 5 71 71 ··· 79 79 u64 rsvd:45; 80 80 }; 81 81 u64 bits; 82 82 - } __packed; 82 82 + }; 83 83 #define IDXD_GRPCAP_OFFSET 0x30 84 84 85 85 union engine_cap_reg { ··· 88 88 u64 rsvd:56; 89 89 }; 90 90 u64 bits; 91 91 - } __packed; 91 91 + }; 92 92 93 93 #define IDXD_ENGCAP_OFFSET 0x38 94 94 ··· 114 114 u64 rsvd:48; 115 115 }; 116 116 u64 bits[2]; 117 117 - } __packed; 117 117 + }; 118 118 119 119 #define IDXD_TABLE_MULT 0x100 120 120 ··· 128 128 u32 rsvd2:18; 129 129 }; 130 130 u32 bits; 131 131 - } __packed; 131 131 + }; 132 132 133 133 #define IDXD_GENCTRL_OFFSET 0x88 134 134 union genctrl_reg { ··· 139 139 u32 rsvd:29; 140 140 }; 141 141 u32 bits; 142 142 - } __packed; 142 142 + }; 143 143 144 144 #define IDXD_GENSTATS_OFFSET 0x90 145 145 union gensts_reg { ··· 149 149 u32 rsvd:28; 150 150 }; 151 151 u32 bits; 152 152 - } __packed; 152 152 + }; 153 153 154 154 enum idxd_device_status_state { 155 155 IDXD_DEVICE_STATE_DISABLED = 0, ··· 183 183 u32 int_req:1; 184 184 }; 185 185 u32 bits; 186 186 - } __packed; 186 186 + }; 187 187 188 188 enum idxd_cmd { 189 189 IDXD_CMD_ENABLE_DEVICE = 1, ··· 213 213 u8 active:1; 214 214 }; 215 215 u32 bits; 216 216 - } __packed; 216 216 + }; 217 217 #define IDXD_CMDSTS_ACTIVE 0x80000000 218 218 #define IDXD_CMDSTS_ERR_MASK 0xff 219 219 #define IDXD_CMDSTS_RES_SHIFT 8 ··· 284 284 u64 rsvd5; 285 285 }; 286 286 u64 bits[4]; 287 287 - } __packed; 287 287 + }; 288 288 289 289 union iaa_cap_reg { 290 290 struct { ··· 303 303 u64 rsvd:52; 304 304 }; 305 305 u64 bits; 306 306 - } __packed; 306 306 + }; 307 307 308 308 #define IDXD_IAACAP_OFFSET 0x180 309 309 ··· 320 320 u64 rsvd2:28; 321 321 }; 322 322 u64 bits[2]; 323 323 - } __packed; 323 323 + }; 324 324 325 325 #define IDXD_EVL_SIZE_MIN 0x0040 326 326 #define IDXD_EVL_SIZE_MAX 0xffff ··· 334 334 u32 pasid:20; 335 335 }; 336 336 u32 bits; 337 337 - } __packed; 337 337 + }; 338 338 339 339 union group_flags { 340 340 struct { ··· 352 352 u64 rsvd5:26; 353 353 }; 354 354 u64 bits; 355 355 - } __packed; 355 355 + }; 356 356 357 357 struct grpcfg { 358 358 u64 wqs[4]; 359 359 u64 engines; 360 360 union group_flags flags; 361 361 - } __packed; 361 361 + }; 362 362 363 363 union wqcfg { 364 364 struct { ··· 410 410 u64 op_config[4]; 411 411 }; 412 412 u32 bits[16]; 413 413 - } __packed; 413 413 + }; 414 414 415 415 #define WQCFG_PASID_IDX 2 416 416 #define WQCFG_PRIVL_IDX 2 ··· 474 474 u64 rsvd3:8; 475 475 }; 476 476 u64 bits; 477 477 - } __packed; 477 477 + }; 478 478 479 479 #define IDXD_EVNTCAP_OFFSET 0x80 480 480 union idxd_evntcap { ··· 483 483 u64 rsvd:36; 484 484 }; 485 485 u64 bits; 486 486 - } __packed; 486 486 + }; 487 487 488 488 struct idxd_event { 489 489 union { ··· 493 493 }; 494 494 u32 val; 495 495 }; 496 496 - } __packed; 496 496 + }; 497 497 498 498 #define IDXD_CNTRCAP_OFFSET 0x800 499 499 struct idxd_cntrcap { ··· 506 506 u32 val; 507 507 }; 508 508 struct idxd_event events[]; 509 509 - } __packed; 509 509 + }; 510 510 511 511 #define IDXD_PERFRST_OFFSET 0x10 512 512 union idxd_perfrst { ··· 516 516 u32 rsvd:30; 517 517 }; 518 518 u32 val; 519 519 - } __packed; 519 519 + }; 520 520 521 521 #define IDXD_OVFSTATUS_OFFSET 0x30 522 522 #define IDXD_PERFFRZ_OFFSET 0x20 ··· 533 533 u64 rsvd3:4; 534 534 }; 535 535 u64 val; 536 536 - } __packed; 536 536 + }; 537 537 538 538 #define IDXD_FLTCFG_OFFSET 0x300 539 539 ··· 543 543 u64 event_count_value; 544 544 }; 545 545 u64 val; 546 546 - } __packed; 546 546 + }; 547 547 548 548 union event_cfg { 549 549 struct { ··· 551 551 u64 event_enc:28; 552 552 }; 553 553 u64 val; 554 554 - } __packed; 554 554 + }; 555 555 556 556 union filter_cfg { 557 557 struct { ··· 562 562 u64 eng:8; 563 563 }; 564 564 u64 val; 565 565 - } __packed; 565 565 + }; 566 566 567 567 #define IDXD_EVLSTATUS_OFFSET 0xf0 568 568 ··· 580 580 u32 bits_upper32; 581 581 }; 582 582 u64 bits; 583 583 - } __packed; 583 583 + }; 584 584 585 585 #define IDXD_MAX_BATCH_IDENT 256 586 586 ··· 620 620 }; 621 621 u64 fault_addr; 622 622 u64 rsvd5; 623 623 - } __packed; 623 623 + }; 624 624 625 625 struct dsa_evl_entry { 626 626 struct __evl_entry e; 627 627 struct dsa_completion_record cr; 628 628 - } __packed; 628 628 + }; 629 629 630 630 struct iax_evl_entry { 631 631 struct __evl_entry e; 632 632 u64 rsvd[4]; 633 633 struct iax_completion_record cr; 634 634 - } __packed; 634 634 + }; 635 635 636 636 #endif

+1 -1

drivers/dma/mmp_tdma.c

reviewed

··· 641 641 int chan_num = TDMA_CHANNEL_NUM; 642 642 struct gen_pool *pool = NULL; 643 643 644 644 - type = (enum mmp_tdma_type)device_get_match_data(&pdev->dev); 644 644 + type = (kernel_ulong_t)device_get_match_data(&pdev->dev); 645 645 646 646 /* always have couple channels */ 647 647 tdev = devm_kzalloc(&pdev->dev, sizeof(*tdev), GFP_KERNEL);

+19 -2

drivers/dma/mv_xor.c

reviewed

··· 1061 1061 */ 1062 1062 mv_chan->dummy_src_addr = dma_map_single(dma_dev->dev, 1063 1063 mv_chan->dummy_src, MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE); 1064 1064 + if (dma_mapping_error(dma_dev->dev, mv_chan->dummy_src_addr)) 1065 1065 + return ERR_PTR(-ENOMEM); 1066 1066 + 1064 1067 mv_chan->dummy_dst_addr = dma_map_single(dma_dev->dev, 1065 1068 mv_chan->dummy_dst, MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE); 1069 1069 + if (dma_mapping_error(dma_dev->dev, mv_chan->dummy_dst_addr)) { 1070 1070 + ret = -ENOMEM; 1071 1071 + goto err_unmap_src; 1072 1072 + } 1073 1073 + 1066 1074 1067 1075 /* allocate coherent memory for hardware descriptors 1068 1076 * note: writecombine gives slightly better performance, but ··· 1079 1071 mv_chan->dma_desc_pool_virt = 1080 1072 dma_alloc_wc(&pdev->dev, MV_XOR_POOL_SIZE, &mv_chan->dma_desc_pool, 1081 1073 GFP_KERNEL); 1082 1082 - if (!mv_chan->dma_desc_pool_virt) 1083 1083 - return ERR_PTR(-ENOMEM); 1074 1074 + if (!mv_chan->dma_desc_pool_virt) { 1075 1075 + ret = -ENOMEM; 1076 1076 + goto err_unmap_dst; 1077 1077 + } 1084 1078 1085 1079 /* discover transaction capabilities from the platform data */ 1086 1080 dma_dev->cap_mask = cap_mask; ··· 1165 1155 err_free_dma: 1166 1156 dma_free_coherent(&pdev->dev, MV_XOR_POOL_SIZE, 1167 1157 mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool); 1158 1158 + err_unmap_dst: 1159 1159 + dma_unmap_single(dma_dev->dev, mv_chan->dummy_dst_addr, 1160 1160 + MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE); 1161 1161 + err_unmap_src: 1162 1162 + dma_unmap_single(dma_dev->dev, mv_chan->dummy_src_addr, 1163 1163 + MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE); 1164 1164 + 1168 1165 return ERR_PTR(ret); 1169 1166 } 1170 1167

+13

drivers/dma/nbpfaxi.c

reviewed

··· 711 711 list_add_tail(&ldesc->node, &lhead); 712 712 ldesc->hwdesc_dma_addr = dma_map_single(dchan->device->dev, 713 713 hwdesc, sizeof(*hwdesc), DMA_TO_DEVICE); 714 714 + if (dma_mapping_error(dchan->device->dev, 715 715 + ldesc->hwdesc_dma_addr)) 716 716 + goto unmap_error; 714 717 715 718 dev_dbg(dev, "%s(): mapped 0x%p to %pad\n", __func__, 716 719 hwdesc, &ldesc->hwdesc_dma_addr); ··· 740 737 spin_unlock_irq(&chan->lock); 741 738 742 739 return ARRAY_SIZE(dpage->desc); 740 740 + 741 741 + unmap_error: 742 742 + while (i--) { 743 743 + ldesc--; hwdesc--; 744 744 + 745 745 + dma_unmap_single(dchan->device->dev, ldesc->hwdesc_dma_addr, 746 746 + sizeof(hwdesc), DMA_TO_DEVICE); 747 747 + } 748 748 + 749 749 + return -ENOMEM; 743 750 } 744 751 745 752 static void nbpf_desc_put(struct nbpf_desc *desc)

-11

drivers/dma/qcom/gpi.c

reviewed

··· 569 569 writel_relaxed(val, addr); 570 570 } 571 571 572 572 - /* gpi_write_reg_field - write to specific bit field */ 573 573 - static inline void gpi_write_reg_field(struct gpii *gpii, void __iomem *addr, 574 574 - u32 mask, u32 shift, u32 val) 575 575 - { 576 576 - u32 tmp = gpi_read_reg(gpii, addr); 577 577 - 578 578 - tmp &= ~mask; 579 579 - val = tmp | ((val << shift) & mask); 580 580 - gpi_write_reg(gpii, addr, val); 581 581 - } 582 582 - 583 572 static __always_inline void 584 573 gpi_update_reg(struct gpii *gpii, u32 offset, u32 mask, u32 val) 585 574 {

+1 -1

drivers/dma/sh/Kconfig

reviewed

··· 16 16 depends on SUPERH || COMPILE_TEST 17 17 depends on !SUPERH || SH_DMA 18 18 depends on !SH_DMA_API 19 19 - default y 19 19 + default SUPERH || SH_DMA 20 20 select RENESAS_DMA 21 21 help 22 22 Enable support for the Renesas SuperH DMA controllers.

+6 -6

drivers/dma/stm32/stm32-dma.c

reviewed

··· 613 613 reg->dma_scr |= STM32_DMA_SCR_EN; 614 614 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); 615 615 616 616 - dev_dbg(chan2dev(chan), "vchan %pK: started\n", &chan->vchan); 616 616 + dev_dbg(chan2dev(chan), "vchan %p: started\n", &chan->vchan); 617 617 } 618 618 619 619 static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan) ··· 676 676 677 677 chan->status = DMA_PAUSED; 678 678 679 679 - dev_dbg(chan2dev(chan), "vchan %pK: paused\n", &chan->vchan); 679 679 + dev_dbg(chan2dev(chan), "vchan %p: paused\n", &chan->vchan); 680 680 } 681 681 682 682 static void stm32_dma_post_resume_reconfigure(struct stm32_dma_chan *chan) ··· 728 728 dma_scr |= STM32_DMA_SCR_EN; 729 729 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr); 730 730 731 731 - dev_dbg(chan2dev(chan), "vchan %pK: reconfigured after pause/resume\n", &chan->vchan); 731 731 + dev_dbg(chan2dev(chan), "vchan %p: reconfigured after pause/resume\n", &chan->vchan); 732 732 } 733 733 734 734 static void stm32_dma_handle_chan_done(struct stm32_dma_chan *chan, u32 scr) ··· 744 744 /* cyclic while CIRC/DBM disable => post resume reconfiguration needed */ 745 745 if (!(scr & (STM32_DMA_SCR_CIRC | STM32_DMA_SCR_DBM))) 746 746 stm32_dma_post_resume_reconfigure(chan); 747 747 - else if (scr & STM32_DMA_SCR_DBM) 747 747 + else if (scr & STM32_DMA_SCR_DBM && chan->desc->num_sgs > 2) 748 748 stm32_dma_configure_next_sg(chan); 749 749 } else { 750 750 chan->busy = false; ··· 820 820 821 821 spin_lock_irqsave(&chan->vchan.lock, flags); 822 822 if (vchan_issue_pending(&chan->vchan) && !chan->desc && !chan->busy) { 823 823 - dev_dbg(chan2dev(chan), "vchan %pK: issued\n", &chan->vchan); 823 823 + dev_dbg(chan2dev(chan), "vchan %p: issued\n", &chan->vchan); 824 824 stm32_dma_start_transfer(chan); 825 825 826 826 } ··· 922 922 923 923 spin_unlock_irqrestore(&chan->vchan.lock, flags); 924 924 925 925 - dev_dbg(chan2dev(chan), "vchan %pK: resumed\n", &chan->vchan); 925 925 + dev_dbg(chan2dev(chan), "vchan %p: resumed\n", &chan->vchan); 926 926 927 927 return 0; 928 928 }

+5 -5

drivers/dma/stm32/stm32-dma3.c

reviewed

··· 801 801 802 802 chan->dma_status = DMA_IN_PROGRESS; 803 803 804 804 - dev_dbg(chan2dev(chan), "vchan %pK: started\n", &chan->vchan); 804 804 + dev_dbg(chan2dev(chan), "vchan %p: started\n", &chan->vchan); 805 805 } 806 806 807 807 static int stm32_dma3_chan_suspend(struct stm32_dma3_chan *chan, bool susp) ··· 1452 1452 1453 1453 chan->dma_status = DMA_PAUSED; 1454 1454 1455 1455 - dev_dbg(chan2dev(chan), "vchan %pK: paused\n", &chan->vchan); 1455 1455 + dev_dbg(chan2dev(chan), "vchan %p: paused\n", &chan->vchan); 1456 1456 1457 1457 return 0; 1458 1458 } ··· 1465 1465 1466 1466 chan->dma_status = DMA_IN_PROGRESS; 1467 1467 1468 1468 - dev_dbg(chan2dev(chan), "vchan %pK: resumed\n", &chan->vchan); 1468 1468 + dev_dbg(chan2dev(chan), "vchan %p: resumed\n", &chan->vchan); 1469 1469 1470 1470 return 0; 1471 1471 } ··· 1490 1490 spin_unlock_irqrestore(&chan->vchan.lock, flags); 1491 1491 vchan_dma_desc_free_list(&chan->vchan, &head); 1492 1492 1493 1493 - dev_dbg(chan2dev(chan), "vchan %pK: terminated\n", &chan->vchan); 1493 1493 + dev_dbg(chan2dev(chan), "vchan %p: terminated\n", &chan->vchan); 1494 1494 1495 1495 return 0; 1496 1496 } ··· 1543 1543 spin_lock_irqsave(&chan->vchan.lock, flags); 1544 1544 1545 1545 if (vchan_issue_pending(&chan->vchan) && !chan->swdesc) { 1546 1546 - dev_dbg(chan2dev(chan), "vchan %pK: issued\n", &chan->vchan); 1546 1546 + dev_dbg(chan2dev(chan), "vchan %p: issued\n", &chan->vchan); 1547 1547 stm32_dma3_chan_start(chan); 1548 1548 } 1549 1549

+4 -4

drivers/dma/stm32/stm32-mdma.c

reviewed

··· 1187 1187 1188 1188 chan->busy = true; 1189 1189 1190 1190 - dev_dbg(chan2dev(chan), "vchan %pK: started\n", &chan->vchan); 1190 1190 + dev_dbg(chan2dev(chan), "vchan %p: started\n", &chan->vchan); 1191 1191 } 1192 1192 1193 1193 static void stm32_mdma_issue_pending(struct dma_chan *c) ··· 1200 1200 if (!vchan_issue_pending(&chan->vchan)) 1201 1201 goto end; 1202 1202 1203 1203 - dev_dbg(chan2dev(chan), "vchan %pK: issued\n", &chan->vchan); 1203 1203 + dev_dbg(chan2dev(chan), "vchan %p: issued\n", &chan->vchan); 1204 1204 1205 1205 if (!chan->desc && !chan->busy) 1206 1206 stm32_mdma_start_transfer(chan); ··· 1220 1220 spin_unlock_irqrestore(&chan->vchan.lock, flags); 1221 1221 1222 1222 if (!ret) 1223 1223 - dev_dbg(chan2dev(chan), "vchan %pK: pause\n", &chan->vchan); 1223 1223 + dev_dbg(chan2dev(chan), "vchan %p: pause\n", &chan->vchan); 1224 1224 1225 1225 return ret; 1226 1226 } ··· 1261 1261 1262 1262 spin_unlock_irqrestore(&chan->vchan.lock, flags); 1263 1263 1264 1264 - dev_dbg(chan2dev(chan), "vchan %pK: resume\n", &chan->vchan); 1264 1264 + dev_dbg(chan2dev(chan), "vchan %p: resume\n", &chan->vchan); 1265 1265 1266 1266 return 0; 1267 1267 }

+13 -33

drivers/dma/sun4i-dma.c

reviewed

··· 1249 1249 if (priv->irq < 0) 1250 1250 return priv->irq; 1251 1251 1252 1252 - priv->clk = devm_clk_get(&pdev->dev, NULL); 1253 1253 - if (IS_ERR(priv->clk)) { 1254 1254 - dev_err(&pdev->dev, "No clock specified\n"); 1255 1255 - return PTR_ERR(priv->clk); 1256 1256 - } 1252 1252 + priv->clk = devm_clk_get_enabled(&pdev->dev, NULL); 1253 1253 + if (IS_ERR(priv->clk)) 1254 1254 + return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk), 1255 1255 + "Couldn't start the clock\n"); 1257 1256 1258 1257 if (priv->cfg->has_reset) { 1259 1258 priv->rst = devm_reset_control_get_exclusive_deasserted(&pdev->dev, NULL); ··· 1327 1328 vchan_init(&vchan->vc, &priv->slave); 1328 1329 } 1329 1330 1330 1330 - ret = clk_prepare_enable(priv->clk); 1331 1331 - if (ret) { 1332 1332 - dev_err(&pdev->dev, "Couldn't enable the clock\n"); 1333 1333 - return ret; 1334 1334 - } 1335 1335 - 1336 1331 /* 1337 1332 * Make sure the IRQs are all disabled and accounted for. The bootloader 1338 1333 * likes to leave these dirty ··· 1336 1343 1337 1344 ret = devm_request_irq(&pdev->dev, priv->irq, sun4i_dma_interrupt, 1338 1345 0, dev_name(&pdev->dev), priv); 1339 1339 - if (ret) { 1340 1340 - dev_err(&pdev->dev, "Cannot request IRQ\n"); 1341 1341 - goto err_clk_disable; 1342 1342 - } 1346 1346 + if (ret) 1347 1347 + return dev_err_probe(&pdev->dev, ret, "Cannot request IRQ\n"); 1343 1348 1344 1344 - ret = dma_async_device_register(&priv->slave); 1345 1345 - if (ret) { 1346 1346 - dev_warn(&pdev->dev, "Failed to register DMA engine device\n"); 1347 1347 - goto err_clk_disable; 1348 1348 - } 1349 1349 + ret = dmaenginem_async_device_register(&priv->slave); 1350 1350 + if (ret) 1351 1351 + return dev_err_probe(&pdev->dev, ret, 1352 1352 + "Failed to register DMA engine device\n"); 1349 1353 1350 1354 ret = of_dma_controller_register(pdev->dev.of_node, sun4i_dma_of_xlate, 1351 1355 priv); 1352 1352 - if (ret) { 1353 1353 - dev_err(&pdev->dev, "of_dma_controller_register failed\n"); 1354 1354 - goto err_dma_unregister; 1355 1355 - } 1356 1356 + if (ret) 1357 1357 + return dev_err_probe(&pdev->dev, ret, 1358 1358 + "Failed to register translation function\n"); 1356 1359 1357 1360 dev_dbg(&pdev->dev, "Successfully probed SUN4I_DMA\n"); 1358 1361 1359 1362 return 0; 1360 1360 - 1361 1361 - err_dma_unregister: 1362 1362 - dma_async_device_unregister(&priv->slave); 1363 1363 - err_clk_disable: 1364 1364 - clk_disable_unprepare(priv->clk); 1365 1365 - return ret; 1366 1363 } 1367 1364 1368 1365 static void sun4i_dma_remove(struct platform_device *pdev) ··· 1363 1380 disable_irq(priv->irq); 1364 1381 1365 1382 of_dma_controller_free(pdev->dev.of_node); 1366 1366 - dma_async_device_unregister(&priv->slave); 1367 1367 - 1368 1368 - clk_disable_unprepare(priv->clk); 1369 1383 } 1370 1384 1371 1385 static struct sun4i_dma_config sun4i_a10_dma_cfg = {

+2 -2

drivers/dma/ti/Kconfig

reviewed

··· 17 17 select DMA_ENGINE 18 18 select DMA_VIRTUAL_CHANNELS 19 19 select TI_DMA_CROSSBAR if (ARCH_OMAP || COMPILE_TEST) 20 20 - default y 20 20 + default ARCH_DAVINCI || ARCH_OMAP || ARCH_KEYSTONE 21 21 help 22 22 Enable support for the TI EDMA (Enhanced DMA) controller. This DMA 23 23 engine is found on TI DaVinci, AM33xx, AM43xx, DRA7xx and Keystone 2 ··· 29 29 select DMA_ENGINE 30 30 select DMA_VIRTUAL_CHANNELS 31 31 select TI_DMA_CROSSBAR if (SOC_DRA7XX || COMPILE_TEST) 32 32 - default y 32 32 + default ARCH_OMAP 33 33 help 34 34 Enable support for the TI sDMA (System DMA or DMA4) controller. This 35 35 DMA engine is found on OMAP and DRA7xx parts.