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Documentation: nova: remove register abstraction task

The `register!` macro has been implemented and all nova-core code
converted to use it. Remove the corresponding task in todo.rst.

Reviewed-by: Eliot Courtney <ecourtney@nvidia.com>
Reviewed-by: Gary Guo <gary@garyguo.net>
Acked-by: Danilo Krummrich <dakr@kernel.org>
Link: https://patch.msgid.link/20260325-b4-nova-register-v4-10-bdf172f0f6ca@nvidia.com
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>

-76
-76
Documentation/gpu/nova/core/todo.rst
··· 51 51 | Link: https://lore.kernel.org/all/cover.1750689857.git.y.j3ms.n@gmail.com/ [1] 52 52 | Link: https://rust-for-linux.zulipchat.com/#narrow/channel/288089-General/topic/Implement.20.60FromPrimitive.60.20trait.20.2B.20derive.20macro.20for.20nova-core/with/541971854 [2] 53 53 54 - Generic register abstraction [REGA] 55 - ----------------------------------- 56 - 57 - Work out how register constants and structures can be automatically generated 58 - through generalized macros. 59 - 60 - Example: 61 - 62 - .. code-block:: rust 63 - 64 - register!(BOOT0, 0x0, u32, pci::Bar<SIZE>, Fields [ 65 - MINOR_REVISION(3:0, RO), 66 - MAJOR_REVISION(7:4, RO), 67 - REVISION(7:0, RO), // Virtual register combining major and minor rev. 68 - ]) 69 - 70 - This could expand to something like: 71 - 72 - .. code-block:: rust 73 - 74 - const BOOT0_OFFSET: usize = 0x00000000; 75 - const BOOT0_MINOR_REVISION_SHIFT: u8 = 0; 76 - const BOOT0_MINOR_REVISION_MASK: u32 = 0x0000000f; 77 - const BOOT0_MAJOR_REVISION_SHIFT: u8 = 4; 78 - const BOOT0_MAJOR_REVISION_MASK: u32 = 0x000000f0; 79 - const BOOT0_REVISION_SHIFT: u8 = BOOT0_MINOR_REVISION_SHIFT; 80 - const BOOT0_REVISION_MASK: u32 = BOOT0_MINOR_REVISION_MASK | BOOT0_MAJOR_REVISION_MASK; 81 - 82 - struct Boot0(u32); 83 - 84 - impl Boot0 { 85 - #[inline] 86 - fn read(bar: &RevocableGuard<'_, pci::Bar<SIZE>>) -> Self { 87 - Self(bar.readl(BOOT0_OFFSET)) 88 - } 89 - 90 - #[inline] 91 - fn minor_revision(&self) -> u32 { 92 - (self.0 & BOOT0_MINOR_REVISION_MASK) >> BOOT0_MINOR_REVISION_SHIFT 93 - } 94 - 95 - #[inline] 96 - fn major_revision(&self) -> u32 { 97 - (self.0 & BOOT0_MAJOR_REVISION_MASK) >> BOOT0_MAJOR_REVISION_SHIFT 98 - } 99 - 100 - #[inline] 101 - fn revision(&self) -> u32 { 102 - (self.0 & BOOT0_REVISION_MASK) >> BOOT0_REVISION_SHIFT 103 - } 104 - } 105 - 106 - Usage: 107 - 108 - .. code-block:: rust 109 - 110 - let bar = bar.try_access().ok_or(ENXIO)?; 111 - 112 - let boot0 = Boot0::read(&bar); 113 - pr_info!("Revision: {}\n", boot0.revision()); 114 - 115 - A work-in-progress implementation currently resides in 116 - `drivers/gpu/nova-core/regs/macros.rs` and is used in nova-core. It would be 117 - nice to improve it (possibly using proc macros) and move it to the `kernel` 118 - crate so it can be used by other components as well. 119 - 120 - Features desired before this happens: 121 - 122 - * Make I/O optional I/O (for field values that are not registers), 123 - * Support other sizes than `u32`, 124 - * Allow visibility control for registers and individual fields, 125 - * Use Rust slice syntax to express fields ranges. 126 - 127 - | Complexity: Advanced 128 - | Contact: Alexandre Courbot 129 - 130 54 Numerical operations [NUMM] 131 55 --------------------------- 132 56