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drm/i915/cx0: Enable dpll framework for MTL+

MTL+ platforms are supported by dpll framework remove a separate
check for hw comparison and rely solely on dpll framework
hw comparison.

Finally, all required hooks are now in place so initialize
PLL manager for MTL+ platforms and remove the redirections
to the legacy code paths from the following interfaces:

* intel_encoder::clock_enable/disable()
* intel_encoder::get_config()
* intel_dpll_funcs::get_hw_state()
* intel_ddi_update_active_dpll()
* pipe_config_pll_mismatch()

v2: Rebase on !HAS_LT_PHY check in intel_ddi_update_active_dpll()
v3: Rebase on !display->dpll.mgr check in intel_ddi_update_active_dpll()
Add check for NVL as the platform is not part of pll framework (Suraj)

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20251118132859.2584452-1-mika.kahola@intel.com

Mika Kahola 1a7fad2a 2a6e4179

+6 -86
-10
drivers/gpu/drm/i915/display/intel_cx0_phy.c
··· 3432 3432 3433 3433 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 3434 3434 intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock); 3435 - else 3436 - /* TODO: remove when PLL mgr is in place. */ 3437 - intel_mtl_pll_enable(encoder, NULL, &crtc_state->dpll_hw_state); 3438 3435 } 3439 3436 3440 3437 /* ··· 3595 3598 3596 3599 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 3597 3600 intel_mtl_tbt_pll_disable_clock(encoder); 3598 - else 3599 - /* TODO: remove when PLL mgr is in place. */ 3600 - intel_mtl_pll_disable(encoder); 3601 3601 } 3602 3602 3603 3603 enum icl_port_dpll_id ··· 3622 3628 struct intel_cx0pll_state *pll_state) 3623 3629 { 3624 3630 memset(pll_state, 0, sizeof(*pll_state)); 3625 - 3626 - pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)); 3627 - if (pll_state->tbt_mode) 3628 - return true; 3629 3631 3630 3632 if (!intel_cx0_pll_is_enabled(encoder)) 3631 3633 return false;
+1 -22
drivers/gpu/drm/i915/display/intel_ddi.c
··· 4257 4257 intel_ddi_get_config(encoder, crtc_state); 4258 4258 } 4259 4259 4260 - static void mtl_ddi_get_config(struct intel_encoder *encoder, 4261 - struct intel_crtc_state *crtc_state) 4262 - { 4263 - intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); 4264 - 4265 - if (crtc_state->dpll_hw_state.cx0pll.tbt_mode) 4266 - crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 4267 - else 4268 - crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); 4269 - 4270 - intel_ddi_get_config(encoder, crtc_state); 4271 - } 4272 - 4273 4260 static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll) 4274 4261 { 4275 4262 return pll->info->id == DPLL_ID_ICL_TBTPLL; ··· 4303 4316 { 4304 4317 struct intel_display *display = to_intel_display(encoder); 4305 4318 4306 - /* TODO: Remove when the PLL manager is in place. */ 4307 - mtl_ddi_get_config(encoder, crtc_state); 4308 - return; 4309 - 4310 4319 mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT, 4311 4320 mtl_port_to_pll_id(display, encoder->port)); 4312 4321 } ··· 4311 4328 struct intel_crtc_state *crtc_state) 4312 4329 { 4313 4330 struct intel_display *display = to_intel_display(encoder); 4314 - 4315 - /* TODO: Remove when the PLL manager is in place. */ 4316 - mtl_ddi_get_config(encoder, crtc_state); 4317 - return; 4318 4331 4319 4332 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 4320 4333 mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT, ··· 5301 5322 } else if (DISPLAY_VER(display) >= 14) { 5302 5323 encoder->enable_clock = intel_mtl_pll_enable_clock; 5303 5324 encoder->disable_clock = intel_mtl_pll_disable_clock; 5304 - encoder->port_pll_type = intel_mtl_port_pll_type; 5325 + encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5305 5326 if (intel_encoder_is_tc(encoder)) 5306 5327 encoder->get_config = mtl_ddi_tc_phy_get_config; 5307 5328 else
-29
drivers/gpu/drm/i915/display/intel_display.c
··· 4977 4977 intel_dpll_dump_hw_state(display, p, b); 4978 4978 } 4979 4979 4980 - static void 4981 - pipe_config_cx0pll_mismatch(struct drm_printer *p, bool fastset, 4982 - const struct intel_crtc *crtc, 4983 - const char *name, 4984 - const struct intel_cx0pll_state *a, 4985 - const struct intel_cx0pll_state *b) 4986 - { 4987 - char *chipname = a->use_c10 ? "C10" : "C20"; 4988 - 4989 - pipe_config_mismatch(p, fastset, crtc, name, chipname); 4990 - 4991 - drm_printf(p, "expected:\n"); 4992 - intel_cx0pll_dump_hw_state(p, a); 4993 - drm_printf(p, "found:\n"); 4994 - intel_cx0pll_dump_hw_state(p, b); 4995 - } 4996 - 4997 4980 static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_state) 4998 4981 { 4999 4982 struct intel_display *display = to_intel_display(old_crtc_state); ··· 5124 5141 pipe_config_pll_mismatch(&p, fastset, crtc, __stringify(name), \ 5125 5142 &current_config->name, \ 5126 5143 &pipe_config->name); \ 5127 - ret = false; \ 5128 - } \ 5129 - } while (0) 5130 - 5131 - #define PIPE_CONF_CHECK_PLL_CX0(name) do { \ 5132 - if (!intel_cx0pll_compare_hw_state(&current_config->name, \ 5133 - &pipe_config->name)) { \ 5134 - pipe_config_cx0pll_mismatch(&p, fastset, crtc, __stringify(name), \ 5135 - &current_config->name, \ 5136 - &pipe_config->name); \ 5137 5144 ret = false; \ 5138 5145 } \ 5139 5146 } while (0) ··· 5367 5394 /* FIXME convert MTL+ platforms over to dpll_mgr */ 5368 5395 if (HAS_LT_PHY(display)) 5369 5396 PIPE_CONF_CHECK_PLL_LT(dpll_hw_state.ltpll); 5370 - else if (DISPLAY_VER(display) >= 14) 5371 - PIPE_CONF_CHECK_PLL_CX0(dpll_hw_state.cx0pll); 5372 5397 5373 5398 PIPE_CONF_CHECK_X(dsi_pll.ctrl); 5374 5399 PIPE_CONF_CHECK_X(dsi_pll.div);
+1 -22
drivers/gpu/drm/i915/display/intel_dpll.c
··· 1212 1212 return 0; 1213 1213 } 1214 1214 1215 - static int mtl_crtc_compute_clock(struct intel_atomic_state *state, 1216 - struct intel_crtc *crtc) 1217 - { 1218 - struct intel_crtc_state *crtc_state = 1219 - intel_atomic_get_new_crtc_state(state, crtc); 1220 - struct intel_encoder *encoder = 1221 - intel_get_crtc_new_encoder(state, crtc_state); 1222 - int ret; 1223 - 1224 - ret = intel_cx0pll_calc_state(crtc_state, encoder, &crtc_state->dpll_hw_state); 1225 - if (ret) 1226 - return ret; 1227 - 1228 - /* TODO: Do the readback via intel_dpll_compute() */ 1229 - crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); 1230 - 1231 - crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); 1232 - 1233 - return 0; 1234 - } 1235 - 1236 1215 static int xe3plpd_crtc_compute_clock(struct intel_atomic_state *state, 1237 1216 struct intel_crtc *crtc) 1238 1217 { ··· 1698 1719 }; 1699 1720 1700 1721 static const struct intel_dpll_global_funcs mtl_dpll_funcs = { 1701 - .crtc_compute_clock = mtl_crtc_compute_clock, 1722 + .crtc_compute_clock = hsw_crtc_compute_clock, 1702 1723 .crtc_get_dpll = hsw_crtc_get_dpll, 1703 1724 }; 1704 1725
+4 -3
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
··· 4558 4558 return intel_cx0pll_compare_hw_state(a, b); 4559 4559 } 4560 4560 4561 - __maybe_unused 4562 4561 static const struct intel_dpll_mgr mtl_pll_mgr = { 4563 4562 .dpll_info = mtl_plls, 4564 4563 .compute_dplls = mtl_compute_dplls, ··· 4583 4584 4584 4585 mutex_init(&display->dpll.lock); 4585 4586 4586 - if (DISPLAY_VER(display) >= 14 || display->platform.dg2) 4587 - /* No shared DPLLs on DG2; port PLLs are part of the PHY */ 4587 + if (DISPLAY_VER(display) >= 35 || display->platform.dg2) 4588 + /* No shared DPLLs on NVL or DG2; port PLLs are part of the PHY */ 4588 4589 dpll_mgr = NULL; 4590 + else if (DISPLAY_VER(display) >= 14) 4591 + dpll_mgr = &mtl_pll_mgr; 4589 4592 else if (display->platform.alderlake_p) 4590 4593 dpll_mgr = &adlp_pll_mgr; 4591 4594 else if (display->platform.alderlake_s)