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drm/i915/cx0: Add MTL+ Thunderbolt PLL hooks

Add the PLL hooks for the TBT PLL on MTL+. These are simple stubs
similarly to the TBT PLL on earlier platforms, since this PLL is always
on from the display POV - so no PLL enable/disable programming is
required as opposed to the non-TBT PLLs - and the clocks for different
link rates are enabled/disabled at a different level, via the
intel_encoder::enable_clock()/disable_clock() interface.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20251117104602.2363671-32-mika.kahola@intel.com

authored by

Imre Deak and committed by
Mika Kahola 2a6e4179 6b566d06

+59 -2
+18
drivers/gpu/drm/i915/display/intel_cx0_phy.c
··· 3283 3283 intel_cx0_phy_transaction_end(encoder, wakeref); 3284 3284 } 3285 3285 3286 + void intel_mtl_tbt_pll_calc_state(struct intel_dpll_hw_state *hw_state) 3287 + { 3288 + memset(hw_state, 0, sizeof(*hw_state)); 3289 + 3290 + hw_state->cx0pll.tbt_mode = true; 3291 + } 3292 + 3293 + bool intel_mtl_tbt_pll_readout_hw_state(struct intel_display *display, 3294 + struct intel_dpll *pll, 3295 + struct intel_dpll_hw_state *hw_state) 3296 + { 3297 + memset(hw_state, 0, sizeof(*hw_state)); 3298 + 3299 + hw_state->cx0pll.tbt_mode = true; 3300 + 3301 + return true; 3302 + } 3303 + 3286 3304 int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder) 3287 3305 { 3288 3306 struct intel_display *display = to_intel_display(encoder);
+6
drivers/gpu/drm/i915/display/intel_cx0_phy.h
··· 70 70 int intel_cx0_wait_for_ack(struct intel_encoder *encoder, 71 71 int command, int lane, u32 *val); 72 72 void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane); 73 + 74 + void intel_mtl_tbt_pll_calc_state(struct intel_dpll_hw_state *hw_state); 75 + bool intel_mtl_tbt_pll_readout_hw_state(struct intel_display *display, 76 + struct intel_dpll *pll, 77 + struct intel_dpll_hw_state *hw_state); 73 78 int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder); 79 + 74 80 void intel_cx0_pll_power_save_wa(struct intel_display *display); 75 81 void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder, 76 82 const struct intel_crtc_state *crtc_state);
+35 -2
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
··· 4421 4421 .get_freq = mtl_pll_get_freq, 4422 4422 }; 4423 4423 4424 + static void mtl_tbt_pll_enable(struct intel_display *display, 4425 + struct intel_dpll *pll, 4426 + const struct intel_dpll_hw_state *hw_state) 4427 + { 4428 + } 4429 + 4430 + static void mtl_tbt_pll_disable(struct intel_display *display, 4431 + struct intel_dpll *pll) 4432 + { 4433 + } 4434 + 4435 + static int mtl_tbt_pll_get_freq(struct intel_display *display, 4436 + const struct intel_dpll *pll, 4437 + const struct intel_dpll_hw_state *dpll_hw_state) 4438 + { 4439 + /* 4440 + * The PLL outputs multiple frequencies at the same time, selection is 4441 + * made at DDI clock mux level. 4442 + */ 4443 + drm_WARN_ON(display->drm, 1); 4444 + 4445 + return 0; 4446 + } 4447 + 4448 + static const struct intel_dpll_funcs mtl_tbt_pll_funcs = { 4449 + .enable = mtl_tbt_pll_enable, 4450 + .disable = mtl_tbt_pll_disable, 4451 + .get_hw_state = intel_mtl_tbt_pll_readout_hw_state, 4452 + .get_freq = mtl_tbt_pll_get_freq, 4453 + }; 4454 + 4424 4455 static const struct dpll_info mtl_plls[] = { 4425 4456 { .name = "DPLL 0", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_DPLL0, }, 4426 4457 { .name = "DPLL 1", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_DPLL1, }, 4427 - /* TODO: Add TBT PLL */ 4458 + { .name = "TBT PLL", .funcs = &mtl_tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, 4459 + .is_alt_port_dpll = true, .always_on = true }, 4428 4460 { .name = "TC PLL 1", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, }, 4429 4461 { .name = "TC PLL 2", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, }, 4430 4462 { .name = "TC PLL 3", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, }, ··· 4502 4470 struct icl_port_dpll *port_dpll; 4503 4471 int ret; 4504 4472 4505 - /* TODO: Add state calculation for TBT PLL */ 4473 + port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; 4474 + intel_mtl_tbt_pll_calc_state(&port_dpll->hw_state); 4506 4475 4507 4476 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY]; 4508 4477 ret = intel_cx0pll_calc_state(crtc_state, encoder, &port_dpll->hw_state);