Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
gpu: nova-core: convert FUSE registers to kernel register macro
Convert all FUSE registers to use the kernel's register macro and update
the code accordingly.
Reviewed-by: Eliot Courtney <ecourtney@nvidia.com>
Reviewed-by: Gary Guo <gary@garyguo.net>
Acked-by: Danilo Krummrich <dakr@kernel.org>
Link: https://patch.msgid.link/20260325-b4-nova-register-v4-6-bdf172f0f6ca@nvidia.com
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
+41
-22
+12
-5
drivers/gpu/nova-core/falcon/hal/ga102.rs
+12
-5
drivers/gpu/nova-core/falcon/hal/ga102.rs
···
4
4
5
5
use kernel::{
6
6
device,
7
-
io::poll::read_poll_timeout,
7
+
io::{
8
+
poll::read_poll_timeout,
9
+
register::Array,
10
+
Io, //
11
+
},
8
12
prelude::*,
9
13
time::Delta, //
10
14
};
···
64
60
65
61
// `ucode_idx` is guaranteed to be in the range [0..15], making the `read` calls provable valid
66
62
// at build-time.
67
-
let reg_fuse_version = if engine_id_mask & 0x0001 != 0 {
68
-
regs::NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION::read(bar, ucode_idx).data()
63
+
let reg_fuse_version: u16 = if engine_id_mask & 0x0001 != 0 {
64
+
bar.read(regs::NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION::at(ucode_idx))
65
+
.data()
69
66
} else if engine_id_mask & 0x0004 != 0 {
70
-
regs::NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION::read(bar, ucode_idx).data()
67
+
bar.read(regs::NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION::at(ucode_idx))
68
+
.data()
71
69
} else if engine_id_mask & 0x0400 != 0 {
72
-
regs::NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION::read(bar, ucode_idx).data()
70
+
bar.read(regs::NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION::at(ucode_idx))
71
+
.data()
73
72
} else {
74
73
dev_err!(dev, "unexpected engine_id_mask {:#x}\n", engine_id_mask);
75
74
return Err(EINVAL);
+2
-1
drivers/gpu/nova-core/fb/hal/ga100.rs
+2
-1
drivers/gpu/nova-core/fb/hal/ga100.rs
···
40
40
}
41
41
42
42
pub(super) fn display_enabled_ga100(bar: &Bar0) -> bool {
43
-
!regs::ga100::NV_FUSE_STATUS_OPT_DISPLAY::read(bar).display_disabled()
43
+
!bar.read(regs::ga100::NV_FUSE_STATUS_OPT_DISPLAY)
44
+
.display_disabled()
44
45
}
45
46
46
47
/// Shift applied to the sysmem address before it is written into
+2
-1
drivers/gpu/nova-core/fb/hal/tu102.rs
+2
-1
drivers/gpu/nova-core/fb/hal/tu102.rs
···
29
29
}
30
30
31
31
pub(super) fn display_enabled_gm107(bar: &Bar0) -> bool {
32
-
!regs::gm107::NV_FUSE_STATUS_OPT_DISPLAY::read(bar).display_disabled()
32
+
!bar.read(regs::gm107::NV_FUSE_STATUS_OPT_DISPLAY)
33
+
.display_disabled()
33
34
}
34
35
35
36
pub(super) fn vidmem_size_gp102(bar: &Bar0) -> u64 {
+25
-15
drivers/gpu/nova-core/regs.rs
+25
-15
drivers/gpu/nova-core/regs.rs
···
270
270
271
271
pub(crate) const NV_FUSE_OPT_FPF_SIZE: usize = 16;
272
272
273
-
register!(NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION @ 0x00824100[NV_FUSE_OPT_FPF_SIZE] {
274
-
15:0 data as u16;
275
-
});
273
+
io::register! {
274
+
pub(crate) NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION(u32)[NV_FUSE_OPT_FPF_SIZE] @ 0x00824100 {
275
+
15:0 data => u16;
276
+
}
276
277
277
-
register!(NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION @ 0x00824140[NV_FUSE_OPT_FPF_SIZE] {
278
-
15:0 data as u16;
279
-
});
278
+
pub(crate) NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION(u32)[NV_FUSE_OPT_FPF_SIZE] @ 0x00824140 {
279
+
15:0 data => u16;
280
+
}
280
281
281
-
register!(NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION @ 0x008241c0[NV_FUSE_OPT_FPF_SIZE] {
282
-
15:0 data as u16;
283
-
});
282
+
pub(crate) NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION(u32)[NV_FUSE_OPT_FPF_SIZE] @ 0x008241c0 {
283
+
15:0 data => u16;
284
+
}
285
+
}
284
286
285
287
// PFALCON
286
288
···
493
491
// only be used in HAL modules.
494
492
495
493
pub(crate) mod gm107 {
494
+
use kernel::io;
495
+
496
496
// FUSE
497
497
498
-
register!(NV_FUSE_STATUS_OPT_DISPLAY @ 0x00021c04 {
499
-
0:0 display_disabled as bool;
500
-
});
498
+
io::register! {
499
+
pub(crate) NV_FUSE_STATUS_OPT_DISPLAY(u32) @ 0x00021c04 {
500
+
0:0 display_disabled => bool;
501
+
}
502
+
}
501
503
}
502
504
503
505
pub(crate) mod ga100 {
506
+
use kernel::io;
507
+
504
508
// FUSE
505
509
506
-
register!(NV_FUSE_STATUS_OPT_DISPLAY @ 0x00820c04 {
507
-
0:0 display_disabled as bool;
508
-
});
510
+
io::register! {
511
+
pub(crate) NV_FUSE_STATUS_OPT_DISPLAY(u32) @ 0x00820c04 {
512
+
0:0 display_disabled => bool;
513
+
}
514
+
}
509
515
}