gpu: nova-core: convert GC6 registers to kernel register macro

+5 -2

drivers/gpu/nova-core/falcon/gsp.rs

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 3 3 use kernel::{ 4 - io::poll::read_poll_timeout, 4 + io::{ 5 + poll::read_poll_timeout, 6 + Io, // 7 + }, 5 8 prelude::*, 6 9 time::Delta, // 7 10 }; ··· 50 47 /// Checks if GSP reload/resume has completed during the boot process. 51 48 pub(crate) fn check_reload_completed(&self, bar: &Bar0, timeout: Delta) -> Result<bool> { 52 49 read_poll_timeout( 53 - || Ok(regs::NV_PGC6_BSI_SECURE_SCRATCH_14::read(bar)), 50 + || Ok(bar.read(regs::NV_PGC6_BSI_SECURE_SCRATCH_14)), 54 51 |val| val.boot_stage_3_handoff(), 55 52 Delta::ZERO, 56 53 timeout,

+5 -2

drivers/gpu/nova-core/fb/hal/ga102.rs

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 3 - use kernel::prelude::*; 3 + use kernel::{ 4 + io::Io, 5 + prelude::*, // 6 + }; 4 7 5 8 use crate::{ 6 9 driver::Bar0, ··· 12 9 }; 13 10 14 11 fn vidmem_size_ga102(bar: &Bar0) -> u64 { 15 - regs::NV_USABLE_FB_SIZE_IN_MB::read(bar).usable_fb_size() 12 + bar.read(regs::NV_USABLE_FB_SIZE_IN_MB).usable_fb_size() 16 13 } 17 14 18 15 struct Ga102;

+8 -3

drivers/gpu/nova-core/gfw.rs

··· 19 19 //! Note that the devinit sequence also needs to run during suspend/resume. 20 20 21 21 use kernel::{ 22 - io::poll::read_poll_timeout, 22 + io::{ 23 + poll::read_poll_timeout, 24 + Io, // 25 + }, 23 26 prelude::*, 24 27 time::Delta, // 25 28 }; ··· 61 58 Ok( 62 59 // Check that FWSEC has lowered its protection level before reading the GFW_BOOT 63 60 // status. 64 - regs::NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK::read(bar) 61 + bar.read(regs::NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK) 65 62 .read_protection_level0() 66 - && regs::NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT::read(bar).completed(), 63 + && bar 64 + .read(regs::NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT) 65 + .completed(), 67 66 ) 68 67 }, 69 68 |&gfw_booted| gfw_booted,

+34 -33

drivers/gpu/nova-core/regs.rs

··· 198 198 // These scratch registers remain powered on even in a low-power state and have a designated group 199 199 // number. 200 200 201 - // Boot Sequence Interface (BSI) register used to determine 202 - // if GSP reload/resume has completed during the boot process. 203 - register!(NV_PGC6_BSI_SECURE_SCRATCH_14 @ 0x001180f8 { 204 - 26:26 boot_stage_3_handoff as bool; 205 - }); 206 - 207 - // Privilege level mask register. It dictates whether the host CPU has privilege to access the 208 - // `PGC6_AON_SECURE_SCRATCH_GROUP_05` register (which it needs to read GFW_BOOT). 209 - register!(NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK @ 0x00118128, 210 - "Privilege level mask register" { 211 - 0:0 read_protection_level0 as bool, "Set after FWSEC lowers its protection level"; 212 - }); 213 - 214 - // OpenRM defines this as a register array, but doesn't specify its size and only uses its first 215 - // element. Be conservative until we know the actual size or need to use more registers. 216 - register!(NV_PGC6_AON_SECURE_SCRATCH_GROUP_05 @ 0x00118234[1] {}); 217 - 218 - register!( 219 - NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT => NV_PGC6_AON_SECURE_SCRATCH_GROUP_05[0], 220 - "Scratch group 05 register 0 used as GFW boot progress indicator" { 221 - 7:0 progress as u8, "Progress of GFW boot (0xff means completed)"; 201 + io::register! { 202 + /// Boot Sequence Interface (BSI) register used to determine 203 + /// if GSP reload/resume has completed during the boot process. 204 + pub(crate) NV_PGC6_BSI_SECURE_SCRATCH_14(u32) @ 0x001180f8 { 205 + 26:26 boot_stage_3_handoff => bool; 222 206 } 223 - ); 207 + 208 + /// Privilege level mask register. It dictates whether the host CPU has privilege to access the 209 + /// `PGC6_AON_SECURE_SCRATCH_GROUP_05` register (which it needs to read GFW_BOOT). 210 + pub(crate) NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK(u32) @ 0x00118128 { 211 + /// Set after FWSEC lowers its protection level. 212 + 0:0 read_protection_level0 => bool; 213 + } 214 + 215 + /// OpenRM defines this as a register array, but doesn't specify its size and only uses its 216 + /// first element. Be conservative until we know the actual size or need to use more registers. 217 + pub(crate) NV_PGC6_AON_SECURE_SCRATCH_GROUP_05(u32)[1] @ 0x00118234 {} 218 + 219 + /// Scratch group 05 register 0 used as GFW boot progress indicator. 220 + pub(crate) NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT(u32) 221 + => NV_PGC6_AON_SECURE_SCRATCH_GROUP_05[0] { 222 + /// Progress of GFW boot (0xff means completed). 223 + 7:0 progress; 224 + } 225 + 226 + pub(crate) NV_PGC6_AON_SECURE_SCRATCH_GROUP_42(u32) @ 0x001183a4 { 227 + 31:0 value; 228 + } 229 + 230 + /// Scratch group 42 register used as framebuffer size. 231 + pub(crate) NV_USABLE_FB_SIZE_IN_MB(u32) => NV_PGC6_AON_SECURE_SCRATCH_GROUP_42 { 232 + /// Usable framebuffer size, in megabytes. 233 + 31:0 value; 234 + } 235 + } 224 236 225 237 impl NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT { 226 238 /// Returns `true` if GFW boot is completed. ··· 240 228 self.progress() == 0xff 241 229 } 242 230 } 243 - 244 - register!(NV_PGC6_AON_SECURE_SCRATCH_GROUP_42 @ 0x001183a4 { 245 - 31:0 value as u32; 246 - }); 247 - 248 - register!( 249 - NV_USABLE_FB_SIZE_IN_MB => NV_PGC6_AON_SECURE_SCRATCH_GROUP_42, 250 - "Scratch group 42 register used as framebuffer size" { 251 - 31:0 value as u32, "Usable framebuffer size, in megabytes"; 252 - } 253 - ); 254 231 255 232 impl NV_USABLE_FB_SIZE_IN_MB { 256 233 /// Returns the usable framebuffer size, in bytes.

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