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spi: sh-msiof: Correct RX FIFO size for R-Car Gen2

According to Renesas Technical Updates TN-RCS-S068A/E, the MSIOF receive
FIFOs on R-Car Gen2 SoCs have room for 128 words of 32 bits.

Note that this change has no actual impact on the behavior of the
driver, as SPI_CONTROLLER_MUST_TX is set, and transfer size is currenty
limited to the minimum of the transmit and receive FIFO sizes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/fd11933f932df81d84f417a21e2179bd4fdcfdc1.1747401908.git.geert+renesas@glider.be
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Geert Uytterhoeven and committed by
Mark Brown 1ab2c8c4 955f7ce6

+1 -1
+1 -1
drivers/spi/spi-sh-msiof.c
··· 1099 1099 .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) | 1100 1100 SPI_BPW_MASK(24) | SPI_BPW_MASK(32), 1101 1101 .tx_fifo_size = 64, 1102 - .rx_fifo_size = 64, 1102 + .rx_fifo_size = 128, 1103 1103 .ctlr_flags = SPI_CONTROLLER_MUST_TX, 1104 1104 .min_div_pow = 0, 1105 1105 };