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spi: sh-msiof: Add core support for dual-group transfers

All MSIOF variants support transferring data of multiple (2 or 4)
groups. Add definitions for the register bits related to multiple
groups, and enhance sh_msiof_spi_set_mode_regs() to accept a second
group size.

For now the second group is unused.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/be75e20cfcd2a6c0d73ab09e0126f902911adc69.1747401908.git.geert+renesas@glider.be
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Geert Uytterhoeven and committed by
Mark Brown 955f7ce6 acedbff0

+20 -5
+20 -5
drivers/spi/spi-sh-msiof.c
··· 100 100 /* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */ 101 101 102 102 /* SITMDR2 and SIRMDR2 */ 103 + #define SIMDR2_GRP GENMASK(31, 30) /* Group Count */ 103 104 #define SIMDR2_BITLEN1 GENMASK(28, 24) /* Data Size (8-32 bits) */ 104 105 #define SIMDR2_WDLEN1 GENMASK(23, 16) /* Word Count (1-64/256 (SH, A1))) */ 105 106 #define SIMDR2_GRPMASK GENMASK(3, 0) /* Group Output Mask 1-4 (SH, A1) */ 107 + 108 + /* SITMDR3 and SIRMDR3 */ 109 + #define SIMDR3_BITLEN2 GENMASK(28, 24) /* Data Size (8-32 bits) */ 110 + #define SIMDR3_WDLEN2 GENMASK(23, 16) /* Word Count (1-64/256 (SH, A1))) */ 106 111 107 112 /* SITSCR and SIRSCR */ 108 113 #define SISCR_BRPS GENMASK(12, 8) /* Prescaler Setting (1-32) */ ··· 397 392 398 393 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p, 399 394 const void *tx_buf, void *rx_buf, 400 - u32 bits, u32 words) 395 + u32 bits, u32 words1, u32 words2) 401 396 { 402 - u32 dr2 = FIELD_PREP(SIMDR2_BITLEN1, bits - 1) | 403 - FIELD_PREP(SIMDR2_WDLEN1, words - 1); 397 + u32 dr2 = FIELD_PREP(SIMDR2_GRP, words2 ? 1 : 0) | 398 + FIELD_PREP(SIMDR2_BITLEN1, bits - 1) | 399 + FIELD_PREP(SIMDR2_WDLEN1, words1 - 1); 404 400 405 401 if (tx_buf || (p->ctlr->flags & SPI_CONTROLLER_MUST_TX)) 406 402 sh_msiof_write(p, SITMDR2, dr2); ··· 410 404 411 405 if (rx_buf) 412 406 sh_msiof_write(p, SIRMDR2, dr2); 407 + 408 + if (words2) { 409 + u32 dr3 = FIELD_PREP(SIMDR3_BITLEN2, bits - 1) | 410 + FIELD_PREP(SIMDR3_WDLEN2, words2 - 1); 411 + 412 + sh_msiof_write(p, SITMDR3, dr3); 413 + if (rx_buf) 414 + sh_msiof_write(p, SIRMDR3, dr3); 415 + } 413 416 } 414 417 415 418 static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p) ··· 727 712 sh_msiof_write(p, SIFCTR, 0); 728 713 729 714 /* setup msiof transfer mode registers */ 730 - sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words); 715 + sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words, 0); 731 716 sh_msiof_write(p, SIIER, SIIER_TEOFE | SIIER_REOFE); 732 717 733 718 /* write tx fifo */ ··· 827 812 FIELD_PREP(SIFCTR_RFWM, SIFCTR_RFWM_1)); 828 813 829 814 /* setup msiof transfer mode registers (32-bit words) */ 830 - sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4); 815 + sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4, 0); 831 816 832 817 sh_msiof_write(p, SIIER, ier_bits); 833 818