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arm64: dts: qcom: sa8775p: add missing spi nodes

Add the missing nodes of the SPI buses present on sa8775p platform.

Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526133122.16443-4-quic_shazhuss@quicinc.com

authored by

Shazad Hussain and committed by
Bjorn Andersson 1b2d7ad5 ee2f5f90

+399
+399
arch/arm64/boot/dts/qcom/sa8775p.dtsi
··· 511 511 status = "disabled"; 512 512 }; 513 513 514 + spi14: spi@880000 { 515 + compatible = "qcom,geni-spi"; 516 + reg = <0x0 0x880000 0x0 0x4000>; 517 + #address-cells = <1>; 518 + #size-cells = <0>; 519 + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 520 + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 521 + clock-names = "se"; 522 + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 523 + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 524 + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 525 + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 526 + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 527 + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 528 + interconnect-names = "qup-core", 529 + "qup-config", 530 + "qup-memory"; 531 + power-domains = <&rpmhpd SA8775P_CX>; 532 + status = "disabled"; 533 + }; 534 + 514 535 i2c15: i2c@884000 { 515 536 compatible = "qcom,geni-i2c"; 537 + reg = <0x0 0x884000 0x0 0x4000>; 538 + #address-cells = <1>; 539 + #size-cells = <0>; 540 + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 541 + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 542 + clock-names = "se"; 543 + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 544 + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 545 + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 546 + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 547 + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 548 + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 549 + interconnect-names = "qup-core", 550 + "qup-config", 551 + "qup-memory"; 552 + power-domains = <&rpmhpd SA8775P_CX>; 553 + status = "disabled"; 554 + }; 555 + 556 + spi15: spi@884000 { 557 + compatible = "qcom,geni-spi"; 516 558 reg = <0x0 0x884000 0x0 0x4000>; 517 559 #address-cells = <1>; 518 560 #size-cells = <0>; ··· 637 595 status = "disabled"; 638 596 }; 639 597 598 + spi17: spi@88c000 { 599 + compatible = "qcom,geni-spi"; 600 + reg = <0x0 0x88c000 0x0 0x4000>; 601 + #address-cells = <1>; 602 + #size-cells = <0>; 603 + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 604 + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 605 + clock-names = "se"; 606 + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 607 + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 608 + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 609 + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 610 + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 611 + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 612 + interconnect-names = "qup-core", 613 + "qup-config", 614 + "qup-memory"; 615 + power-domains = <&rpmhpd SA8775P_CX>; 616 + status = "disabled"; 617 + }; 618 + 640 619 uart17: serial@88c000 { 641 620 compatible = "qcom,geni-uart"; 642 621 reg = <0x0 0x0088c000 0x0 0x4000>; ··· 694 631 status = "disabled"; 695 632 }; 696 633 634 + spi18: spi@890000 { 635 + compatible = "qcom,geni-spi"; 636 + reg = <0x0 0x890000 0x0 0x4000>; 637 + #address-cells = <1>; 638 + #size-cells = <0>; 639 + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 640 + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 641 + clock-names = "se"; 642 + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 643 + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 644 + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 645 + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 646 + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 647 + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 648 + interconnect-names = "qup-core", 649 + "qup-config", 650 + "qup-memory"; 651 + power-domains = <&rpmhpd SA8775P_CX>; 652 + status = "disabled"; 653 + }; 654 + 697 655 i2c19: i2c@894000 { 698 656 compatible = "qcom,geni-i2c"; 699 657 reg = <0x0 0x894000 0x0 0x4000>; ··· 736 652 status = "disabled"; 737 653 }; 738 654 655 + spi19: spi@894000 { 656 + compatible = "qcom,geni-spi"; 657 + reg = <0x0 0x894000 0x0 0x4000>; 658 + #address-cells = <1>; 659 + #size-cells = <0>; 660 + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 661 + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 662 + clock-names = "se"; 663 + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 664 + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 665 + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 666 + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 667 + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 668 + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 669 + interconnect-names = "qup-core", 670 + "qup-config", 671 + "qup-memory"; 672 + power-domains = <&rpmhpd SA8775P_CX>; 673 + status = "disabled"; 674 + }; 675 + 739 676 i2c20: i2c@898000 { 740 677 compatible = "qcom,geni-i2c"; 678 + reg = <0x0 0x898000 0x0 0x4000>; 679 + #address-cells = <1>; 680 + #size-cells = <0>; 681 + interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 682 + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 683 + clock-names = "se"; 684 + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 685 + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 686 + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 687 + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 688 + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 689 + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 690 + interconnect-names = "qup-core", 691 + "qup-config", 692 + "qup-memory"; 693 + power-domains = <&rpmhpd SA8775P_CX>; 694 + status = "disabled"; 695 + }; 696 + 697 + spi20: spi@898000 { 698 + compatible = "qcom,geni-spi"; 741 699 reg = <0x0 0x898000 0x0 0x4000>; 742 700 #address-cells = <1>; 743 701 #size-cells = <0>; ··· 833 707 status = "disabled"; 834 708 }; 835 709 710 + spi0: spi@980000 { 711 + compatible = "qcom,geni-spi"; 712 + reg = <0x0 0x980000 0x0 0x4000>; 713 + #address-cells = <1>; 714 + #size-cells = <0>; 715 + interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 716 + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 717 + clock-names = "se"; 718 + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 719 + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 720 + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 721 + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 722 + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 723 + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 724 + interconnect-names = "qup-core", 725 + "qup-config", 726 + "qup-memory"; 727 + power-domains = <&rpmhpd SA8775P_CX>; 728 + status = "disabled"; 729 + }; 730 + 836 731 i2c1: i2c@984000 { 837 732 compatible = "qcom,geni-i2c"; 733 + reg = <0x0 0x984000 0x0 0x4000>; 734 + #address-cells = <1>; 735 + #size-cells = <0>; 736 + interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 737 + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 738 + clock-names = "se"; 739 + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 740 + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 741 + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 742 + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 743 + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 744 + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 745 + interconnect-names = "qup-core", 746 + "qup-config", 747 + "qup-memory"; 748 + power-domains = <&rpmhpd SA8775P_CX>; 749 + status = "disabled"; 750 + }; 751 + 752 + spi1: spi@984000 { 753 + compatible = "qcom,geni-spi"; 838 754 reg = <0x0 0x984000 0x0 0x4000>; 839 755 #address-cells = <1>; 840 756 #size-cells = <0>; ··· 917 749 status = "disabled"; 918 750 }; 919 751 752 + spi2: spi@988000 { 753 + compatible = "qcom,geni-spi"; 754 + reg = <0x0 0x988000 0x0 0x4000>; 755 + #address-cells = <1>; 756 + #size-cells = <0>; 757 + interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 758 + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 759 + clock-names = "se"; 760 + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 761 + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 762 + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 763 + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 764 + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 765 + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 766 + interconnect-names = "qup-core", 767 + "qup-config", 768 + "qup-memory"; 769 + power-domains = <&rpmhpd SA8775P_CX>; 770 + status = "disabled"; 771 + }; 772 + 920 773 i2c3: i2c@98c000 { 921 774 compatible = "qcom,geni-i2c"; 775 + reg = <0x0 0x98c000 0x0 0x4000>; 776 + #address-cells = <1>; 777 + #size-cells = <0>; 778 + interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 779 + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 780 + clock-names = "se"; 781 + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 782 + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 783 + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 784 + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 785 + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 786 + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 787 + interconnect-names = "qup-core", 788 + "qup-config", 789 + "qup-memory"; 790 + power-domains = <&rpmhpd SA8775P_CX>; 791 + status = "disabled"; 792 + }; 793 + 794 + spi3: spi@98c000 { 795 + compatible = "qcom,geni-spi"; 922 796 reg = <0x0 0x98c000 0x0 0x4000>; 923 797 #address-cells = <1>; 924 798 #size-cells = <0>; ··· 1001 791 status = "disabled"; 1002 792 }; 1003 793 794 + spi4: spi@990000 { 795 + compatible = "qcom,geni-spi"; 796 + reg = <0x0 0x990000 0x0 0x4000>; 797 + #address-cells = <1>; 798 + #size-cells = <0>; 799 + interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 800 + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 801 + clock-names = "se"; 802 + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 803 + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 804 + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 805 + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 806 + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 807 + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 808 + interconnect-names = "qup-core", 809 + "qup-config", 810 + "qup-memory"; 811 + power-domains = <&rpmhpd SA8775P_CX>; 812 + status = "disabled"; 813 + }; 814 + 1004 815 i2c5: i2c@994000 { 1005 816 compatible = "qcom,geni-i2c"; 817 + reg = <0x0 0x994000 0x0 0x4000>; 818 + #address-cells = <1>; 819 + #size-cells = <0>; 820 + interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 821 + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 822 + clock-names = "se"; 823 + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 824 + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 825 + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 826 + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 827 + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 828 + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 829 + interconnect-names = "qup-core", 830 + "qup-config", 831 + "qup-memory"; 832 + power-domains = <&rpmhpd SA8775P_CX>; 833 + status = "disabled"; 834 + }; 835 + 836 + spi5: spi@994000 { 837 + compatible = "qcom,geni-spi"; 1006 838 reg = <0x0 0x994000 0x0 0x4000>; 1007 839 #address-cells = <1>; 1008 840 #size-cells = <0>; ··· 1098 846 status = "disabled"; 1099 847 }; 1100 848 849 + spi7: spi@a80000 { 850 + compatible = "qcom,geni-spi"; 851 + reg = <0x0 0xa80000 0x0 0x4000>; 852 + #address-cells = <1>; 853 + #size-cells = <0>; 854 + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 855 + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 856 + clock-names = "se"; 857 + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 858 + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 859 + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 860 + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 861 + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 862 + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 863 + interconnect-names = "qup-core", 864 + "qup-config", 865 + "qup-memory"; 866 + power-domains = <&rpmhpd SA8775P_CX>; 867 + status = "disabled"; 868 + }; 869 + 1101 870 i2c8: i2c@a84000 { 1102 871 compatible = "qcom,geni-i2c"; 872 + reg = <0x0 0xa84000 0x0 0x4000>; 873 + #address-cells = <1>; 874 + #size-cells = <0>; 875 + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 876 + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 877 + clock-names = "se"; 878 + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 879 + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 880 + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 881 + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 882 + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 883 + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 884 + interconnect-names = "qup-core", 885 + "qup-config", 886 + "qup-memory"; 887 + power-domains = <&rpmhpd SA8775P_CX>; 888 + status = "disabled"; 889 + }; 890 + 891 + spi8: spi@a84000 { 892 + compatible = "qcom,geni-spi"; 1103 893 reg = <0x0 0xa84000 0x0 0x4000>; 1104 894 #address-cells = <1>; 1105 895 #size-cells = <0>; ··· 1182 888 status = "disabled"; 1183 889 }; 1184 890 891 + spi9: spi@a88000 { 892 + compatible = "qcom,geni-spi"; 893 + reg = <0x0 0xa88000 0x0 0x4000>; 894 + #address-cells = <1>; 895 + #size-cells = <0>; 896 + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 897 + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 898 + clock-names = "se"; 899 + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 900 + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 901 + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 902 + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 903 + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 904 + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 905 + interconnect-names = "qup-core", 906 + "qup-config", 907 + "qup-memory"; 908 + power-domains = <&rpmhpd SA8775P_CX>; 909 + status = "disabled"; 910 + }; 911 + 1185 912 i2c10: i2c@a8c000 { 1186 913 compatible = "qcom,geni-i2c"; 914 + reg = <0x0 0xa8c000 0x0 0x4000>; 915 + #address-cells = <1>; 916 + #size-cells = <0>; 917 + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 918 + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 919 + clock-names = "se"; 920 + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 921 + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 922 + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 923 + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 924 + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 925 + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 926 + interconnect-names = "qup-core", 927 + "qup-config", 928 + "qup-memory"; 929 + power-domains = <&rpmhpd SA8775P_CX>; 930 + status = "disabled"; 931 + }; 932 + 933 + spi10: spi@a8c000 { 934 + compatible = "qcom,geni-spi"; 1187 935 reg = <0x0 0xa8c000 0x0 0x4000>; 1188 936 #address-cells = <1>; 1189 937 #size-cells = <0>; ··· 1282 946 status = "disabled"; 1283 947 }; 1284 948 949 + spi11: spi@a90000 { 950 + compatible = "qcom,geni-spi"; 951 + reg = <0x0 0xa90000 0x0 0x4000>; 952 + #address-cells = <1>; 953 + #size-cells = <0>; 954 + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 955 + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 956 + clock-names = "se"; 957 + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 958 + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 959 + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 960 + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 961 + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 962 + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 963 + interconnect-names = "qup-core", 964 + "qup-config", 965 + "qup-memory"; 966 + power-domains = <&rpmhpd SA8775P_CX>; 967 + status = "disabled"; 968 + }; 969 + 1285 970 i2c12: i2c@a94000 { 1286 971 compatible = "qcom,geni-i2c"; 972 + reg = <0x0 0xa94000 0x0 0x4000>; 973 + #address-cells = <1>; 974 + #size-cells = <0>; 975 + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 976 + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 977 + clock-names = "se"; 978 + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 979 + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 980 + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 981 + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 982 + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 983 + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 984 + interconnect-names = "qup-core", 985 + "qup-config", 986 + "qup-memory"; 987 + power-domains = <&rpmhpd SA8775P_CX>; 988 + status = "disabled"; 989 + }; 990 + 991 + spi12: spi@a94000 { 992 + compatible = "qcom,geni-spi"; 1287 993 reg = <0x0 0xa94000 0x0 0x4000>; 1288 994 #address-cells = <1>; 1289 995 #size-cells = <0>; ··· 1396 1018 1397 1019 i2c21: i2c@b80000 { 1398 1020 compatible = "qcom,geni-i2c"; 1021 + reg = <0x0 0xb80000 0x0 0x4000>; 1022 + #address-cells = <1>; 1023 + #size-cells = <0>; 1024 + interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 1025 + clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 1026 + clock-names = "se"; 1027 + interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 1028 + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 1029 + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1030 + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 1031 + <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 1032 + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1033 + interconnect-names = "qup-core", 1034 + "qup-config", 1035 + "qup-memory"; 1036 + power-domains = <&rpmhpd SA8775P_CX>; 1037 + status = "disabled"; 1038 + }; 1039 + 1040 + spi21: spi@b80000 { 1041 + compatible = "qcom,geni-spi"; 1399 1042 reg = <0x0 0xb80000 0x0 0x4000>; 1400 1043 #address-cells = <1>; 1401 1044 #size-cells = <0>;