Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
arm64: dts: qcom: sa8775p: add missing i2c nodes
Add the missing nodes for the i2c buses present on sa8775p Soc.
Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526133122.16443-3-quic_shazhuss@quicinc.com
authored by
Shazad Hussain
and committed by
Bjorn Andersson
ee2f5f90
07e3e172
+420
+420
arch/arm64/boot/dts/qcom/sa8775p.dtsi
+420
arch/arm64/boot/dts/qcom/sa8775p.dtsi
···
490
490
#size-cells = <2>;
491
491
status = "disabled";
492
492
493
+
i2c14: i2c@880000 {
494
+
compatible = "qcom,geni-i2c";
495
+
reg = <0x0 0x880000 0x0 0x4000>;
496
+
#address-cells = <1>;
497
+
#size-cells = <0>;
498
+
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
499
+
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
500
+
clock-names = "se";
501
+
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
502
+
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
503
+
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
504
+
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
505
+
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
506
+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
507
+
interconnect-names = "qup-core",
508
+
"qup-config",
509
+
"qup-memory";
510
+
power-domains = <&rpmhpd SA8775P_CX>;
511
+
status = "disabled";
512
+
};
513
+
514
+
i2c15: i2c@884000 {
515
+
compatible = "qcom,geni-i2c";
516
+
reg = <0x0 0x884000 0x0 0x4000>;
517
+
#address-cells = <1>;
518
+
#size-cells = <0>;
519
+
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
520
+
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
521
+
clock-names = "se";
522
+
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
523
+
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
524
+
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
525
+
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
526
+
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
527
+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
528
+
interconnect-names = "qup-core",
529
+
"qup-config",
530
+
"qup-memory";
531
+
power-domains = <&rpmhpd SA8775P_CX>;
532
+
status = "disabled";
533
+
};
534
+
535
+
i2c16: i2c@888000 {
536
+
compatible = "qcom,geni-i2c";
537
+
reg = <0x0 0x888000 0x0 0x4000>;
538
+
#address-cells = <1>;
539
+
#size-cells = <0>;
540
+
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
541
+
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
542
+
clock-names = "se";
543
+
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
544
+
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
545
+
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
546
+
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
547
+
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
548
+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
549
+
interconnect-names = "qup-core",
550
+
"qup-config",
551
+
"qup-memory";
552
+
power-domains = <&rpmhpd SA8775P_CX>;
553
+
status = "disabled";
554
+
};
555
+
493
556
spi16: spi@888000 {
494
557
compatible = "qcom,geni-spi";
495
558
reg = <0x0 0x00888000 0x0 0x4000>;
···
571
508
power-domains = <&rpmhpd SA8775P_CX>;
572
509
#address-cells = <1>;
573
510
#size-cells = <0>;
511
+
status = "disabled";
512
+
};
513
+
514
+
i2c17: i2c@88c000 {
515
+
compatible = "qcom,geni-i2c";
516
+
reg = <0x0 0x88c000 0x0 0x4000>;
517
+
#address-cells = <1>;
518
+
#size-cells = <0>;
519
+
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
520
+
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
521
+
clock-names = "se";
522
+
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
523
+
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
524
+
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
525
+
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
526
+
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
527
+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
528
+
interconnect-names = "qup-core",
529
+
"qup-config",
530
+
"qup-memory";
531
+
power-domains = <&rpmhpd SA8775P_CX>;
574
532
status = "disabled";
575
533
};
576
534
···
630
546
#size-cells = <0>;
631
547
status = "disabled";
632
548
};
549
+
550
+
i2c19: i2c@894000 {
551
+
compatible = "qcom,geni-i2c";
552
+
reg = <0x0 0x894000 0x0 0x4000>;
553
+
#address-cells = <1>;
554
+
#size-cells = <0>;
555
+
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
556
+
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
557
+
clock-names = "se";
558
+
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
559
+
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
560
+
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
561
+
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
562
+
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
563
+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
564
+
interconnect-names = "qup-core",
565
+
"qup-config",
566
+
"qup-memory";
567
+
power-domains = <&rpmhpd SA8775P_CX>;
568
+
status = "disabled";
569
+
};
570
+
571
+
i2c20: i2c@898000 {
572
+
compatible = "qcom,geni-i2c";
573
+
reg = <0x0 0x898000 0x0 0x4000>;
574
+
#address-cells = <1>;
575
+
#size-cells = <0>;
576
+
interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
577
+
clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
578
+
clock-names = "se";
579
+
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
580
+
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
581
+
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
582
+
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
583
+
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
584
+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
585
+
interconnect-names = "qup-core",
586
+
"qup-config",
587
+
"qup-memory";
588
+
power-domains = <&rpmhpd SA8775P_CX>;
589
+
status = "disabled";
590
+
};
633
591
};
634
592
635
593
qupv3_id_0: geniqup@9c0000 {
···
685
559
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
686
560
iommus = <&apps_smmu 0x403 0x0>;
687
561
status = "disabled";
562
+
563
+
i2c0: i2c@980000 {
564
+
compatible = "qcom,geni-i2c";
565
+
reg = <0x0 0x980000 0x0 0x4000>;
566
+
#address-cells = <1>;
567
+
#size-cells = <0>;
568
+
interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
569
+
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
570
+
clock-names = "se";
571
+
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
572
+
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
573
+
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
574
+
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
575
+
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
576
+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
577
+
interconnect-names = "qup-core",
578
+
"qup-config",
579
+
"qup-memory";
580
+
power-domains = <&rpmhpd SA8775P_CX>;
581
+
status = "disabled";
582
+
};
583
+
584
+
i2c1: i2c@984000 {
585
+
compatible = "qcom,geni-i2c";
586
+
reg = <0x0 0x984000 0x0 0x4000>;
587
+
#address-cells = <1>;
588
+
#size-cells = <0>;
589
+
interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
590
+
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
591
+
clock-names = "se";
592
+
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
593
+
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
594
+
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
595
+
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
596
+
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
597
+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
598
+
interconnect-names = "qup-core",
599
+
"qup-config",
600
+
"qup-memory";
601
+
power-domains = <&rpmhpd SA8775P_CX>;
602
+
status = "disabled";
603
+
};
604
+
605
+
i2c2: i2c@988000 {
606
+
compatible = "qcom,geni-i2c";
607
+
reg = <0x0 0x988000 0x0 0x4000>;
608
+
#address-cells = <1>;
609
+
#size-cells = <0>;
610
+
interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
611
+
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
612
+
clock-names = "se";
613
+
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
614
+
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
615
+
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
616
+
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
617
+
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
618
+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
619
+
interconnect-names = "qup-core",
620
+
"qup-config",
621
+
"qup-memory";
622
+
power-domains = <&rpmhpd SA8775P_CX>;
623
+
status = "disabled";
624
+
};
625
+
626
+
i2c3: i2c@98c000 {
627
+
compatible = "qcom,geni-i2c";
628
+
reg = <0x0 0x98c000 0x0 0x4000>;
629
+
#address-cells = <1>;
630
+
#size-cells = <0>;
631
+
interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
632
+
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
633
+
clock-names = "se";
634
+
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
635
+
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
636
+
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
637
+
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
638
+
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
639
+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
640
+
interconnect-names = "qup-core",
641
+
"qup-config",
642
+
"qup-memory";
643
+
power-domains = <&rpmhpd SA8775P_CX>;
644
+
status = "disabled";
645
+
};
646
+
647
+
i2c4: i2c@990000 {
648
+
compatible = "qcom,geni-i2c";
649
+
reg = <0x0 0x990000 0x0 0x4000>;
650
+
#address-cells = <1>;
651
+
#size-cells = <0>;
652
+
interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
653
+
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
654
+
clock-names = "se";
655
+
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
656
+
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
657
+
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
658
+
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
659
+
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
660
+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
661
+
interconnect-names = "qup-core",
662
+
"qup-config",
663
+
"qup-memory";
664
+
power-domains = <&rpmhpd SA8775P_CX>;
665
+
status = "disabled";
666
+
};
667
+
668
+
i2c5: i2c@994000 {
669
+
compatible = "qcom,geni-i2c";
670
+
reg = <0x0 0x994000 0x0 0x4000>;
671
+
#address-cells = <1>;
672
+
#size-cells = <0>;
673
+
interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
674
+
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
675
+
clock-names = "se";
676
+
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
677
+
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
678
+
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
679
+
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
680
+
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
681
+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
682
+
interconnect-names = "qup-core",
683
+
"qup-config",
684
+
"qup-memory";
685
+
power-domains = <&rpmhpd SA8775P_CX>;
686
+
status = "disabled";
687
+
};
688
688
};
689
689
690
690
qupv3_id_1: geniqup@ac0000 {
···
824
572
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
825
573
iommus = <&apps_smmu 0x443 0x0>;
826
574
status = "disabled";
575
+
576
+
i2c7: i2c@a80000 {
577
+
compatible = "qcom,geni-i2c";
578
+
reg = <0x0 0xa80000 0x0 0x4000>;
579
+
#address-cells = <1>;
580
+
#size-cells = <0>;
581
+
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
582
+
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
583
+
clock-names = "se";
584
+
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
585
+
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
586
+
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
587
+
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
588
+
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
589
+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
590
+
interconnect-names = "qup-core",
591
+
"qup-config",
592
+
"qup-memory";
593
+
power-domains = <&rpmhpd SA8775P_CX>;
594
+
status = "disabled";
595
+
};
596
+
597
+
i2c8: i2c@a84000 {
598
+
compatible = "qcom,geni-i2c";
599
+
reg = <0x0 0xa84000 0x0 0x4000>;
600
+
#address-cells = <1>;
601
+
#size-cells = <0>;
602
+
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
603
+
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
604
+
clock-names = "se";
605
+
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
606
+
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
607
+
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
608
+
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
609
+
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
610
+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
611
+
interconnect-names = "qup-core",
612
+
"qup-config",
613
+
"qup-memory";
614
+
power-domains = <&rpmhpd SA8775P_CX>;
615
+
status = "disabled";
616
+
};
617
+
618
+
i2c9: i2c@a88000 {
619
+
compatible = "qcom,geni-i2c";
620
+
reg = <0x0 0xa88000 0x0 0x4000>;
621
+
#address-cells = <1>;
622
+
#size-cells = <0>;
623
+
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
624
+
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
625
+
clock-names = "se";
626
+
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
627
+
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
628
+
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
629
+
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
630
+
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
631
+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
632
+
interconnect-names = "qup-core",
633
+
"qup-config",
634
+
"qup-memory";
635
+
power-domains = <&rpmhpd SA8775P_CX>;
636
+
status = "disabled";
637
+
};
638
+
639
+
i2c10: i2c@a8c000 {
640
+
compatible = "qcom,geni-i2c";
641
+
reg = <0x0 0xa8c000 0x0 0x4000>;
642
+
#address-cells = <1>;
643
+
#size-cells = <0>;
644
+
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
645
+
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
646
+
clock-names = "se";
647
+
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
648
+
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
649
+
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
650
+
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
651
+
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
652
+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
653
+
interconnect-names = "qup-core",
654
+
"qup-config",
655
+
"qup-memory";
656
+
power-domains = <&rpmhpd SA8775P_CX>;
657
+
status = "disabled";
658
+
};
827
659
828
660
uart10: serial@a8c000 {
829
661
compatible = "qcom,geni-uart";
···
925
589
status = "disabled";
926
590
};
927
591
592
+
i2c11: i2c@a90000 {
593
+
compatible = "qcom,geni-i2c";
594
+
reg = <0x0 0xa90000 0x0 0x4000>;
595
+
#address-cells = <1>;
596
+
#size-cells = <0>;
597
+
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
598
+
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
599
+
clock-names = "se";
600
+
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
601
+
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
602
+
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
603
+
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
604
+
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
605
+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
606
+
interconnect-names = "qup-core",
607
+
"qup-config",
608
+
"qup-memory";
609
+
power-domains = <&rpmhpd SA8775P_CX>;
610
+
status = "disabled";
611
+
};
612
+
613
+
i2c12: i2c@a94000 {
614
+
compatible = "qcom,geni-i2c";
615
+
reg = <0x0 0xa94000 0x0 0x4000>;
616
+
#address-cells = <1>;
617
+
#size-cells = <0>;
618
+
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
619
+
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
620
+
clock-names = "se";
621
+
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
622
+
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
623
+
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
624
+
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
625
+
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
626
+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
627
+
interconnect-names = "qup-core",
628
+
"qup-config",
629
+
"qup-memory";
630
+
power-domains = <&rpmhpd SA8775P_CX>;
631
+
status = "disabled";
632
+
};
633
+
928
634
uart12: serial@a94000 {
929
635
compatible = "qcom,geni-uart";
930
636
reg = <0x0 0x00a94000 0x0 0x4000>;
···
978
600
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
979
601
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
980
602
interconnect-names = "qup-core", "qup-config";
603
+
power-domains = <&rpmhpd SA8775P_CX>;
604
+
status = "disabled";
605
+
};
606
+
607
+
i2c13: i2c@a98000 {
608
+
compatible = "qcom,geni-i2c";
609
+
reg = <0x0 0xa98000 0x0 0x4000>;
610
+
#address-cells = <1>;
611
+
#size-cells = <0>;
612
+
interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
613
+
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
614
+
clock-names = "se";
615
+
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
616
+
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
617
+
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
618
+
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
619
+
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
620
+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
621
+
interconnect-names = "qup-core",
622
+
"qup-config",
623
+
"qup-memory";
981
624
power-domains = <&rpmhpd SA8775P_CX>;
982
625
status = "disabled";
983
626
};
···
1015
616
<&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>;
1016
617
iommus = <&apps_smmu 0x43 0x0>;
1017
618
status = "disabled";
619
+
620
+
i2c21: i2c@b80000 {
621
+
compatible = "qcom,geni-i2c";
622
+
reg = <0x0 0xb80000 0x0 0x4000>;
623
+
#address-cells = <1>;
624
+
#size-cells = <0>;
625
+
interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
626
+
clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
627
+
clock-names = "se";
628
+
interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
629
+
&clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
630
+
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
631
+
&config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>,
632
+
<&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
633
+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
634
+
interconnect-names = "qup-core",
635
+
"qup-config",
636
+
"qup-memory";
637
+
power-domains = <&rpmhpd SA8775P_CX>;
638
+
status = "disabled";
639
+
};
1018
640
};
1019
641
1020
642
ufs_mem_hc: ufs@1d84000 {