Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/ast: Move Gen2+ and Gen1 POST code to separate source files
Move POST code for Gen2+ and Gen1 to separate source files and
hide it in ast_2100_post() ans ast_2000_post(). With P2A
configuration, the POST logic for these chip generations has
been mingled in ast_init_dram_reg(). Hence, handle all generations
in a single change. The split simplifies both cases. Also move
the DRAM init tables for each Gen into the respective source
file. No changes to the overall logic.
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com>
Link: https://lore.kernel.org/r/20250706162816.211552-6-tzimmermann@suse.de
+478
-370
+2
drivers/gpu/drm/ast/Makefile
+2
drivers/gpu/drm/ast/Makefile
+117
drivers/gpu/drm/ast/ast_2000.c
+117
drivers/gpu/drm/ast/ast_2000.c
···
1
+
// SPDX-License-Identifier: MIT
2
+
/*
3
+
* Copyright 2012 Red Hat Inc.
4
+
*
5
+
* Permission is hereby granted, free of charge, to any person obtaining a
6
+
* copy of this software and associated documentation files (the
7
+
* "Software"), to deal in the Software without restriction, including
8
+
* without limitation the rights to use, copy, modify, merge, publish,
9
+
* distribute, sub license, and/or sell copies of the Software, and to
10
+
* permit persons to whom the Software is furnished to do so, subject to
11
+
* the following conditions:
12
+
*
13
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15
+
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16
+
* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17
+
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18
+
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19
+
* USE OR OTHER DEALINGS IN THE SOFTWARE.
20
+
*
21
+
* The above copyright notice and this permission notice (including the
22
+
* next paragraph) shall be included in all copies or substantial portions
23
+
* of the Software.
24
+
*/
25
+
/*
26
+
* Authors: Dave Airlie <airlied@redhat.com>
27
+
*/
28
+
29
+
#include <linux/delay.h>
30
+
31
+
#include "ast_dram_tables.h"
32
+
#include "ast_drv.h"
33
+
34
+
/*
35
+
* POST
36
+
*/
37
+
38
+
static const struct ast_dramstruct ast2000_dram_table_data[] = {
39
+
{ 0x0108, 0x00000000 },
40
+
{ 0x0120, 0x00004a21 },
41
+
{ 0xFF00, 0x00000043 },
42
+
{ 0x0000, 0xFFFFFFFF },
43
+
{ 0x0004, 0x00000089 },
44
+
{ 0x0008, 0x22331353 },
45
+
{ 0x000C, 0x0d07000b },
46
+
{ 0x0010, 0x11113333 },
47
+
{ 0x0020, 0x00110350 },
48
+
{ 0x0028, 0x1e0828f0 },
49
+
{ 0x0024, 0x00000001 },
50
+
{ 0x001C, 0x00000000 },
51
+
{ 0x0014, 0x00000003 },
52
+
{ 0xFF00, 0x00000043 },
53
+
{ 0x0018, 0x00000131 },
54
+
{ 0x0014, 0x00000001 },
55
+
{ 0xFF00, 0x00000043 },
56
+
{ 0x0018, 0x00000031 },
57
+
{ 0x0014, 0x00000001 },
58
+
{ 0xFF00, 0x00000043 },
59
+
{ 0x0028, 0x1e0828f1 },
60
+
{ 0x0024, 0x00000003 },
61
+
{ 0x002C, 0x1f0f28fb },
62
+
{ 0x0030, 0xFFFFFE01 },
63
+
{ 0xFFFF, 0xFFFFFFFF }
64
+
};
65
+
66
+
static void ast_post_chip_2000(struct ast_device *ast)
67
+
{
68
+
u8 j;
69
+
u32 temp, i;
70
+
const struct ast_dramstruct *dram_reg_info;
71
+
72
+
j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
73
+
74
+
if ((j & 0x80) == 0) { /* VGA only */
75
+
dram_reg_info = ast2000_dram_table_data;
76
+
ast_write32(ast, 0xf004, 0x1e6e0000);
77
+
ast_write32(ast, 0xf000, 0x1);
78
+
ast_write32(ast, 0x10100, 0xa8);
79
+
80
+
do {
81
+
;
82
+
} while (ast_read32(ast, 0x10100) != 0xa8);
83
+
84
+
while (dram_reg_info->index != 0xffff) {
85
+
if (dram_reg_info->index == 0xff00) {/* delay fn */
86
+
for (i = 0; i < 15; i++)
87
+
udelay(dram_reg_info->data);
88
+
} else {
89
+
ast_write32(ast, 0x10000 + dram_reg_info->index,
90
+
dram_reg_info->data);
91
+
}
92
+
dram_reg_info++;
93
+
}
94
+
95
+
temp = ast_read32(ast, 0x10140);
96
+
ast_write32(ast, 0x10140, temp | 0x40);
97
+
}
98
+
99
+
/* wait ready */
100
+
do {
101
+
j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
102
+
} while ((j & 0x40) == 0);
103
+
}
104
+
105
+
int ast_2000_post(struct ast_device *ast)
106
+
{
107
+
if (ast->config_mode == ast_use_p2a) {
108
+
ast_post_chip_2000(ast);
109
+
} else {
110
+
if (ast->tx_chip == AST_TX_SIL164) {
111
+
/* Enable DVO */
112
+
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80);
113
+
}
114
+
}
115
+
116
+
return 0;
117
+
}
+346
drivers/gpu/drm/ast/ast_2100.c
+346
drivers/gpu/drm/ast/ast_2100.c
···
1
+
// SPDX-License-Identifier: MIT
2
+
/*
3
+
* Copyright 2012 Red Hat Inc.
4
+
*
5
+
* Permission is hereby granted, free of charge, to any person obtaining a
6
+
* copy of this software and associated documentation files (the
7
+
* "Software"), to deal in the Software without restriction, including
8
+
* without limitation the rights to use, copy, modify, merge, publish,
9
+
* distribute, sub license, and/or sell copies of the Software, and to
10
+
* permit persons to whom the Software is furnished to do so, subject to
11
+
* the following conditions:
12
+
*
13
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15
+
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16
+
* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17
+
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18
+
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19
+
* USE OR OTHER DEALINGS IN THE SOFTWARE.
20
+
*
21
+
* The above copyright notice and this permission notice (including the
22
+
* next paragraph) shall be included in all copies or substantial portions
23
+
* of the Software.
24
+
*/
25
+
/*
26
+
* Authors: Dave Airlie <airlied@redhat.com>
27
+
*/
28
+
29
+
#include <linux/delay.h>
30
+
31
+
#include "ast_dram_tables.h"
32
+
#include "ast_drv.h"
33
+
34
+
/*
35
+
* POST
36
+
*/
37
+
38
+
static const struct ast_dramstruct ast1100_dram_table_data[] = {
39
+
{ 0x2000, 0x1688a8a8 },
40
+
{ 0x2020, 0x000041f0 },
41
+
{ 0xFF00, 0x00000043 },
42
+
{ 0x0000, 0xfc600309 },
43
+
{ 0x006C, 0x00909090 },
44
+
{ 0x0064, 0x00050000 },
45
+
{ 0x0004, 0x00000585 },
46
+
{ 0x0008, 0x0011030f },
47
+
{ 0x0010, 0x22201724 },
48
+
{ 0x0018, 0x1e29011a },
49
+
{ 0x0020, 0x00c82222 },
50
+
{ 0x0014, 0x01001523 },
51
+
{ 0x001C, 0x1024010d },
52
+
{ 0x0024, 0x00cb2522 },
53
+
{ 0x0038, 0xffffff82 },
54
+
{ 0x003C, 0x00000000 },
55
+
{ 0x0040, 0x00000000 },
56
+
{ 0x0044, 0x00000000 },
57
+
{ 0x0048, 0x00000000 },
58
+
{ 0x004C, 0x00000000 },
59
+
{ 0x0050, 0x00000000 },
60
+
{ 0x0054, 0x00000000 },
61
+
{ 0x0058, 0x00000000 },
62
+
{ 0x005C, 0x00000000 },
63
+
{ 0x0060, 0x032aa02a },
64
+
{ 0x0064, 0x002d3000 },
65
+
{ 0x0068, 0x00000000 },
66
+
{ 0x0070, 0x00000000 },
67
+
{ 0x0074, 0x00000000 },
68
+
{ 0x0078, 0x00000000 },
69
+
{ 0x007C, 0x00000000 },
70
+
{ 0x0034, 0x00000001 },
71
+
{ 0xFF00, 0x00000043 },
72
+
{ 0x002C, 0x00000732 },
73
+
{ 0x0030, 0x00000040 },
74
+
{ 0x0028, 0x00000005 },
75
+
{ 0x0028, 0x00000007 },
76
+
{ 0x0028, 0x00000003 },
77
+
{ 0x0028, 0x00000001 },
78
+
{ 0x000C, 0x00005a08 },
79
+
{ 0x002C, 0x00000632 },
80
+
{ 0x0028, 0x00000001 },
81
+
{ 0x0030, 0x000003c0 },
82
+
{ 0x0028, 0x00000003 },
83
+
{ 0x0030, 0x00000040 },
84
+
{ 0x0028, 0x00000003 },
85
+
{ 0x000C, 0x00005a21 },
86
+
{ 0x0034, 0x00007c03 },
87
+
{ 0x0120, 0x00004c41 },
88
+
{ 0xffff, 0xffffffff },
89
+
};
90
+
91
+
static const struct ast_dramstruct ast2100_dram_table_data[] = {
92
+
{ 0x2000, 0x1688a8a8 },
93
+
{ 0x2020, 0x00004120 },
94
+
{ 0xFF00, 0x00000043 },
95
+
{ 0x0000, 0xfc600309 },
96
+
{ 0x006C, 0x00909090 },
97
+
{ 0x0064, 0x00070000 },
98
+
{ 0x0004, 0x00000489 },
99
+
{ 0x0008, 0x0011030f },
100
+
{ 0x0010, 0x32302926 },
101
+
{ 0x0018, 0x274c0122 },
102
+
{ 0x0020, 0x00ce2222 },
103
+
{ 0x0014, 0x01001523 },
104
+
{ 0x001C, 0x1024010d },
105
+
{ 0x0024, 0x00cb2522 },
106
+
{ 0x0038, 0xffffff82 },
107
+
{ 0x003C, 0x00000000 },
108
+
{ 0x0040, 0x00000000 },
109
+
{ 0x0044, 0x00000000 },
110
+
{ 0x0048, 0x00000000 },
111
+
{ 0x004C, 0x00000000 },
112
+
{ 0x0050, 0x00000000 },
113
+
{ 0x0054, 0x00000000 },
114
+
{ 0x0058, 0x00000000 },
115
+
{ 0x005C, 0x00000000 },
116
+
{ 0x0060, 0x0f2aa02a },
117
+
{ 0x0064, 0x003f3005 },
118
+
{ 0x0068, 0x02020202 },
119
+
{ 0x0070, 0x00000000 },
120
+
{ 0x0074, 0x00000000 },
121
+
{ 0x0078, 0x00000000 },
122
+
{ 0x007C, 0x00000000 },
123
+
{ 0x0034, 0x00000001 },
124
+
{ 0xFF00, 0x00000043 },
125
+
{ 0x002C, 0x00000942 },
126
+
{ 0x0030, 0x00000040 },
127
+
{ 0x0028, 0x00000005 },
128
+
{ 0x0028, 0x00000007 },
129
+
{ 0x0028, 0x00000003 },
130
+
{ 0x0028, 0x00000001 },
131
+
{ 0x000C, 0x00005a08 },
132
+
{ 0x002C, 0x00000842 },
133
+
{ 0x0028, 0x00000001 },
134
+
{ 0x0030, 0x000003c0 },
135
+
{ 0x0028, 0x00000003 },
136
+
{ 0x0030, 0x00000040 },
137
+
{ 0x0028, 0x00000003 },
138
+
{ 0x000C, 0x00005a21 },
139
+
{ 0x0034, 0x00007c03 },
140
+
{ 0x0120, 0x00005061 },
141
+
{ 0xffff, 0xffffffff },
142
+
};
143
+
144
+
/*
145
+
* AST2100/2150 DLL CBR Setting
146
+
*/
147
+
#define CBR_SIZE_AST2150 ((16 << 10) - 1)
148
+
#define CBR_PASSNUM_AST2150 5
149
+
#define CBR_THRESHOLD_AST2150 10
150
+
#define CBR_THRESHOLD2_AST2150 10
151
+
#define TIMEOUT_AST2150 5000000
152
+
153
+
#define CBR_PATNUM_AST2150 8
154
+
155
+
static const u32 pattern_AST2150[14] = {
156
+
0xFF00FF00,
157
+
0xCC33CC33,
158
+
0xAA55AA55,
159
+
0xFFFE0001,
160
+
0x683501FE,
161
+
0x0F1929B0,
162
+
0x2D0B4346,
163
+
0x60767F02,
164
+
0x6FBE36A6,
165
+
0x3A253035,
166
+
0x3019686D,
167
+
0x41C6167E,
168
+
0x620152BF,
169
+
0x20F050E0
170
+
};
171
+
172
+
static u32 mmctestburst2_ast2150(struct ast_device *ast, u32 datagen)
173
+
{
174
+
u32 data, timeout;
175
+
176
+
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
177
+
ast_moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3));
178
+
timeout = 0;
179
+
do {
180
+
data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
181
+
if (++timeout > TIMEOUT_AST2150) {
182
+
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
183
+
return 0xffffffff;
184
+
}
185
+
} while (!data);
186
+
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
187
+
ast_moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3));
188
+
timeout = 0;
189
+
do {
190
+
data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
191
+
if (++timeout > TIMEOUT_AST2150) {
192
+
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
193
+
return 0xffffffff;
194
+
}
195
+
} while (!data);
196
+
data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
197
+
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
198
+
return data;
199
+
}
200
+
201
+
static int cbrtest_ast2150(struct ast_device *ast)
202
+
{
203
+
int i;
204
+
205
+
for (i = 0; i < 8; i++)
206
+
if (mmctestburst2_ast2150(ast, i))
207
+
return 0;
208
+
return 1;
209
+
}
210
+
211
+
static int cbrscan_ast2150(struct ast_device *ast, int busw)
212
+
{
213
+
u32 patcnt, loop;
214
+
215
+
for (patcnt = 0; patcnt < CBR_PATNUM_AST2150; patcnt++) {
216
+
ast_moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]);
217
+
for (loop = 0; loop < CBR_PASSNUM_AST2150; loop++) {
218
+
if (cbrtest_ast2150(ast))
219
+
break;
220
+
}
221
+
if (loop == CBR_PASSNUM_AST2150)
222
+
return 0;
223
+
}
224
+
return 1;
225
+
}
226
+
227
+
static void cbrdlli_ast2150(struct ast_device *ast, int busw)
228
+
{
229
+
u32 dll_min[4], dll_max[4], dlli, data, passcnt;
230
+
231
+
cbr_start:
232
+
dll_min[0] = 0xff;
233
+
dll_min[1] = 0xff;
234
+
dll_min[2] = 0xff;
235
+
dll_min[3] = 0xff;
236
+
dll_max[0] = 0x00;
237
+
dll_max[1] = 0x00;
238
+
dll_max[2] = 0x00;
239
+
dll_max[3] = 0x00;
240
+
passcnt = 0;
241
+
242
+
for (dlli = 0; dlli < 100; dlli++) {
243
+
ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
244
+
data = cbrscan_ast2150(ast, busw);
245
+
if (data != 0) {
246
+
if (data & 0x1) {
247
+
if (dll_min[0] > dlli)
248
+
dll_min[0] = dlli;
249
+
if (dll_max[0] < dlli)
250
+
dll_max[0] = dlli;
251
+
}
252
+
passcnt++;
253
+
} else if (passcnt >= CBR_THRESHOLD_AST2150) {
254
+
goto cbr_start;
255
+
}
256
+
}
257
+
if (dll_max[0] == 0 || (dll_max[0] - dll_min[0]) < CBR_THRESHOLD_AST2150)
258
+
goto cbr_start;
259
+
260
+
dlli = dll_min[0] + (((dll_max[0] - dll_min[0]) * 7) >> 4);
261
+
ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
262
+
}
263
+
264
+
static void ast_post_chip_2100(struct ast_device *ast)
265
+
{
266
+
u8 j;
267
+
u32 data, temp, i;
268
+
const struct ast_dramstruct *dram_reg_info;
269
+
270
+
j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
271
+
272
+
if ((j & 0x80) == 0) { /* VGA only */
273
+
if (ast->chip == AST2100 || ast->chip == AST2200)
274
+
dram_reg_info = ast2100_dram_table_data;
275
+
else
276
+
dram_reg_info = ast1100_dram_table_data;
277
+
278
+
ast_write32(ast, 0xf004, 0x1e6e0000);
279
+
ast_write32(ast, 0xf000, 0x1);
280
+
ast_write32(ast, 0x12000, 0x1688A8A8);
281
+
do {
282
+
;
283
+
} while (ast_read32(ast, 0x12000) != 0x01);
284
+
285
+
ast_write32(ast, 0x10000, 0xfc600309);
286
+
do {
287
+
;
288
+
} while (ast_read32(ast, 0x10000) != 0x01);
289
+
290
+
while (dram_reg_info->index != 0xffff) {
291
+
if (dram_reg_info->index == 0xff00) {/* delay fn */
292
+
for (i = 0; i < 15; i++)
293
+
udelay(dram_reg_info->data);
294
+
} else if (dram_reg_info->index == 0x4) {
295
+
data = dram_reg_info->data;
296
+
if (ast->dram_type == AST_DRAM_1Gx16)
297
+
data = 0x00000d89;
298
+
else if (ast->dram_type == AST_DRAM_1Gx32)
299
+
data = 0x00000c8d;
300
+
301
+
temp = ast_read32(ast, 0x12070);
302
+
temp &= 0xc;
303
+
temp <<= 2;
304
+
ast_write32(ast, 0x10000 + dram_reg_info->index, data | temp);
305
+
} else {
306
+
ast_write32(ast, 0x10000 + dram_reg_info->index,
307
+
dram_reg_info->data);
308
+
}
309
+
dram_reg_info++;
310
+
}
311
+
312
+
/* AST 2100/2150 DRAM calibration */
313
+
data = ast_read32(ast, 0x10120);
314
+
if (data == 0x5061) { /* 266Mhz */
315
+
data = ast_read32(ast, 0x10004);
316
+
if (data & 0x40)
317
+
cbrdlli_ast2150(ast, 16); /* 16 bits */
318
+
else
319
+
cbrdlli_ast2150(ast, 32); /* 32 bits */
320
+
}
321
+
322
+
temp = ast_read32(ast, 0x1200c);
323
+
ast_write32(ast, 0x1200c, temp & 0xfffffffd);
324
+
temp = ast_read32(ast, 0x12040);
325
+
ast_write32(ast, 0x12040, temp | 0x40);
326
+
}
327
+
328
+
/* wait ready */
329
+
do {
330
+
j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
331
+
} while ((j & 0x40) == 0);
332
+
}
333
+
334
+
int ast_2100_post(struct ast_device *ast)
335
+
{
336
+
if (ast->config_mode == ast_use_p2a) {
337
+
ast_post_chip_2100(ast);
338
+
} else {
339
+
if (ast->tx_chip == AST_TX_SIL164) {
340
+
/* Enable DVO */
341
+
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80);
342
+
}
343
+
}
344
+
345
+
return 0;
346
+
}
-134
drivers/gpu/drm/ast/ast_dram_tables.h
-134
drivers/gpu/drm/ast/ast_dram_tables.h
···
8
8
u32 data;
9
9
};
10
10
11
-
static const struct ast_dramstruct ast2000_dram_table_data[] = {
12
-
{ 0x0108, 0x00000000 },
13
-
{ 0x0120, 0x00004a21 },
14
-
{ 0xFF00, 0x00000043 },
15
-
{ 0x0000, 0xFFFFFFFF },
16
-
{ 0x0004, 0x00000089 },
17
-
{ 0x0008, 0x22331353 },
18
-
{ 0x000C, 0x0d07000b },
19
-
{ 0x0010, 0x11113333 },
20
-
{ 0x0020, 0x00110350 },
21
-
{ 0x0028, 0x1e0828f0 },
22
-
{ 0x0024, 0x00000001 },
23
-
{ 0x001C, 0x00000000 },
24
-
{ 0x0014, 0x00000003 },
25
-
{ 0xFF00, 0x00000043 },
26
-
{ 0x0018, 0x00000131 },
27
-
{ 0x0014, 0x00000001 },
28
-
{ 0xFF00, 0x00000043 },
29
-
{ 0x0018, 0x00000031 },
30
-
{ 0x0014, 0x00000001 },
31
-
{ 0xFF00, 0x00000043 },
32
-
{ 0x0028, 0x1e0828f1 },
33
-
{ 0x0024, 0x00000003 },
34
-
{ 0x002C, 0x1f0f28fb },
35
-
{ 0x0030, 0xFFFFFE01 },
36
-
{ 0xFFFF, 0xFFFFFFFF }
37
-
};
38
-
39
-
static const struct ast_dramstruct ast1100_dram_table_data[] = {
40
-
{ 0x2000, 0x1688a8a8 },
41
-
{ 0x2020, 0x000041f0 },
42
-
{ 0xFF00, 0x00000043 },
43
-
{ 0x0000, 0xfc600309 },
44
-
{ 0x006C, 0x00909090 },
45
-
{ 0x0064, 0x00050000 },
46
-
{ 0x0004, 0x00000585 },
47
-
{ 0x0008, 0x0011030f },
48
-
{ 0x0010, 0x22201724 },
49
-
{ 0x0018, 0x1e29011a },
50
-
{ 0x0020, 0x00c82222 },
51
-
{ 0x0014, 0x01001523 },
52
-
{ 0x001C, 0x1024010d },
53
-
{ 0x0024, 0x00cb2522 },
54
-
{ 0x0038, 0xffffff82 },
55
-
{ 0x003C, 0x00000000 },
56
-
{ 0x0040, 0x00000000 },
57
-
{ 0x0044, 0x00000000 },
58
-
{ 0x0048, 0x00000000 },
59
-
{ 0x004C, 0x00000000 },
60
-
{ 0x0050, 0x00000000 },
61
-
{ 0x0054, 0x00000000 },
62
-
{ 0x0058, 0x00000000 },
63
-
{ 0x005C, 0x00000000 },
64
-
{ 0x0060, 0x032aa02a },
65
-
{ 0x0064, 0x002d3000 },
66
-
{ 0x0068, 0x00000000 },
67
-
{ 0x0070, 0x00000000 },
68
-
{ 0x0074, 0x00000000 },
69
-
{ 0x0078, 0x00000000 },
70
-
{ 0x007C, 0x00000000 },
71
-
{ 0x0034, 0x00000001 },
72
-
{ 0xFF00, 0x00000043 },
73
-
{ 0x002C, 0x00000732 },
74
-
{ 0x0030, 0x00000040 },
75
-
{ 0x0028, 0x00000005 },
76
-
{ 0x0028, 0x00000007 },
77
-
{ 0x0028, 0x00000003 },
78
-
{ 0x0028, 0x00000001 },
79
-
{ 0x000C, 0x00005a08 },
80
-
{ 0x002C, 0x00000632 },
81
-
{ 0x0028, 0x00000001 },
82
-
{ 0x0030, 0x000003c0 },
83
-
{ 0x0028, 0x00000003 },
84
-
{ 0x0030, 0x00000040 },
85
-
{ 0x0028, 0x00000003 },
86
-
{ 0x000C, 0x00005a21 },
87
-
{ 0x0034, 0x00007c03 },
88
-
{ 0x0120, 0x00004c41 },
89
-
{ 0xffff, 0xffffffff },
90
-
};
91
-
92
-
static const struct ast_dramstruct ast2100_dram_table_data[] = {
93
-
{ 0x2000, 0x1688a8a8 },
94
-
{ 0x2020, 0x00004120 },
95
-
{ 0xFF00, 0x00000043 },
96
-
{ 0x0000, 0xfc600309 },
97
-
{ 0x006C, 0x00909090 },
98
-
{ 0x0064, 0x00070000 },
99
-
{ 0x0004, 0x00000489 },
100
-
{ 0x0008, 0x0011030f },
101
-
{ 0x0010, 0x32302926 },
102
-
{ 0x0018, 0x274c0122 },
103
-
{ 0x0020, 0x00ce2222 },
104
-
{ 0x0014, 0x01001523 },
105
-
{ 0x001C, 0x1024010d },
106
-
{ 0x0024, 0x00cb2522 },
107
-
{ 0x0038, 0xffffff82 },
108
-
{ 0x003C, 0x00000000 },
109
-
{ 0x0040, 0x00000000 },
110
-
{ 0x0044, 0x00000000 },
111
-
{ 0x0048, 0x00000000 },
112
-
{ 0x004C, 0x00000000 },
113
-
{ 0x0050, 0x00000000 },
114
-
{ 0x0054, 0x00000000 },
115
-
{ 0x0058, 0x00000000 },
116
-
{ 0x005C, 0x00000000 },
117
-
{ 0x0060, 0x0f2aa02a },
118
-
{ 0x0064, 0x003f3005 },
119
-
{ 0x0068, 0x02020202 },
120
-
{ 0x0070, 0x00000000 },
121
-
{ 0x0074, 0x00000000 },
122
-
{ 0x0078, 0x00000000 },
123
-
{ 0x007C, 0x00000000 },
124
-
{ 0x0034, 0x00000001 },
125
-
{ 0xFF00, 0x00000043 },
126
-
{ 0x002C, 0x00000942 },
127
-
{ 0x0030, 0x00000040 },
128
-
{ 0x0028, 0x00000005 },
129
-
{ 0x0028, 0x00000007 },
130
-
{ 0x0028, 0x00000003 },
131
-
{ 0x0028, 0x00000001 },
132
-
{ 0x000C, 0x00005a08 },
133
-
{ 0x002C, 0x00000842 },
134
-
{ 0x0028, 0x00000001 },
135
-
{ 0x0030, 0x000003c0 },
136
-
{ 0x0028, 0x00000003 },
137
-
{ 0x0030, 0x00000040 },
138
-
{ 0x0028, 0x00000003 },
139
-
{ 0x000C, 0x00005a21 },
140
-
{ 0x0034, 0x00007c03 },
141
-
{ 0x0120, 0x00005061 },
142
-
{ 0xffff, 0xffffffff },
143
-
};
144
-
145
11
#endif
+6
drivers/gpu/drm/ast/ast_drv.h
+6
drivers/gpu/drm/ast/ast_drv.h
···
417
417
418
418
int ast_mm_init(struct ast_device *ast);
419
419
420
+
/* ast_2000.c */
421
+
int ast_2000_post(struct ast_device *ast);
422
+
423
+
/* ast_2100.c */
424
+
int ast_2100_post(struct ast_device *ast);
425
+
420
426
/* ast_2300.c */
421
427
int ast_2300_post(struct ast_device *ast);
422
428
+7
-236
drivers/gpu/drm/ast/ast_post.c
+7
-236
drivers/gpu/drm/ast/ast_post.c
···
31
31
32
32
#include <drm/drm_print.h>
33
33
34
-
#include "ast_dram_tables.h"
35
34
#include "ast_drv.h"
36
35
#include "ast_post.h"
37
36
···
110
111
__ast_moutdwm(ast->regs, r, v);
111
112
}
112
113
113
-
/*
114
-
* AST2100/2150 DLL CBR Setting
115
-
*/
116
-
#define CBR_SIZE_AST2150 ((16 << 10) - 1)
117
-
#define CBR_PASSNUM_AST2150 5
118
-
#define CBR_THRESHOLD_AST2150 10
119
-
#define CBR_THRESHOLD2_AST2150 10
120
-
#define TIMEOUT_AST2150 5000000
121
-
122
-
#define CBR_PATNUM_AST2150 8
123
-
124
-
static const u32 pattern_AST2150[14] = {
125
-
0xFF00FF00,
126
-
0xCC33CC33,
127
-
0xAA55AA55,
128
-
0xFFFE0001,
129
-
0x683501FE,
130
-
0x0F1929B0,
131
-
0x2D0B4346,
132
-
0x60767F02,
133
-
0x6FBE36A6,
134
-
0x3A253035,
135
-
0x3019686D,
136
-
0x41C6167E,
137
-
0x620152BF,
138
-
0x20F050E0
139
-
};
140
-
141
-
static u32 mmctestburst2_ast2150(struct ast_device *ast, u32 datagen)
142
-
{
143
-
u32 data, timeout;
144
-
145
-
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
146
-
ast_moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3));
147
-
timeout = 0;
148
-
do {
149
-
data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
150
-
if (++timeout > TIMEOUT_AST2150) {
151
-
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
152
-
return 0xffffffff;
153
-
}
154
-
} while (!data);
155
-
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
156
-
ast_moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3));
157
-
timeout = 0;
158
-
do {
159
-
data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
160
-
if (++timeout > TIMEOUT_AST2150) {
161
-
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
162
-
return 0xffffffff;
163
-
}
164
-
} while (!data);
165
-
data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
166
-
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
167
-
return data;
168
-
}
169
-
170
-
#if 0 /* unused in DDX driver - here for completeness */
171
-
static u32 mmctestsingle2_ast2150(struct ast_device *ast, u32 datagen)
172
-
{
173
-
u32 data, timeout;
174
-
175
-
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
176
-
ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
177
-
timeout = 0;
178
-
do {
179
-
data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
180
-
if (++timeout > TIMEOUT_AST2150) {
181
-
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
182
-
return 0xffffffff;
183
-
}
184
-
} while (!data);
185
-
data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
186
-
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
187
-
return data;
188
-
}
189
-
#endif
190
-
191
-
static int cbrtest_ast2150(struct ast_device *ast)
192
-
{
193
-
int i;
194
-
195
-
for (i = 0; i < 8; i++)
196
-
if (mmctestburst2_ast2150(ast, i))
197
-
return 0;
198
-
return 1;
199
-
}
200
-
201
-
static int cbrscan_ast2150(struct ast_device *ast, int busw)
202
-
{
203
-
u32 patcnt, loop;
204
-
205
-
for (patcnt = 0; patcnt < CBR_PATNUM_AST2150; patcnt++) {
206
-
ast_moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]);
207
-
for (loop = 0; loop < CBR_PASSNUM_AST2150; loop++) {
208
-
if (cbrtest_ast2150(ast))
209
-
break;
210
-
}
211
-
if (loop == CBR_PASSNUM_AST2150)
212
-
return 0;
213
-
}
214
-
return 1;
215
-
}
216
-
217
-
218
-
static void cbrdlli_ast2150(struct ast_device *ast, int busw)
219
-
{
220
-
u32 dll_min[4], dll_max[4], dlli, data, passcnt;
221
-
222
-
cbr_start:
223
-
dll_min[0] = dll_min[1] = dll_min[2] = dll_min[3] = 0xff;
224
-
dll_max[0] = dll_max[1] = dll_max[2] = dll_max[3] = 0x0;
225
-
passcnt = 0;
226
-
227
-
for (dlli = 0; dlli < 100; dlli++) {
228
-
ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
229
-
data = cbrscan_ast2150(ast, busw);
230
-
if (data != 0) {
231
-
if (data & 0x1) {
232
-
if (dll_min[0] > dlli)
233
-
dll_min[0] = dlli;
234
-
if (dll_max[0] < dlli)
235
-
dll_max[0] = dlli;
236
-
}
237
-
passcnt++;
238
-
} else if (passcnt >= CBR_THRESHOLD_AST2150)
239
-
goto cbr_start;
240
-
}
241
-
if (dll_max[0] == 0 || (dll_max[0]-dll_min[0]) < CBR_THRESHOLD_AST2150)
242
-
goto cbr_start;
243
-
244
-
dlli = dll_min[0] + (((dll_max[0] - dll_min[0]) * 7) >> 4);
245
-
ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
246
-
}
247
-
248
-
249
-
250
-
static void ast_init_dram_reg(struct ast_device *ast)
251
-
{
252
-
u8 j;
253
-
u32 data, temp, i;
254
-
const struct ast_dramstruct *dram_reg_info;
255
-
256
-
j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
257
-
258
-
if ((j & 0x80) == 0) { /* VGA only */
259
-
if (IS_AST_GEN1(ast)) {
260
-
dram_reg_info = ast2000_dram_table_data;
261
-
ast_write32(ast, 0xf004, 0x1e6e0000);
262
-
ast_write32(ast, 0xf000, 0x1);
263
-
ast_write32(ast, 0x10100, 0xa8);
264
-
265
-
do {
266
-
;
267
-
} while (ast_read32(ast, 0x10100) != 0xa8);
268
-
} else { /* GEN2/GEN3 */
269
-
if (ast->chip == AST2100 || ast->chip == AST2200)
270
-
dram_reg_info = ast2100_dram_table_data;
271
-
else
272
-
dram_reg_info = ast1100_dram_table_data;
273
-
274
-
ast_write32(ast, 0xf004, 0x1e6e0000);
275
-
ast_write32(ast, 0xf000, 0x1);
276
-
ast_write32(ast, 0x12000, 0x1688A8A8);
277
-
do {
278
-
;
279
-
} while (ast_read32(ast, 0x12000) != 0x01);
280
-
281
-
ast_write32(ast, 0x10000, 0xfc600309);
282
-
do {
283
-
;
284
-
} while (ast_read32(ast, 0x10000) != 0x01);
285
-
}
286
-
287
-
while (dram_reg_info->index != 0xffff) {
288
-
if (dram_reg_info->index == 0xff00) {/* delay fn */
289
-
for (i = 0; i < 15; i++)
290
-
udelay(dram_reg_info->data);
291
-
} else if (dram_reg_info->index == 0x4 && !IS_AST_GEN1(ast)) {
292
-
data = dram_reg_info->data;
293
-
if (ast->dram_type == AST_DRAM_1Gx16)
294
-
data = 0x00000d89;
295
-
else if (ast->dram_type == AST_DRAM_1Gx32)
296
-
data = 0x00000c8d;
297
-
298
-
temp = ast_read32(ast, 0x12070);
299
-
temp &= 0xc;
300
-
temp <<= 2;
301
-
ast_write32(ast, 0x10000 + dram_reg_info->index, data | temp);
302
-
} else
303
-
ast_write32(ast, 0x10000 + dram_reg_info->index, dram_reg_info->data);
304
-
dram_reg_info++;
305
-
}
306
-
307
-
/* AST 2100/2150 DRAM calibration */
308
-
data = ast_read32(ast, 0x10120);
309
-
if (data == 0x5061) { /* 266Mhz */
310
-
data = ast_read32(ast, 0x10004);
311
-
if (data & 0x40)
312
-
cbrdlli_ast2150(ast, 16); /* 16 bits */
313
-
else
314
-
cbrdlli_ast2150(ast, 32); /* 32 bits */
315
-
}
316
-
317
-
switch (AST_GEN(ast)) {
318
-
case 1:
319
-
temp = ast_read32(ast, 0x10140);
320
-
ast_write32(ast, 0x10140, temp | 0x40);
321
-
break;
322
-
case 2:
323
-
case 3:
324
-
temp = ast_read32(ast, 0x1200c);
325
-
ast_write32(ast, 0x1200c, temp & 0xfffffffd);
326
-
temp = ast_read32(ast, 0x12040);
327
-
ast_write32(ast, 0x12040, temp | 0x40);
328
-
break;
329
-
default:
330
-
break;
331
-
}
332
-
}
333
-
334
-
/* wait ready */
335
-
do {
336
-
j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
337
-
} while ((j & 0x40) == 0);
338
-
}
339
-
340
114
int ast_post_gpu(struct ast_device *ast)
341
115
{
342
116
int ret;
···
128
356
ret = ast_2300_post(ast);
129
357
if (ret)
130
358
return ret;
359
+
} else if (AST_GEN(ast) >= 2) {
360
+
ret = ast_2100_post(ast);
361
+
if (ret)
362
+
return ret;
131
363
} else {
132
-
if (ast->config_mode == ast_use_p2a) {
133
-
ast_init_dram_reg(ast);
134
-
} else {
135
-
if (ast->tx_chip == AST_TX_SIL164) {
136
-
/* Enable DVO */
137
-
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80);
138
-
}
139
-
}
364
+
ret = ast_2000_post(ast);
365
+
if (ret)
366
+
return ret;
140
367
}
141
368
142
369
return 0;