tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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clk: renesas: r9a09g056: Add clocks and resets for Mali-G31 GPU

Add clock and reset support for the Mali-G31 GPU on the Renesas RZ/V2N
(R9A09G056) SoC. This includes adding clock sources required for the
module clocks.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250513154635.273664-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Lad Prabhakar and committed by
Geert Uytterhoeven 1bf4adbb e018f9f8

+16
+16
drivers/clk/renesas/r9a09g056-cpg.c
··· 29 29 CLK_PLLDTY, 30 30 CLK_PLLCA55, 31 31 CLK_PLLETH, 32 + CLK_PLLGPU, 32 33 33 34 /* Internal Core Clocks */ 34 35 CLK_PLLCM33_DIV16, ··· 37 36 CLK_PLLCLN_DIV8, 38 37 CLK_PLLCLN_DIV16, 39 38 CLK_PLLDTY_ACPU, 39 + CLK_PLLDTY_ACPU_DIV2, 40 40 CLK_PLLDTY_ACPU_DIV4, 41 41 CLK_PLLDTY_DIV8, 42 42 CLK_PLLETH_DIV_250_FIX, ··· 48 46 CLK_SMUX2_GBE0_RXCLK, 49 47 CLK_SMUX2_GBE1_TXCLK, 50 48 CLK_SMUX2_GBE1_RXCLK, 49 + CLK_PLLGPU_GEAR, 51 50 52 51 /* Module Clocks */ 53 52 MOD_CLK_BASE, ··· 96 93 DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), 97 94 DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55), 98 95 DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3), 96 + DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU), 99 97 100 98 /* Internal Core Clocks */ 101 99 DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), ··· 106 102 DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16), 107 103 108 104 DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64), 105 + DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2), 109 106 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4), 110 107 DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8), 111 108 ··· 120 115 DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk), 121 116 DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk), 122 117 DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk), 118 + 119 + DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64), 123 120 124 121 /* Core Clocks */ 125 122 DEF_FIXED("sys_0_pclk", R9A09G056_SYS_0_PCLK, CLK_QEXTAL, 1, 1), ··· 243 236 BUS_MSTOP(8, BIT(6))), 244 237 DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3, 245 238 BUS_MSTOP(8, BIT(6))), 239 + DEF_MOD("gpu_0_clk", CLK_PLLGPU_GEAR, 15, 0, 7, 16, 240 + BUS_MSTOP(3, BIT(4))), 241 + DEF_MOD("gpu_0_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17, 242 + BUS_MSTOP(3, BIT(4))), 243 + DEF_MOD("gpu_0_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18, 244 + BUS_MSTOP(3, BIT(4))), 246 245 }; 247 246 248 247 static const struct rzv2h_reset r9a09g056_resets[] __initconst = { ··· 282 269 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */ 283 270 DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */ 284 271 DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */ 272 + DEF_RST(13, 13, 6, 14), /* GPU_0_RESETN */ 273 + DEF_RST(13, 14, 6, 15), /* GPU_0_AXI_RESETN */ 274 + DEF_RST(13, 15, 6, 16), /* GPU_0_ACE_RESETN */ 285 275 }; 286 276 287 277 const struct rzv2h_cpg_info r9a09g056_cpg_info __initconst = {