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clk: renesas: r9a09g056: Add clock and reset entries for WDT controllers

Add module clock and reset definitions for WDT0-3, which are available
on the RZ/V2N (R9A09G056) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250513154635.273664-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Lad Prabhakar and committed by
Geert Uytterhoeven e018f9f8 d3c25dd1

+20
+20
drivers/clk/renesas/r9a09g056-cpg.c
··· 152 152 BUS_MSTOP(11, BIT(15))), 153 153 DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10, 154 154 BUS_MSTOP(12, BIT(0))), 155 + DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11, 156 + BUS_MSTOP(3, BIT(10))), 157 + DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12, 158 + BUS_MSTOP(3, BIT(10))), 159 + DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13, 160 + BUS_MSTOP(1, BIT(0))), 161 + DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14, 162 + BUS_MSTOP(1, BIT(0))), 163 + DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15, 164 + BUS_MSTOP(5, BIT(12))), 165 + DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16, 166 + BUS_MSTOP(5, BIT(12))), 167 + DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17, 168 + BUS_MSTOP(5, BIT(13))), 169 + DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18, 170 + BUS_MSTOP(5, BIT(13))), 155 171 DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15, 156 172 BUS_MSTOP(3, BIT(14))), 157 173 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19, ··· 250 234 DEF_RST(7, 2, 3, 3), /* GTM_5_PRESETZ */ 251 235 DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */ 252 236 DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */ 237 + DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */ 238 + DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */ 239 + DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */ 240 + DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */ 253 241 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */ 254 242 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */ 255 243 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */