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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
clk: renesas: r9a07g043: Add clock and reset entries for CANFD
Add clock and reset entries for CANFD in CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220425095244.156720-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
authored by
Biju Das
and committed by
Geert Uytterhoeven
1cbda377
666b5a01
+5
+5
drivers/clk/renesas/r9a07g043-cpg.c
+5
drivers/clk/renesas/r9a07g043-cpg.c
···
100
100
CLK_DIVIDER_HIWORD_MASK),
101
101
DEF_DIV("P0", R9A07G043_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A,
102
102
dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
103
+
DEF_FIXED("P0_DIV2", R9A07G043_CLK_P0_DIV2, R9A07G043_CLK_P0, 1, 2),
103
104
DEF_DIV("P1", R9A07G043_CLK_P1, CLK_PLL3_DIV2_4,
104
105
DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
105
106
DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G043_CLK_P1, 1, 2),
···
199
198
0x588, 0),
200
199
DEF_MOD("sci1", R9A07G043_SCI1_CLKP, R9A07G043_CLK_P0,
201
200
0x588, 1),
201
+
DEF_MOD("canfd", R9A07G043_CANFD_PCLK, R9A07G043_CLK_P0,
202
+
0x594, 0),
202
203
DEF_MOD("gpio", R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK,
203
204
0x598, 0),
204
205
};
···
234
231
DEF_RST(R9A07G043_SCIF4_RST_SYSTEM_N, 0x884, 4),
235
232
DEF_RST(R9A07G043_SCI0_RST, 0x888, 0),
236
233
DEF_RST(R9A07G043_SCI1_RST, 0x888, 1),
234
+
DEF_RST(R9A07G043_CANFD_RSTP_N, 0x894, 0),
235
+
DEF_RST(R9A07G043_CANFD_RSTC_N, 0x894, 1),
237
236
DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0),
238
237
DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1),
239
238
DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2),